KR20180048319A - 원자층 퇴적에 의한 기판 상의 전이 금속 질화물 막의 형성 방법 및 관련 반도체 소자 구조물들 - Google Patents

원자층 퇴적에 의한 기판 상의 전이 금속 질화물 막의 형성 방법 및 관련 반도체 소자 구조물들 Download PDF

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KR20180048319A
KR20180048319A KR1020170135856A KR20170135856A KR20180048319A KR 20180048319 A KR20180048319 A KR 20180048319A KR 1020170135856 A KR1020170135856 A KR 1020170135856A KR 20170135856 A KR20170135856 A KR 20170135856A KR 20180048319 A KR20180048319 A KR 20180048319A
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transition metal
nitride film
metal nitride
precursor
substrate
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페트리 라이사넨
마이클 유진 기븐스
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에이에스엠 아이피 홀딩 비.브이.
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Publication of KR20180048319A publication Critical patent/KR20180048319A/ko
Priority to KR1020230007650A priority Critical patent/KR102661251B1/ko
Priority to KR1020230007653A priority patent/KR102662958B1/ko

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Abstract

원자층 퇴적법에 의해 기판 상에 전이 금속 질화물 막을 형성하기 위한 방법들 및 관련 반도체 소자 구조물들이 제공된다. 일부 실시예들에서, 방법들은 상기 기판을 전이 금속 전구체를 포함하는 제1 기상 반응물과 접촉시키는 단계 및 상기 기판을 알킬-히드라진(alkyl-hydrazine) 전구체를 포함하는 제2 기상 반응물과 접촉시키는 단계를 포함할 수 있다. 일부 실시예들에서, 관련된 반도체 소자 구조물들은 PMOS 트랜지스터 게이트 구조물을 포함할 수 있고, 상기 PMOS 트랜지스터 게이트 구조물은 전이 금속 질화물 막과, 상기 전이 금속 질화물 막과 반도체 바디 사이에 배치되는 게이트 유전체를 포함할 수 있다. 상기 전이 금속 질화물 막은 지배적인 (200) 결정학적 배향을 포함한다.

Description

원자층 퇴적에 의한 기판 상의 전이 금속 질화물 막의 형성 방법 및 관련 반도체 소자 구조물들{Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures}
[1] 본 개시는 2016년 11월 1일 출원된 "METHODS FOR FORMING A TRANSITION METAL NITRIDE FILM ON A SUBSTRATE BY ATOMIC LAYER DEPOSITION AND RELATED SEMICONDUCTOR DEVICE STRUCTURES"라는 발명의 명칭의 미국 임시 특허 출원 제62/415,842호의 이익을 주장하며, 이는 여기에 참조문헌으로서 병합된다.
[2] 본 개시는 일반적으로 원자층 퇴적에 의하여 기판 상에 전이 금속 질화물 막을 형성하기 위한 방법들 및 관련 반도체 소자 구조물들에 관한 것이다.
[3] 금속 산화물 반도체(MOS) 기술은 게이트 전극 물질로서 통상적으로 n-형 도핑된 폴리실리콘을 사용해왔다. 그러나, 도핑된 폴리실리콘은 향상된 노드의 어플리케이션들을 위하여 이상적인 게이트 전극 물질이 아닐 수 있다. 예를 들어, 도핑된 폴리실리콘이 도전성이지만, 바이어스 조건들 하에서 캐리어들이 공핍될(depleted) 수 있는 표면 영역이 여전히 존재할 수 있다. 이러한 영역은 일반적으로 게이트 공핍으로 지칭되며, 여분의 게이트 절연체 두께로서 나타날 수 있고, 등가 산화물 두께에 기여할 수 있다. 게이트 공핍 영역이 수 옹스트롬(Å)의 오더로 얇을 수 있는 한편, 향상된 노드의 어플리케이션들에서 게이트 산화물 두께들이 감소됨에 따라 이는 중요해질 수 있다. 추가적인 예시로서, 폴리실리콘은 NMOS 및 PMOS 모두를 위한 이상적인 유효 일함수(eWF)를 나타내지 않는다. 도핑된 폴리실리콘의 비이상적인 유효 일함수를 극복하기 위하여, 문턱 전압 조절 주입법이 사용될 수 있다. 그러나, 향상된 노드의 어플리케이션들에서 소자 기하구조들이 감소함에 따라 문턱 전압 조절 주입 공정들은 상당히 복잡하고 비실용적이 될 수 있다.
[4] 도핑된 폴리실리콘 게이트 전극들과 연관된 문제들을 극복하기 위하여, 비이상적인 도핑된 폴리실리콘 게이트 물질은 예를 들어 전이 금속 질화물과 같은 대안의 물질로 대체될 수 있다. 예를 들어, 전이 금속 질화물의 특성들은 NMOS 및 PMOS 소자들 모두를 위한 더욱 이상적인 유효 일함수를 갖는 게이트 전극 구조물을 제공하도록 개조될 수 있고, 여기서 게이트 전극의 유효 일함수, 즉 전자를 추출하는 데 필요한 에너지는 반도체 물질의 배리어 높이와 호환 가능해야 한다. 예를 들어, PMOS 소자들의 경우에는, 요구되는 유효 일함수는 대략 5.0 eV이다.
[5] 원자층 퇴적(ALD)은 예를 들어, 탄탈륨 질화물(TaN), 티타늄 질화물(TiN), 텅스텐 질화물(WN), 및 니오븀 질화물(NbN)과 같은 전이 금속 질화물 막들의 퇴적을 위하여 사용될 수 있다. 그러나, 공지의 전구체들을 사용하여 ALD 형성된 전이 금속 질화물 막들의 전자적 또는 결정학적 특성들의 개조는 ALD 공정의 자기-제한적 속성에 기인하여 제한될 수 있다.
본 발명의 목적은 전술한 문제들을 극복하기 위한 것이다.
[6] 본 요약은 단순화된 형태로 개념들의 선택을 소개하기 위하여 제공된다. 이러한 개념들은 아래에서 본 개시의 예시적 실시예들의 상세한 설명에서 더욱 상세히 설명된다. 이러한 요약은 청구되는 기술적 특징의 주요 특징들 또는 필수 특징들을 식별하도록 의도되지 않으며, 청구되는 기술적 특징의 범위를 한정하는 데 사용되도록 의도되지 않는다.
[7] 일부 실시예들에서, 원자층 퇴적에 의해 기판 상에 전이 금속 질화물 막을 형성하기 위한 방법들이 제공된다. 상기 방법들은 상기 기판을 전이 금속 전구체를 포함하는 제1 기상 반응물과 접촉시키는 단계 및 상기 기판을 알킬-히드라진 전구체를 포함하는 제2 기상 반응물과 접촉시키는 단계를 포함할 수 있다.
[8] 일부 실시예들에서, 반도체 소자 구조물들이 제공된다. 반도체 소자 구조물들은 PMOS 트랜지스터 게이트 구조물을 포함할 수 있고, PMOS 트랜지스터 게이트 구조물은 전이 금속 질화물 막, 및 전이 금속 질화물 막과 반도체 바디 사이의 게이트 유전체를 포함한다. 일부 실시예들에서, 전이 금속 질화물 막은 지배적인(predominant) (200) 결정학적 배향을 포함한다.
[9] 본 발명 및 종래 기술에 대비하여 얻어질 수 있는 이점들을 요약하기 위한 목적들로서, 본 발명의 특정한 목적들 및 이점들이 위에서 설명되었다. 물론, 이러한 목적들 및 이점들 모두가 본 발명의 임의의 특정한 실시예에 따라 얻어질 수 있을 필요는 없다는 점이 이해되어야 한다. 따라서, 예를 들어 당업자는 본 발명이 여기서 개시되거나 암시될 수 있는 것과 같은 다른 목적들 또는 이점들을 필수적으로 달성하지 않고 여기서 개시되거나 암시되는 하나의 이점 또는 일 군의 이점들을 달성하거나 최적화하는 방식으로 구체화되거나 수행될 수 있다는 점을 인식할 것이다.
[10] 실시예들 모두가 여기 개시된 본 발명의 범위 내에 있을 것이 의도된다. 이러한 및 다른 실시예들은 첨부된 도면들을 참조로 한 특정한 실시예들의 하기의 상세한 설명으로부터 당업자에게 즉각적으로 명백해질 것이며, 본 발명이 개시된 임의의 특정한 실시예(들)에 한정되는 것은 아니다.
[11] 본 명세서가 본 발명의 실시예들로 간주되는 것을 특별히 지시하고 명백하게 주장하는 청구항들로 마무리짓는 한편, 본 개시의 실시예들의 이점들이 첨부한 도면들과 결합하여 읽힐 때 본 개시의 실시예들의 특정한 예시의 상세한 설명으로부터 더욱 즉각적으로 확인될 수 있다.
[12] 도 1은 본 개시의 실시예들에 따라 형성된 티타늄 질화물 막들의 X-선 회절(XRD) 스캔들을 나타내는 그래프이다.
[13] 도 2는 본 개시의 실시예들에 따라 형성된 반도체 구조물의 단순화된 단면도이다.
[14] 도 3은 티타늄 질화물 막을 포함하는 다양한 게이트 전극 구조물들의, 티타늄 질화물 막 두께의 함수로서 유효 일함수(eWF)를 나타내는 그래프이다.
[15] 도 4는 본 개시의 실시예들을 수행하도록 구성된 반응 시스템을 나타낸다.
[16] 여기 표현되는 도시들은 임의의 특정한 물질, 구조물, 또는 소자의 실제 도면임을 의미하는 것은 아니며, 단순히 본 개시의 실시예들을 설명하는 데 사용되는 이상화된 대표도들이다.
[17] 여기 사용된 바와 같이, 용어 "원자층 퇴적(atomic layer deposition, ALD)"은 퇴적 사이클들, 바람직하게는 복수의 연속적 퇴적 사이클들이 공정 챔버 내에서 수행되는 기상 퇴적 공정을 가리킬 수 있다. 일반적으로, 각각의 사이클 동안 전구체가 퇴적 표면에 화학 흡착되고(예를 들어, 기판 표면 또는 이전의 ALD 사이클로부터의 물질과 같은 이전에 퇴적된 하부 표면), 추가적인 전구체와 즉각적으로 반응하지 않는 모노레이어(monolayer) 또는 서브-모노레이어를 형성한다(즉, 자기-제한적 반응). 그 이후, 만약 필요하다면 반응물(예를 들어, 다른 전구체 또는 반응 가스)이 퇴적 표면 상에서 화학 흡착된 전구체를 요구되는 물질로 변환하는 데 사용하기 위하여 공정 챔버 내에 후속적으로 도입될 수 있다. 일반적으로, 이러한 반응물은 전구체와의 추가적인 반응이 가능하다. 더욱이, 퍼지 단계들은 또한 공정 챔버로부터 여분의 전구체를 제거하고 및/또는 화학흡착된 전구체의 변환 이후에 공정 챔버로부터 여분의 반응물 및/또는 반응 부산물을 제거하도록 각각의 사이클 동안 사용될 수 있다. 더욱이, 여기 사용된 바와 같이 용어 "원자층 퇴적"은 또한 전구체 조성(들), 반응성 가스, 및 퍼지(예를 들어 비활성 캐리어) 가스의 교대되는 펄스들과 함께 수행될 때 "화학 기상 원자층 퇴적", "원자층 에피택시(atomic layer epitaxy, ALE)", 분자 빔 에피택시(MBE), 가스 소스 MBE, 유기금속 MBE, 및 화학 빔 에피택시와 같은 관련된 용어들에 의해 지정되는 공정들을 포함하도록 의도된다.
[18] 여기 사용된 바와 같이, 용어 "기판"은 임의의 하부 물질 또는 사용될 수 있거나 그 상부에 소자, 회로 또는 막이 형성될 수 있는 물질들을 가리킬 수 있다.
[19] 여기 사용된 바와 같이, 용어 "알킬-히드라진(alkyl-hydrazine)"은 알킬 기능기를 포함할 수 있고 또한 추가적인 기능기들을 포함할 수 있는 히드라진(N2H4)의 유도체를 가리킬 수 있다.
[20] 본 개시는 전이 금속 질화물 막을 형성하는 데 사용될 수 있거나 전이 금속 질화물 막을 포함하는 방법들 및 소자 구조물들을 포함한다. 전이 금속 질화물 막들의 ALD 내에서 사용될 수 있는 존재하는 전구체들은 ALD 전이 금속 질화물 막의 특정한 특성들을 조절하기 불가능함으로 인하여 많은 제약들을 가질 수 있고, 이러한 특성들은 유효 일함수 및 결정학적 배향을 포함할 수 있다. 예를 들어, 게이트 전극의 유효 일함수는 그 두께의 함수로서 달라질 수 있고, 즉 게이트 전극의 유효 일함수가 게이트 전극을 포함하는 물질들의 감소되는 두께에 따라 감소되거나 증가될 수 있다는 점이 알려져 있다. 향상된 노드의 어플리케이션들에서 소자 기하 구조들이 감소함에 따라, 예를 들어 게이트 전극과 같은 대응되는 소자 막들의 두께 또한 상기 막의 유효 일함수의 대응되는 변화에 따라 감소될 수 있다. 감소된 두께에서의 게이트 전극의 유효 일함수의 이러한 변화는 NMOS 및 PMOS 소자 구조물들을 위한 비이상적 유효 일함수를 유발할 수 있다. 그러므로 방법들 및 구조물들이 더욱 요구되는 전이 금속 질화물 막을 제공할 필요가 있다. 이러한 방법들 및 구조물들의 예시들이 아래에서 더욱 상세하게 개시된다.
[21] ALD는 일반적으로 자기-제한적 반응들에 기초하며, 여기서 순차적이고 교대하는 반응물 펄스들이 퇴적 사이클마다 물질의 대략 일 원자(또는 분자) 모노레이어를 퇴적하는 데 사용된다. 일반적으로 하나의 반응물의 흡착된 층이 동일한 반응물의 기상 반응물과 비반응성인 표면 터미네이션을 남기도록, 퇴적 조건들 및 전구체들은 자기-포화 반응들을 제공하도록 선택된다. 기판은 연속된 퇴적을 가능하게 하도록 이전의 터미네이션과 반응하는 다른 반응물과 후속하여 접촉된다. 따라서, 교대하는 펄스들의 각각의 사이클이 일반적으로 요구되는 물질의 대략 하나의 모노레이어 이상 남기지 않는다. 그러나, 앞서 언급한 바와 같이, 당업자는 예를 들어 상기 공정의 교대하는 속성에도 불구하고 일부 기상 반응들이 일어난다면 하나 또는 그 이상의 ALD 사이클들 내에서 물질의 일 모노레이어 이상이 퇴적될 수 있다는 점을 인식할 것이다.
[22] 전이 금속 질화물 막들을 퇴적하기 위한 ALD 타입의 공정에서, 일 퇴적 사이클은 기판을 제1 반응물에 노출하는 단계, 임의의 미반응된 제1 반응물 및 반응 부산물들을 반응 공간으로부터 제거하는 단계, 기판을 제2 반응물에 노출하는 단계, 및 뒤따르는 제2 제거 단계를 포함한다. 제1 반응물은 금속 전구체, 특히 티타늄 전구체와 같은 전이 금속 전구체를 포함할 수 있고, 제2 반응물은 예를 들어 터르트부틸히드라진(tertbutylhydrazine, C4H9N2H3), 메틸히드라진(methylhydrazine, CH3NHNH2), 디메틸히드라진(dimethylhydrazine, (CH3)2N2H2).) 중 적어도 하나와 같은 알킬-히드라진 전구체를 포함할 수 있다.
[23] 전이 금속 전구체 또는 화합물은 스칸듐(Sc), 이트륨(Y), 티타늄(Ti), 지르코늄(Zr), 하프늄(Hf), 바나듐(V), 니오븀(Nb), 탄탈륨(Ta), 크롬(Cr), 몰리브덴(Mo), 텅스텐(W), 망간(Mn), 테크네튬(Tc), 레늄(Re), 철(Fe), 루테늄(Ru), 오스뮴(Os), 코발트(Co), 로듐(Rh), 이리듐(Ir), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 구리(Cu), 은(Ag), 금(Au), 아연(Zn), 카드뮴(Cd) 또는 수은(Hg)을 포함하는 군으로부터 선택되는 적어도 하나의 전이 금속들을 포함할 수 있다. 그러나, 티타늄 질화물 막들이 여기서 예시화되는 것과 같이, 이러한 실시예들에서 금속 화합물은 티타늄을 포함할 수 있다.
[24] 비한정적 예시적인 실시예로서, 예를 들어 티타늄 테트라클로라이드(TiCl4)와 같은 전이 금속 할라이드 반응물이 ALD 공정들 내의 전이 금속 전구체로서 사용될 수 있다.
[25] 반응물들 사이의 기상 반응들을 방지하고 자기-포화적 표면 반응들을 가능하게 하기 위하여 전구체들은 아르곤(Ar) 또는 질소(N2)와 같은 비활성 가스들에 의해 분리될 수 있다. 그러나 일부 실시예들에서, 기판은 제1 금속 반응물 및 제2 알킬-히드라진 반응물을 개별적으로 접촉하도록 이동될 수 있다. 반응들이 자기-포화하기 때문에, 기판들의 엄격한 온도 조절 및 전구체들의 정밀한 도즈 조절이 일반적으로 요구되지 않는다. 그러나 기판 온도는 바람직하게는 입사 가스 종이 모노레이어들로 응축하지 않거나 또는 표면 상에서 분해하지 않도록 된다. 여분의 화학물질들 및 만약 있다면 반응 부산물들이, 기판이 다음의 반응성 화학물질과 접촉되기 전에 예를 들어 반응 공간을 퍼지하거나, 기판을 이동함에 의해서와 같이 기판 표면으로부터 제거된다. 원치 않는 기체의 분자들이 비활성 퍼지 가스들의 도움으로 반응 공간으로부터 효과적으로 배출될 수 있다. 진공 펌프는 퍼지 단계를 돕는 데 사용될 수 있다.
[26] 일부 실시예들에 따르면, ALD-타입의 공정들이 집적 회로 작업물과 같은 기판 상에 전이 금속 질화물 막들, 예를 들어 티타늄 질화물 막들을 형성하는 데 사용된다. 바람직하게는, 각각의 ALD 사이클은 두 개의 개별적인 단계들 또는 상들(phases)을 포함한다. 퇴적 사이클의 제1 상("금속 상")에서, 그 상부에 퇴적이 요구되는 기판 표면이 기판 표면 상에 화학흡착되는 티타늄(예를 들어 티타늄 소스 물질 또는 화학물질)과 같은 전이 금속을 포함하는 제1 반응물과 접촉되고, 기판의 표면 상에 반응물 종의 대략 일 모노레이어보다 크지 않게 형성한다.
[27] 일부 실시예들에서, 또한 여기서 "전이 금속 화합물"로 지칭되는(또는 일부 실시예들에서 "티타늄 화합물"로 지칭되는) 전이 금속(예를 들어, 티타늄) 소스 화학물질은 할라이드이며, 흡착된 모노레이어는 할로겐 리간드들로 터미네이션된다. 일부 실시예들에서, 티타늄 할라이드는 티타늄 테트라클로라이드(TiCl4)일 수 있다.
[28] 여분의 전이 금속(예를 들어, 티타늄) 소스 물질 및 반응 부산물들(만약 있다면)은 예를 들어 비활성 가스로 퍼지함에 의해서 기판 표면으로부터 제거될 수 있다. 여분의 전이 금속 소스 물질 및 임의의 반응 부산물들은 시스템을 펌핑함에 의해 생성되는 진공의 도움으로 제거될 수 있다.
[29] 퇴적 사이클의 제2 상("질소 상")에서, 기판은 알킬-히드라진과 접촉된다. 일부 실시예들에서, 알킬-히드라진은 터르트부틸히드라진, 메틸히드라진, 디메틸히드라진 중 적어도 하나를 포함할 수 있다. 제2 알킬-히드라진 반응물은 기판 표면 상에 남겨진 티타늄-함유 분자들과 반응할 수 있다. 바람직하게는, 제2 상 내에서 전이 금속(예를 들어 티타늄) 소스 물질에 의해 남겨진 모노레이어와 제2 알킬-히드라진 반응물의 상호작용에 의해 질소가 상기 막 내부로 병합된다. 일부 실시예들에서, 제2 알킬-히드라진 반응물과 화학흡착된 전이 금속 종 사이의 반응은 기판 상에 전이 금속 질화물 막을 생성한다.
[30] 여분의 제2 소스 화학물질 및 만약 있다면 반응 부산물들은 예를 들어 퍼지 가스 펄스에 의해, 및/또는 시스템을 펌핑함에 의하여 생성된 진공에 의해 기판 표면으로부터 제거된다. 퍼지 가스는 바람직하게는 아르곤(Ar), 질소(N2), 또는 헬륨(He)과 같은 임의의 비활성 가스이며, 이에 한정되지 않는다. 하나의 상은 퍼지 (즉, 퍼지 가스의 펄스) 또는 다른 반응물 제거 단계가 개입한다면 다른 상을 즉각적으로 따르는 것으로 일반적으로 여겨진다.
[31] 도 1은 전이 금속 전구체 및 알킬-히드라진 전구체를 사용한 본 개시의 ALD 공정에 의해 형성되는 예시적인 티타늄 질화물 막들의 2θ X-선 회절(XRD) 스캔들을 나타내는 그래프이다. 예를 들어, 라벨 100으로 표시된 XRD 스캔은 350℃의 기판 온도에서 티타늄 테트라클로라이드와 알킬-히드라진을 사용한 ALD에 의해 형성된 티타늄 질화물 막으로부터 취해진 것이다. 라벨 100으로 표시된 XRD 스캔은 본 개시의 방법들에 의해 형성된 예를 들어 티타늄 질화물과 같은 전이 금속 질화물 막들이 (111), (200), (220), (311), 및 (420) 배향들을 포함하는 다수의 결정학적 배향들을 포함할 수 있고, (200) 결정학적 배향이 우세함을 가리킨다. 그러므로, 본 개시의 일부 실시예들에서, 여기 설명된 ALD 공정들에 의해 형성된 전이 금속 질화물 막은 (200) 결정학적 배향을 포함하며, 일부 실시예들에서 전이 금속 질화물 막은 지배적인 (200) 결정학적 배향을 포함한다.
[32] 본 개시의 일부 실시예들에서, 전이 금속 질화물 막을 형성하는 단계는 전이 금속 질화물 막을 50 옹스트롬보다 작은 두께, 또는 30 옹스트롬보다 작은 두께, 또는 20 옹스트롬보다 작은 두께까지 형성하는 단계를 포함할 수 있다. 본 개시의 비한정적인 예시적 실시예로서, 전이 금속 질화물 막을 형성하는 단계는 티타늄 질화물 막을 30 옹스트롬보다 작은 두께까지 형성하는 단계를 포함할 수 있다.
[33] 여기 설명된 ALD 공정들에서 질소 소스로서 알킬-히드라진 전구체를 사용하는 것은 증가된 원자 퍼센트의 카본 및 수소를 갖는 티타늄 질화물과 같은 전이 금속 질화물 막들의 헝성을 가능하게 할 수 있다. 증가된 원자 퍼센트의 카본 및 수소를 전이 금속 질화물 막 내로 병합하는 능력은 ALD 전이 금속 질화물 막의 특성들을 개조하는 능력을 가능하게 할 수 있다. 예를 들어, 일부 실시예들에서, 방법들은 전이 금속 질화물 막이 0.1%보다 크거나, 또는 0.5%보다 크거나, 또는 1%보다 크거나, 또는 10%보다도 큰 카본의 원자 농도를 갖도록 형성하는 단계를 포함할 수 있다. 추가적으로, 일부 실시예들에서, 방법들은 전이 금속 질화물 막이 0.1%보다 크거나, 또는 1%보다 크거나, 또는 2%보다 크거나, 또는 10%보다도 큰 수소의 원자 농도를 갖도록 형성하는 단계를 포함할 수 있다. 여기 요약된 실시예들에서, 원소의 원자 농도는 러더포드 백스캐터링법(Rutherford backscattering, RBS)을 사용하여 결정될 수 있다.
[34] 전이 금속 전구체와 알킬-히드라진 전구체를 사용하는 여기 설명된 ALD 공정들은 가열된 기판을 갖는 ALD 퇴적 시스템 내에서 수행될 수 있다. 예를 들어, 일부 실시예들에서, 방법들은 기판을 300℃보다 큰 온도까지 가열하는 단계를 포함할 수 있다. 일부 실시예들에서, 방법들은 기판을 350℃보다 큰 온도까지 가열하는 단계를 포함할 수 있다. 다른 실시예들에서, 방법들은 기판을 450℃보다 큰 온도까지 가열하는 단계를 포함할 수 있다.
[35] 일반적으로 Å/펄스 사이클로서 표현되는 ALD에 의한 박막의 퇴적 속도는, 화학흡착하는 분자들의 표면 및 벌키성(bulkiness) 상에서의 가능한 반응성 표면 사이트들 또는 활성 사이트들의 개수를 포함하는 다수의 요인들에 의존한다. 일부 실시예들에서, 이러한 막들의 퇴적 속도는 약 0.1 내지 약 5.0 Å/펄스 사이클의 범위일 수 있다. 일부 실시예들에서, 퇴적 속도는 약 0.1, 0.2, 0.3, 0.5, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 또는 5.0 Å/펄스 사이클일 수 있다
[36] 여기 개시된 ALD 공정들에 의해 형성되는 티타늄 질화물 박막들과 같은 전이 금속 질화물 박막들은 게이트 전극 구조물들의 형성 내에서와 같은 다양한 맥락들에서 사용될 수 있다. 당업자는 여기 설명된 공정들이 평면 소자들을 포함하는 PMOS 트랜지스터들뿐만 아니라 핀펫들(FinFET)과 같은 다중 게이트 트랜지스터들의 제조를 포함하여 다양한 맥락에 적용할 수 있음을 인식할 것이다.
[37] 비한정적인 예시로서, 도 2를 참조하면, 반도체 구조물(300)은 트랜지스터 구조물을 포함할 수 있고, 또한 소스 영역(302), 드레인 영역(304), 및 그 사이에 배치된 채널 영역(306)을 포함할 수 있다. 트랜지스터 게이트 구조물(308)은 유전 물질(312)에 의해 채널 영역(306)으로부터 분리될 수 있는 게이트 전극(310)을 포함할 수 있다. 본 개시의 가르침에 따르면, 게이트 전극(310)은 전이 금속 전구체와 알킬-히드라진 전구체를 사용한 원자층 퇴적 공정에 의해 형성된 티타늄 질화물과 같은 전이 금속 질화물 막을 포함할 수 있다. 도 2에 도시된 바와 같이, 일부 실시예들에서, 트랜지스터 게이트 구조물(308)은 게이트 전극(310) 상에 형성된 하나 또는 그 이상의 추가적인 도전층들(314)을 더 포함할 수 있다. 하나 또는 그 이상의 추가적인 도전층들(314)은 폴리실리콘, 내화 금속(refractory metal), 전이 금속 카바이드 및 전이 금속 질화물 중 적어도 하나를 포함할 수 있다.
[38] 일부 실시예들에서, 반도체 소자 구조물(300)은 PMOS 트랜지스터를 포함할 수 있다. PMOS 트랜지스터는 트랜지스터 게이트 구조물(308)을 더 포함할 수 있다. PMOS 트랜지스터 게이트 구조물(308)은 전이 금속 질화물 막을 포함하는 게이트 전극(310)과, 전이 금속 질화물 막과 반도체 바디(316) 사이의 게이트 유전체(312)를 포함할 수 있다. 일부 실시예들에서, 반도체 소자 구조물(300)은 NMOS 트랜지스터를 포함할 수 있다. NMOS 트랜지스터는 트랜지스터 게이트 구조물(308)을 더 포함할 수 있다. NMOS 트랜지스터 게이트 구조물(308)은 전이 금속 질화물 막을 포함하는 게이트 전극(310)과, 전이 금속 질화물 막과 반도체 바디(316) 사이의 게이트 유전체(312)를 포함할 수 있다.
[39] 일부 실시예들에서, 게이트 전극(310)은 예를 들어 티타늄 질화물, 탄탈륨 질화물, 텅스텐 질화물, 및 니오븀 질화물과 같은 전이 금속 질화물 막을 포함할 수 있다. 일부 실시예들에서, 게이트 전극(310)은 티타늄 질화물과 같은 전이 금속 질화물 막을 포함할 수 있고, 지배적인 (200) 결정학적 배향을 포함할 수 있다.
[40] 본 개시의 일부 실시예들에서, 추가적인 도전층들(314)은 본질적으로 더 낮은 유효 일함수를 가질 수 있고, 게이트 전극(310)의 목적들 중 하나는 트랜지스터 게이트 구조물(308)의 유효 일함수를 조정할 수 있는 것일 수 있다. 예를 들어, 추가적인 도전층들(314)의 유효 일함수는 대략 4.2 eV일 수 있고, 게이트 전극(310)이 트랜지스터 게이트 구조물(308)의 유효 일함수를 조정하도록 사용될 수 있다. 일부 실시예들에서, 게이트 전극(310)의 특성들(예를 들어, 조성 및 두께)는 대략 4.2 eV와 대략 4.8 eV 사이에서 트랜지스터 게이트 구조물(308)의 유효 일함수를 조절 가능하도록 조정하기 위하여 개조될 수 있다. 비한정적인 예시적 실시예로서, 게이트 전극(308)의 두께 및 카본 함량은 NMOS 트랜지스터 구조물을 위한 최적화된 유효 일함수를 제공하도록 개조될 수 있다. 예를 들어, 본 개시의 일부 실시예들에서, 게이트 전극(310)은 10 옹스트롬보다 작은 두께 및 10%보다 작은 카본 함량을 가질 수 있고, 이는 대략 4.6 eV의 트랜지스터 게이트 구조물(308)의 유효 일함수를 유발할 수 있다.
[41] 본 개시의 일부 실시예들에서, 게이트 전극(310)의 특성들은 PMOS 트랜지스터 및/또는 NMOS 트랜지스터의 문턱 전압(Vth)을 효과적으로 조정하기 위하여 트랜지스터 게이트 구조물(308)의 유효 일함수를 조절 가능하도록 조정하도록 재단될 수 있다. 예를 들어, 트랜지스터 게이트 구조물의 유효 일함수는 다수의 문턱 전압들(Vth)을 갖는 복수의 NMOS 트랜지스터들과 PMOS 트랜지스터들을 포함하는 상보형 금속-산화물-반도체(CMOS) 집적 회로, 일반적으로 다중-문턱 CMOS (multi-threshold CMOS, MTCMOS)로 일컬어지는 것을 제조하기 위하여 달라질 수 있다.
[42] 비한정적인 예시적 실시예로서, 도 3은 티타늄 질화물 막을 포함하는 다양한 게이트 전극 구조물들의, 티타늄 질화물 막 두께의 함수로서 유효 일함수(eWF)를 나타내는 그래프이다. 이러한 비한정적 예시적 실시예들에서, 게이트 전극 구조물(308)은 하프늄 산화물 게이트 산화물(312), 티타늄 질화물 게이트 전극(310), 및 티타늄 알루미늄 카바이드 및 티타늄 질화물을 포함하는 하나 또는 그 이상의 추가적인 도전층들(314)을 포함한다.
[43] 200으로 표시된 eWF 선은 질소 소스로서 일반적 종래 기술의 전구체 암모니아(NH3)를 사용한 ALD에 의해 형성된 티타늄 질화물 막을 포함하는 게이트 전극 구조물의 eWF를 가리킨다. 210으로 표시된 eWF 선은 본 개시에서 설명된 바와 같은, 350℃의 기판 온도에서 질소 소스로서 알킬-히드라진을 사용한, ALD 공정들에 의해 형성된 티타늄 질화물 막을 포함하는 게이트 전극 구조물의 eWF를 가리킨다. 220으로 표시된 eWF 선은 본 개시에서 설명된 바와 같은, 400℃의 기판 온도에서 질소 소스로서 알킬-히드라진을 사용한, ALD 공정들에 의해 형성된 티타늄 질화물 막을 포함하는 게이트 전극 구조물의 eWF를 가리킨다. 도 3에 도시된 바와 같이, 본 개시의 ALD 공정들(즉, 알킬-히드라진 전구체를 사용하는)에 의해 형성되는 티타늄 질화물 막을 포함하는 게이트 전극 구조물들은 감소된 티타늄 질화물 막 두께에서 eWF에 현저한 증가를 나타낸다. 예를 들어, 대략 20 옹스트롬 또는 그 이하의 티타늄 질화물 막 두께에서, 알킬-히드라진 전구체를 사용하여 형성된 티타늄 질화물 막들을 포함하는 게이트 전극 구조물들은, 종래의 암모니아 전구체를 사용하여 형성된 티타늄 질화물 막을 포함하는 게이트 전극 구조물에 대비하여 200 meV보다 큰 eWF의 증가를 나타낸다.
[44] 그러므로, 본 개시의 일부 실시예들에서, 전이 금속 전구체 및 알킬-히드라진 전구체를 사용하여 ALD에 의해 전이 금속 질화물 막을 형성하는 단계는 전이 금속 질화물 막을 포함하는 게이트 전극 구조물이 4.2 eV보다 큰 유효 일함수, 또는 4.4 eV보다도 큰 유효 일함수를 갖도록 형성하는 단계를 포함할 수 있다. 본 개시의 실시예들이 증가된 유효 일 함수를 갖는 얇은 금속 질화물 막들을 포함하는 게이트 전극 구조물들의 형성을 가능하게 함에 주목하여야 하며, 예를 들어 일부 실시예들에서, 방법들은 50 옹스트롬보다 작은 두께와 4.8 eV보다 큰 유효 일함수를 갖는 전이 금속 질화물 막을 포함하는 게이트 전극 구조물을 형성하는 단계를 포함할 수 있다. 추가적인 실시예들에서, 방법들은 30 옹스트롬보다 작은 두께와 4.7 eV보다 큰 유효 일함수를 갖는 전이 금속 질화물 막을 포함하는 게이트 전극 구조물을 형성하는 단계를 포함할 수 있다. 더욱 추가적인 실시예들에서, 방법들은 20 옹스트롬보다 작은 두께와 4.4 eV보다 큰 유효 일함수를 갖는 전이 금속 질화물 막을 포함하는 게이트 전극 구조물을 형성하는 단계를 포함할 수 있다.
[45] 비한정적 예시로서, 게이트 전극(310)을 포함하는 전이 금속 질화물 막은 일부 실시예들에서 50 옹스트롬보다 작은 두께를 가질 수 있고, 또는 일부 실시예들에서 30 옹스트롬보다 작거나, 또는 일부 실시예들에서는 20 옹스트롬보다도 작을 수 있다.
[46] 게이트 전극(310)의 특성들은 또한 게이트 전극(310)을 포함하는 전이 금속 질화물 막 내부로 증가된 원자 퍼센트의 카본 및 수소를 병합하기 위한 능력에 의해 더욱 개조될 수 있다. 예를 들어, 일부 실시예들에서, 게이트 전극(310)을 포함하는 전이 금속 질화물 막은 0.1%보다 크거나, 또는 1%보다 크거나, 또는 10%보다도 큰 카본 원자 농도를 가질 수 있다. 추가적으로, 일부 실시예들에서, 게이트 전극(310)을 포함하는 전이 금속 질화물 막은 0.1%보다 크거나, 또는 1%보다 크거나, 또는 10%보다도 큰 수소 원자 농도를 가질 수 있다. 여기 요약된 실시예들에서, 원소의 원자 농도는 RBS를 사용하여 결정될 수 있다.
[47] 본 개시의 실시예들을 또한 본 개시의 방법들을 수행하도록 구성되는 반응 시스템을 포함할 수 있다. 더욱 상세하게는, 도 4는 반응 챔버(402)를 포함하는 반응 시스템(400)을 개략적으로 도시하며, 반응 챔버(402)는 기판(도시되지 않음)을 미리 결정된 압력, 온도, 및 대기 조건들 하에서 유지하기 위한, 그리고 기판을 다양한 가스들에 선택적으로 노출하기 위한 기구를 더욱 포함한다. 전구체 반응물 소스(404)는 도관들 또는 다른 적합한 부재들(404A)에 의해 반응 챔버(402)에 결합될 수 있고, 전구체 반응물 소스(404)로부터 유래하는 기체의 전구체를 조절하도록 매니폴드, 밸브 조절 시스템, 유량 조절 시스템 또는 기구에 더욱 결합될 수 있다. 전구체 반응물 소스(404)에 의해 공급되는 전구체(도시되지 않음), 반응물(도시되지 않음)은 실온 및 표준 대기압 조건들 하에서 액체 또는 고체일 수 있다. 이러한 전구체는 전구체 소스 챔버 내에서 증기화 온도에서 또는 그 이상에서 유지될 수 있는 반응물 소스 진공 용기(vessel) 내에서 증기화될 수 있다. 이러한 실시예들에서, 증기화된 전구체는 캐리어 가스(예를 들어, 불활성 또는 비활성 가스)와 함께 이송될 수 있고, 이후 도관(404A)을 통해 반응 챔버(402) 내로 투입될 수 있다. 다른 실시예들에서, 전구체는 표준 조건들 하에서 증기일 수 있다. 이러한 실시예들에서, 전구체는 증기화될 필요가 없고 캐리어 가스를 필요로 하지 않을 수 있다. 예를 들어, 일 실시예에서, 전구체는 가스 실린더 내에 저장될 수 있다. 반응 시스템(400)은 또한 전구체 반응물 소스(406)와 같은, 앞서 설명된 바와 같은 도관들(406A)에 의해 반응 챔버와 또한 결합될 수 있는 추가적인 전구체 반응물 소스들을 포함할 수 있다.
[48] 퍼지 가스 소스(408)는 도관들(408A)을 통해 반응 챔버(402)에 또한 결합될 수 있고, 반응 챔버로부터의 전구체 가스 또는 폐기 가스들의 제거를 돕도록 다양한 비활성 또는 불활성 가스들을 반응 챔버(402)까지 선택적으로 공급한다. 공급될 수 있는 다양한 비활성 또는 불활성 가스들은 고체, 액체 또는 저장된 기체의 형태로부터 유래할 수 있다.
[49] 도 4의 반응 시스템(400)은 또한 반응 시스템(400) 내에 포함되는 밸브들, 매니폴드들, 펌프들 및 다른 장치를 선택적으로 구동하도록 전자 회로 및 기계 성분들을 제공하는 시스템 구동 및 조절 기구(410)를 포함할 수 있다. 이러한 회로 및 성분들은 개별적인 전구체 소스들(404, 406) 및 퍼지 가스 소스(408)로부터 전구체, 퍼지 가스들을 도입하도록 구동한다. 시스템 구동 및 조절 기구(410)는 또한 가스 펄스 순서들의 시점, 기판 및 반응 챔버의 온도, 및 반응 챔버의 압력, 및 반응 시스템(400)의 적합한 구동을 제공하도록 필수적인 다양한 다른 구동들을 조절한다. 구동 및 조절 기구(410)는 반응 챔버(402) 내부 및 외부로의 전구체들, 반응물들 및 퍼지 가스들의 흐름을 조절하도록, 소프트웨어 및 전기적으로 또는 공기학적으로 조절되는 밸브들을 조절할 수 있다. 조절 시스템은 특정한 임무들을 수행하는 소프트웨어 또는 하드웨어 성분, 예를 들어 FPGA 또는 ASIC와 같은 모듈들을 포함할 수 있다. 모듈은 유리하게는 조절 시스템의 지정 저장 매체(addressable storage medium) 상에 속하도록 구성될 수 있고, 하나 또는 그 이상의 공정들을 실행하도록 구성될 수 있다.
[50] 관련 기술의 당업자는, 다른 개수 및 종류의 전구체 반응물 소스들 및 퍼지 가스 소스들을 포함하여, 본 반응 시스템의 다른 구성들이 가능함을 인식할 것이다. 더욱이, 이들은 반응 챔버(402) 내부로 가스들을 선택적으로 투입하는 목표를 달성하도록 사용될 수 있는 밸브들, 도관들, 전구체 소스들 및 퍼지 가스 소스들의 많은 배열들이 존재함을 또한 인식할 것이다. 더욱이, 반응 시스템의 개략적 대표도로서, 많은 구성요소들이 도시의 단순화를 위하여 생략되었으며, 이러한 구성요소들이 예를 들어 다양한 밸브들, 매니폴드들, 정류기들, 히터들, 용기들, 벤트들, 및/또는 우회기들(bypass)을 포함할 수 있다.
[51] 전술한 본 개시의 예시적 실시예들은, 이러한 실시예들이 본 발명의 실시예들의 단순한 예시들일 뿐이므로, 본 발명의 범위를 한정하지 않으며, 범위는 첨부된 청구항들 및 이들의 법적인 등가물들에 의해 한정된다. 임의의 등가 실시예들은 본 발명의 범위 내에 속하도록 의도된다. 실제로, 여기 설명되고 보여진 것들에 더하여 설명된 구성요소들의 대안적인 유용한 조합들과 같은 본 개시의 다양한 개조들은 본 명세서로부터 당업자에게 명백해질 수 있다. 이러한 개조들 및 실시예들은 첨부된 청구항들의 범위 내에 속할 것이 또한 의도된다.

Claims (20)

  1. 기판 상에 원자층 퇴적법에 의해 전이 금속 질화물 막을 형성하는 방법으로서,
    상기 기판을 전이 금속 전구체를 포함하는 제1 기상 반응물과 접촉시키는 단계; 및
    상기 기판을 알킬-히드라진(alkyl-hydrazine) 전구체를 포함하는 제2 기상 반응물과 접촉시키는 단계를 포함하는 전이 금속 질화물 막의 형성 방법.
  2. 청구항 1에 있어서,
    상기 알킬 히드라진 전구체가 터르트부틸히드라진(tertbutylhydrazine, C4H9N2H3), 메틸히드라진(methylhydrazine, CH3NHNH2), 디메틸히드라진(dimethylhydrazine, (CH3)2N2H2)) 중 적어도 하나를 포함하도록 선택하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  3. 청구항 1 또는 청구항 2에 있어서,
    상기 전이 금속 전구체가 티타늄 전구체, 탄탈륨 전구체, 텅스텐 전구체 또는 니오븀 전구체 중 적어도 하나를 포함하도록 선택하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  4. 청구항 3에 있어서,
    상기 티타늄 전구체가 티타늄 할라이드(titanium halide)를 포함하도록 선택하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  5. 청구항 4에 있어서,
    상기 티타늄 할라이드가 티타늄 테트라클로라이드(TiCl4)를 포함하도록 선택하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  6. 청구항 1 또는 청구항 2에 있어서,
    상기 방법은 상기 기판이 상기 제1 기상 반응물 및 상기 제2 기상 반응물과 교대로 및 순차적으로 접촉되는 적어도 하나의 퇴적 사이클을 포함하는 것을 특징으로 하는 전이 금속 질화물 막의 형성 방법.
  7. 청구항 6에 있어서,
    상기 퇴적 사이클은 2회 이상 반복되는 것을 특징으로 하는 전이 금속 질화물 막의 형성 방법.
  8. 청구항 1 또는 청구항 2에 있어서,
    상기 전이 금속 질화물 막이 지배적인 (200) 결정학적 배향을 포함하도록 형성하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  9. 청구항 1 또는 청구항 2에 있어서,
    상기 전이 금속 질화물 막이 대략 50 옹스트롬보다 작은 두께를 갖도록 형성하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  10. 청구항 1 또는 청구항 2에 있어서,
    상기 전이 금속 질화물 막을 포함하며, 4.2 eV보다 더 큰 유효 일함수를 갖는 게이트 전극 구조물을 형성하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  11. 청구항 1 또는 청구항 2에 있어서,
    상기 전이 금속 질화물 막이 0.5%보다 큰 카본 원자 농도를 갖도록 형성하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  12. 청구항 1 또는 청구항 2에 있어서,
    대략 350℃보다 더 큰 온도까지 상기 기판을 가열하는 단계를 더 포함하는 전이 금속 질화물 막의 형성 방법.
  13. 청구항 1 또는 청구항 2에 따른 전이 금속 질화물 막의 형성 방법을 수행하도록 구성된 반응 시스템.
  14. PMOS 트랜지스터 게이트 구조물로서,
    전이 금속 질화물 막;
    반도체 바디; 및
    상기 전이 금속 질화물 막과 상기 반도체 바디 사이에 배치되는 게이트 유전체를 포함하는 상기 PMOS 트랜지스터 게이트 구조물을 포함하며,
    상기 전이 금속 질화물 막은 지배적인 (200) 결정학적 배향을 포함하는 반도체 소자 구조물.
  15. 청구항 14에 있어서,
    상기 전이 금속 질화물 막은 티타늄 질화물을 포함하는 것을 특징으로 하는 반도체 소자 구조물.
  16. 청구항 14 또는 청구항 15에 있어서,
    상기 전이 금속 질화물 막은 대략 50 옹스트롬보다 작은 두께를 갖는 것을 특징으로 하는 반도체 소자 구조물.
  17. 청구항 14 또는 청구항 15에 있어서,
    상기 PMOS 게이트 구조물은 4.2 eV보다 더 큰 유효 일함수를 갖는 것을 특징으로 하는 반도체 소자 구조물.
  18. 청구항 14 또는 청구항 15에 있어서,
    상기 전이 금속 질화물 막은 0.5%보다 큰 카본 원자 농도를 갖는 것을 특징으로 하는 반도체 소자 구조물.
  19. NMOS 트랜지스터 게이트 구조물로서,
    전이 금속 질화물 막;
    반도체 바디; 및
    상기 전이 금속 질화물 막과 상기 반도체 바디 사이에 배치되는 게이트 유전체를 포함하는 상기 NMOS 트랜지스터 게이트 구조물을 포함하며,
    상기 전이 금속 질화물 막은 지배적인 (200) 결정학적 배향을 포함하는 반도체 소자 구조물.
  20. 청구항 19에 있어서,
    상기 전이 금속 질화물 막은 티타늄 질화물을 포함하는 것을 특징으로 하는 반도체 소자 구조물.
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