TWI753834B - 透過保形固態摻雜而經改善的源極和汲極性能 - Google Patents
透過保形固態摻雜而經改善的源極和汲極性能 Download PDFInfo
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- TWI753834B TWI753834B TW110118827A TW110118827A TWI753834B TW I753834 B TWI753834 B TW I753834B TW 110118827 A TW110118827 A TW 110118827A TW 110118827 A TW110118827 A TW 110118827A TW I753834 B TWI753834 B TW I753834B
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Abstract
本發明揭示一種用於經由保形固態摻雜而改善源極和汲極性能之方法及其所得裝置。具體言之,該摻雜經由摻雜物層之原子層沉積而進行。相比於諸如離子植入或磊晶摻雜之替代摻雜方法,本發明之具體實例可允許摻雜層增大、保形性經改善以及缺陷形成減少。
Description
本發明大體上係關於用於製造電子裝置之製程。更特定言之,本發明係關於形成用於NMOS及CMOS應用之源極/汲極裝置。具體言之,本發明揭示用以利用保形固態摻雜技術而改善源極/汲極摻雜程度之方法。
[相關申請案之交叉參考]
本申請案係關於2012年9月17日申請之題為「Synthesis and Use of Precursors for ALD of Group VA Element Containing Thin Films」且獲頒為美國專利第9,315,896號之美國非臨時專利申請案第13/504,079號,該案之全部揭示內容特此以全文引用之方式併入。
鍺已被視為供CMOS及NMOS裝置使用之合適材料。隨著裝置朝著小型化發展,裝置上之接觸面積已變得更小,從而實質上增大了接觸電阻。接觸電阻之增大已利用高源極/汲極摻雜來抗衡。
根據Miyoshi等人之VLSI 2014, P180,經由結合雷射退火之銻(Sb)離子植入已達成n型鍺上之最小接觸電阻率。然而,對於FinFET及奈米線裝置,離子植入製程可能具有挑戰性。
因此,需要用於改善源極和汲極性能之方法。
在根據本發明之至少一個具體實例中,揭示了一種形成用於源極/汲極應用之半導體裝置之方法。該方法包含:在反應室中提供用於處理之基板,該基板具有至少一個形成的源極/汲極區;對該基板執行表面清潔,該表面清潔將氧化物或原生氧化物自該基板移除;在該基板上執行摻雜物層之原子層沉積;在該摻雜物層上執行罩蓋層之原子層沉積;以及執行驅入式退火步驟,例如,以使摻雜物自該摻雜物層擴散至該至少一個形成的源極/汲極區中。該摻雜物層可形成用於NMOS及CMOS裝置之通道材料。
在根據本發明之至少一個具體實例中,揭示了一種形成用於源極/汲極應用之半導體裝置之方法。該方法包含:在反應室中提供用於處理之基板,該基板具有至少一個形成的源極/汲極區;對該基板執行表面清潔;在該基板上執行摻雜物層之原子層沉積;以及在該摻雜物層上執行罩蓋層之原子層沉積。該摻雜物層可形成用於NMOS及CMOS裝置之通道材料。
出於概述本發明及所達成的優於先前技術之優點之目的,已在上文中對本發明之某些目標及優點加以描述。當然,應理解,未必所有此等目標或優點均可根據本發明之任何特定具體實例來達成。因此,舉例而言,熟習此項技術者將認識到,可以達成或最佳化如本文中所教示或建議之一個優點或優點組而未必達成本文中可能教示或建議之其他目標或優點的方式來實施或實行本發明。
所有此等具體實例意欲在本文中所揭示的本發明之範圍內。此等及其他具體實例對熟習此項技術者而言將自參考附圖之以下某些具體實例之詳細描述變得顯而易見,但本發明並不限於所揭示之任何特定具體實例。
儘管在下文中揭示了某些具體實例及實例,但熟習此項技術者應理解,本發明延伸超出本發明所具體揭示之具體實例及/或用途及其明顯修改及等效物。因此,希望所揭示之本發明之範圍不應受下文所描述之所特定揭示之具體實例的限制。
原子層沉積(ALD)固態摻雜(SSD)可為形成NMOS及CMOS裝置之一種方式。對此的一個原因可能為ALD SSD能夠形成具有極佳保形性及無缺陷特徵的膜。諸如離子植入的替代摻雜方法可能在3-D結構之保形摻雜期間引入ALD SSD可避免之缺陷。ALD SSD亦可提供在精確次奈米厚度控制情況下沉積薄膜之能力,因此判定在表面處可得到以作為有效摻雜物物質併入至半導體中的原子之劑量或數目。根據本發明之具體實例可導致界面附近之摻雜程度以超淺摻雜分佈增大。舉例而言,摻雜程度大於1x10
20/cm
3且擴散深度小於30 nm可為較佳。
根據本發明之至少一個具體實例,經由ALD SSD的摻雜程度之目標可約為5x10
20/cm
3。ALD SSD摻雜程度可為大於經由替代方法(諸如,磊晶摻雜)達成之數量級5x10
19/cm
3的數量級。此外,諸如離子植入或磊晶摻雜的替代方法可在將高濃度之取代型或填隙摻雜物物質併入至半導體基質中時導致膜之形態降級(degrade),且使膜不適合其在CMOS或NMOS裝置中之預期用途。
圖1說明根據本發明之至少一個具體實例之方法100。舉例而言,方法100可在由ASM International B.V.提供的Pulsar® XP ALD反應器中進行。
方法100可包括源極/汲極(S/D)形成之第一步驟110。第一步驟110可能需要向反應室提供基板,該基板在其中或在其上形成有源極/汲極(S/D)區。舉例而言,該基板可包含鍺、矽、矽鍺或其他III-V族材料,在其中或其上形成有源極區及汲極區。
方法100可包括表面清潔之第二步驟120。第二步驟120可包括使用清潔劑清潔晶圓。第二步驟120之效應可為移除基板之表面上的任何氧化物或原生氧化物。氧化物或原生氧化物之存在可使性能降級,此係因為其存在將不利地影響基板裝置之接觸電阻率。
舉例而言,在第二步驟120中,可能出現預處理,諸如鍺晶圓將用氫氟酸(HF)進行清潔。舉例而言,其他可能的清潔劑包括氫氯酸(HCl)或NF
3電漿。根據本發明之至少一個具體實例,第二步驟120可包含標準濕式清潔,其可在(例如)由ASM International B.V.提供之Horizon模組中進行。
方法100可包括摻雜物層ALD之第三步驟130。第三步驟130中所沉積之摻雜物層可包括(例如)銻、硼、砷、磷、鎂、碳、矽或硫。第三步驟130中所沉積之摻雜物層可為基本或複合材料。第三步驟130可在範圍在20℃與450℃之間的溫度下進行。對於此步驟或本文中所描述之其他沉積步驟,反應室中之壓力通常為約0.01 mbar至約20 mbar,更佳為約1 mbar至約10 mbar。然而,在一些狀況下,壓力將高於或低於此範圍,如熟習此項技術者在給定特定情形下可判定。可重複第三步驟130,直至達成所要厚度(諸如,0.1 nm至15 nm)為止。摻雜物層可包括根據特此以引用之方式併入的美國專利申請案第13/504,079號之揭示內容所沉積的銻或砷。
根據本發明之至少一個具體實例,銻沉積可在第三步驟130期間在反應室中進行。反應室在第三步驟130期間之溫度可在60℃至120℃之間、較佳在60℃至100℃之間且更佳在60℃至80℃之間的範圍中。可視需要重複第三步驟130,以便獲得銻層之所要厚度,該厚度在一些例子中可為0.5 nm且在其他例子中可為10 nm。在一些具體實例中,第三步驟130可能不形成層;替代地,可形成的物件可能為包含銻之材料的材料或島狀物(可能獨立或部分連接)之隔離位置。
為了沉積銻,第三步驟130可包括脈衝包含金屬鹵化物之第一前驅體,金屬鹵化物諸如SbCl
3、SbF
3、SbBr
3或SbI
3。第一前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒與2秒之間的範圍中。第三步驟130可接著包括使用沖洗氣體(諸如N
2、Ar或其他惰性氣體)沖洗該第一前驅體。沖洗氣體之脈衝的持續時間可在5秒與15秒之間且較佳在5秒與10秒之間的範圍中。
為了沉積銻,第三步驟130可包括脈衝包含銻之第二前驅體。舉例而言,該第二前驅體可包含以下各者中之至少一者:三甲基矽烷基銻、三乙基矽烷基銻、烷氧化銻或胺化銻。該第二前驅體亦可包含鍵結至矽原子之銻,其具有通式Sb(AR
1R
2R
3)
3,其中A為Si或Ge且R
1、R
2及R
3為包含一或多個碳原子之烷基。第二前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒至2秒之間的範圍中。第三步驟130可接著包括使用沖洗氣體(諸如N
2、Ar或其他惰性氣體)沖洗該第二前驅體。沖洗氣體之脈衝的持續時間可在5秒與15秒之間且較佳在5秒至10秒之間的範圍中。
方法100可包括罩蓋層ALD之第四步驟140。第四步驟140中所沉積之層可包括(例如)二氧化矽(SiO
2)、氮化矽(SiN)、氮化鋁(AlN)、氮化鈦(TiN)、含矽碳或氧化鋁(Al
2O
3)。第四步驟140可在範圍在20℃與450℃之間的溫度下進行。罩蓋層沉積可不導致第三步驟130中所形成之摻雜物層氧化。
舉例而言,為形成一層二氧化矽,第四步驟140可包括脈衝第一前驅體,該第一前驅體包含(例如)矽烷、二矽烷、三矽烷、胺基矽烷或胺基二矽烷中之至少一者。第一前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒與2秒之間的範圍中。第四步驟140亦可包括使用沖洗氣體(諸如N
2、Ar或其他惰性氣體)沖洗該第一前驅體。沖洗氣體之脈衝的持續時間可在0.1秒與30秒之間且較佳在0.3秒與3秒之間的範圍中。
第四步驟140亦可包括脈衝第二前驅體,其包含氧(O
2)電漿、臭氧(O
3)、水(H
2O)、氧(O
2)、過氧化氫(H
2O
2)或其他氧前驅體中之至少一者。第二前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒與2秒之間的範圍中。第四步驟140可接著包括使用沖洗氣體對第二前驅體進行後續沖洗。沖洗氣體之脈衝的持續時間可在0.01秒與15秒之間且較佳在0.05秒與2秒之間的範圍中。類似於第三步驟130,可視需要重複第四步驟140,以便形成具有所要厚度之層。在一些例子中,雙層結構可用於第四步驟140,例如,SiN/SiO
2結構。
方法100可包括驅入式退火之第五步驟150,該驅入式退火可用以將摻雜物自摻雜物ALD層驅趕至源極及/或汲極區中。在此步驟期間,基板可經受450℃與1100℃之間的溫度範圍,從而導致經改善的摻雜物驅入。退火可具有範圍在1秒與30分鐘之間的持續時間。
第五步驟150中之退火在方法100之總體熱預算中可起重要作用。總體熱預算可判定(例如)30 nm之摻雜物擴散深度。
藉由根據本發明之步驟解決的一個問題可為摻雜物之溶解度。舉例而言,存在鍺中n型摻雜劑低溶解度的問題。第三步驟130可允許合適的摻雜,此歸因於其經改善的保形性以及限制由離子植入引起之缺陷之形成的能力。在使用驅入式退火的情況下,由ALD進行的固態摻雜物之沉積可允許在離子植入中可能無法實現的界面之保形3-D摻雜。此外,由其他摻雜技術引起之缺陷形成可藉由ALD SSD來避免。
方法100可包括頂蓋層移除之可選第六步驟160。頂蓋層移除可藉由使用(例如)將氫氟酸(HF)作為蝕刻劑的蝕刻步驟來實現。
在一些例子中,頂蓋層移除可能並非必需的。若(例如)習知接觸金屬堆疊Ti/TiN可充當頂蓋層以防止摻雜物向外擴散,則驅入式退火可免除對移除頂蓋層之需要。
圖2說明根據本發明之至少一個具體實例之方法200。方法200可包括源極/汲極(S/D)形成之第一步驟210。第一步驟210可能需要向反應室提供基板,其中源極/汲極(S/D)形成於該基板內或該基板上。舉例而言,該基板可包含(例如)鍺、矽、矽鍺或III-V族材料。
方法200可包括表面清潔之第二步驟220。第二步驟220可包括使用清潔劑清潔晶圓。第二步驟220之效應可為移除基板之表面上的任何氧化物或原生氧化物。氧化物或原生氧化物之存在可使性能降級,此係因為其存在將不利地影響基板裝置之接觸電阻率。
舉例而言,在第二步驟220中,可使用氫氟酸(HF)來清潔鍺矽晶圓。舉例而言,其他可能的清潔劑包括氫氯酸(HCl)或NF
3電漿。根據本發明之至少一個具體實例,第二步驟120可包含標準濕式清潔,其可在(例如)由ASM International B.V.提供之Horizon模組中進行。
方法200可包括摻雜物層ALD之第三步驟230。第三步驟230中所沉積之摻雜物層可包括(例如)銻、硼、砷、磷、鎂、碳、矽或硫。第三步驟230可在範圍在20℃與450℃之間的溫度下進行。可重複第三步驟230,直至達成所要厚度(諸如,0.1 nm至15 nm)為止。
根據本發明之至少一個具體實例,銻沉積可在第三步驟230期間在反應室中進行。反應室在第三步驟230期間之溫度可在60℃至120℃之間、較佳在60℃至100℃之間,更佳在60℃至80℃之間的範圍中。可視需要重複第三步驟230,以便獲得銻層之所要厚度,該厚度在一些例子中可為0.5 nm且在其他例子中可為10 nm。
為了沉積銻,第三步驟230可包括脈衝包含一金屬鹵化物之第一前驅體,金屬鹵化物諸如SbCl
3、SbF
3、SbBr
3或SbI
3。第一前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒與2秒之間的範圍中。第三步驟230可包括接著使用沖洗氣體(諸如N
2、Ar或其他惰性氣體)沖洗該第一前驅體。沖洗氣體之脈衝的持續時間可在5秒與15秒之間且較佳在5秒與10秒之間的範圍中。
為了沉積銻,第三步驟230可包括脈衝包含銻之第二前驅體。舉例而言,該第二前驅體可包含以下各者中之至少一者:三甲基矽烷基銻、三乙基矽烷基銻、烷氧化銻或胺化銻。該第二前驅體亦可包含鍵結至矽原子之銻,其具有通式Sb(AR
1R
2R
3)
3,其中A為Si或Ge且R
1、R
2及R
3為包含一或多個碳原子之烷基。第二前驅體之脈衝的持續時間可在0.1秒與5秒之間且較佳在0.5秒與2秒之間的範圍中。第三步驟230可接著包括使用沖洗氣體(諸如N
2、Ar或其他惰性氣體)沖洗該第二前驅體。沖洗氣體之脈衝的持續時間可在5秒與15秒之間且較佳在5秒與10秒之間的範圍中。
方法200可包括罩蓋層ALD之第四步驟240。所沉積的罩蓋層可包含金屬。第四步驟240中所沉積之金屬可包括(例如)鈦、氮化鈦(TiN)、矽化鈦(TiSi
x)、矽化鉭(TaSi
x)或矽化鈮(NbSi
x)。第四步驟240可包括脈衝包含金屬鹵化物之第一前驅體,金屬鹵化物諸如氯化鈦(TiCl
x)、氟化鉭(TaF
x)、氟化鈮(NbF
x)或其他金屬鹵化物。視罩蓋層而定,脈衝之時序可不同。舉例而言,為了形成矽化物,第一前驅體之脈衝的持續時間可在0.01秒與5秒之間或較佳在0.5秒與1秒之間的範圍中。為了形成氮化物,前驅體之脈衝的持續時間可在0.01秒與20秒之間或較佳在1秒與15秒之間的範圍中。第四步驟240可包括脈衝沖洗氣體,諸如N
2、Ar或其他惰性氣體。沖洗氣體之脈衝的持續時間可在5秒與30秒之間且較佳在5秒與10秒之間的範圍中。
舉例而言,第四步驟240可包括脈衝第二前驅體,該第二前驅體諸如氨(NH
3)或矽烷。第二前驅體之脈衝的持續時間可在0.01秒與30秒之間或較佳在1秒與15秒之間的範圍中。第四步驟240可包括脈衝沖洗氣體,諸如N
2、Ar或其他惰性氣體。沖洗氣體之脈衝的持續時間可在5秒與30秒之間且較佳在5秒與10秒之間的範圍中。
第四步驟240可在範圍在20℃與600℃之間、較佳在200℃與500℃之間且更佳在300℃與400℃之間的溫度下進行。可重複第四步驟240,直至達成罩蓋層之所要厚度(諸如0.1 nm至5 nm,較佳在0.1 nm至3 nm或0.1 nm至2 nm之間)為止。罩蓋層之厚度可小於約5 nm,小於約3 nm,小於約2 nm,或較佳小於約1.5 nm。
方法200可包括驅入式退火之第五步驟250。在此步驟期間,基板可經受450℃與1100℃之間的溫度範圍的溫度,從而導致經改善的摻雜物驅入。退火可具有範圍在1秒與30分鐘之間的持續時間。
圖3A說明根據本發明之至少一個具體實例之裝置。形成的裝置可包含罩蓋層310、摻雜物層320及基板330。此時,罩蓋層310已沉積,但該等層中之每一者為獨特且獨立的。此外,驅入式退火尚未進行。摻雜物層320可包含銻,而基板330可包含鍺。
圖3B說明驅入式退火已進行之後的根據本發明之至少一個具體實例之裝置。該裝置具有罩蓋層310及基板330,但摻雜物已浸潤基板330之一部分從而形成經摻雜基板層340。舉例而言,若摻雜物為銻且基板為鍺,則經摻雜基板層340將包含銻摻雜之鍺層。
圖3C說明驅入式退火已進行之後的根據本發明之至少一個具體實例之裝置。類似於圖3B中之裝置,驅入式退火已進行,但在此狀況下,驅入式退火未導致摻雜物完全浸潤至基板330中。該裝置可包含罩蓋層310、基板330及經摻雜基板層340,但亦包括表示尚未浸潤至基板330中之摻雜物的摻雜物層320。
所展示及所描述的特定實施係對本發明及其最佳模式之說明且並不意欲以任何方式另外限制態樣及實施之範圍。實際上,出於簡潔起見,系統之習知製造、連接、製備及其他功能性態樣可不加以詳細描述。此外,各種圖中所示之連接線意欲表示各種要素之間的例示性功能關係及/或實體耦接。許多替代或額外功能關係或實體連接可存在於實際系統中,及/或在一些具體實例中可不存在。
應理解,本文中所述之組態及/或方法實際上為例示性的,且此等特定具體實例或實例不視為具有限制意義,原因在於可能有眾多變化形式。本文中所述之特定常式或方法可表示任何數目個處理策略中一或多者。因此,所說明之各種動作可以所說明之順序、以其他順序進行,或在一些狀況下被省去。
本發明之標的包括本文中所揭示之各種製程、系統及組態及其他特徵、功能、動作及/或性質以及其任何及所有等效物之所有新穎但非顯而易見的組合及子組合。
100:方法
110:第一步驟
120:第二步驟
130:第三步驟
140:第四步驟
150:第五步驟
160:第六步驟
200:方法
210:第一步驟
220:第二步驟
230:第三步驟
240:第四步驟
250:第五步驟
310:罩蓋層
320:摻雜物層
330:基板
340:經摻雜基板層
參考某些具體實例之圖式在下文中描述本文中所揭示的本發明之此等及其他特徵、態樣及優點,該等圖式意欲說明而非限制本發明。
[圖1]為根據本發明之至少一個具體實例之方法的流程圖。
[圖2]為根據本發明之至少一個具體實例之另一方法的流程圖。
[圖3A至圖3C]為根據本發明之具體實例之裝置的說明。
應瞭解,圖中之元件係為了簡單及清楚起見而說明且未必按比例繪製。舉例而言,圖中之一些元件之尺寸可相對於其他元件誇示以幫助改善對本發明所說明具體實例的理解。
100:方法
110:第一步驟
120:第二步驟
130:第三步驟
140:第四步驟
150:第五步驟
160:第六步驟
Claims (16)
- 一種形成用於源極/汲極應用之半導體裝置之方法,其包含: 在反應室中提供用於處理之基板,該基板具有至少一個形成的源極/汲極區,使該至少一個形成的源極/汲極區暴露於清潔以移除氧化物或原生氧化物; 在該基板上執行元素摻雜物層之原子層沉積;以及 在該元素摻雜物層上執行罩蓋層之原子層沉積; 其中,在該罩蓋層之原子層沉積之後,該半導體裝置經歷驅入式退火步驟,以使摻雜物自該元素摻雜物層擴散至該等形成的源極/汲極區中之至少一者中,且 其中該元素摻雜物層之原子層沉積形成具有在基板中的摻雜程度大於1x10 20/cm 3且擴散深度小於30 nm的NMOS裝置之通道材料。
- 如請求項1之方法,其進一步包含:移除該罩蓋層。
- 如請求項1之方法,其中該基板包含以下至少一者:矽、鍺、矽鍺或III-V族材料。
- 如請求項1之方法,其中該元素摻雜物層包含銻、硼、砷、磷、鎂、碳、矽或硫。
- 如請求項1之方法,其中其中該罩蓋層包含以下至少一者:二氧化矽(SiO 2)、氮化鈦(TiN)、氮化矽(SiN)、氮化鋁(AlN)、含矽碳或氧化鋁(Al 2O 3)。
- 如請求項1之方法,其中執行該元素摻雜物層之原子層沉積包含: 將第一前驅體脈衝至該基板上,其中該第一前驅體為以下至少一者:SbCl 3、SbF 3、SbI 3、SbBr 3或金屬鹵化物; 使用沖洗氣體自該反應室沖洗該第一前驅體,其中該沖洗氣體包含以下至少一者:N 2、Ar或惰性氣體; 將第二前驅體脈衝至該基板上,其中該第二前驅體為以下至少一者:三甲基矽烷基銻或三乙基矽烷基銻;以及 使用該沖洗氣體自該反應室沖洗該第二前驅體。
- 如請求項1之方法,其中在一或多個源極/汲極區中的摻雜程度為約5x10 20/cm 3。
- 如請求項1之方法,其中該驅入式退火在大於400℃之溫度下執行。
- 一種形成用於源極/汲極應用之半導體裝置之方法,其包含: 在反應室中提供用於處理之基板,該基板具有形成的源極/汲極區; 在該基板上執行元素摻雜物層之原子層沉積;以及 在該元素摻雜物層上執行罩蓋層之原子層沉積; 其中該元素摻雜物層之原子層沉積形成具有在基板中的摻雜程度大於1x10 20/cm 3且擴散深度小於30 nm的NMOS裝置之通道材料。
- 如請求項9之方法,其中該基板包含以下至少一者:矽、鍺、矽鍺或III-V族材料。
- 如請求項9之方法,其中該元素摻雜物層包含銻、硼、砷、磷、鎂、碳、矽或硫。
- 如請求項9方法,其中該罩蓋層包含以下至少一者:鈦;氮化鈦(TiN x);矽化鈦(TiSi x);矽化鉭(TaSi x);或矽化鈮(NbSi x)。
- 如請求項9之方法,其中驅入式退火係在大於400℃之溫度下對該基板執行。
- 如請求項9之方法,其中執行該元素摻雜物層之原子層沉積包含: 將第一前驅體脈衝至該基板上,其中該第一前驅體為以下至少一者:SbCl 3、SbF 3、SbI 3、SbBr 3或金屬鹵化物; 使用沖洗氣體自該反應室沖洗該第一前驅體,其中該沖洗氣體包含以下至少一者:N 2、Ar或惰性氣體; 將第二前驅體脈衝至該基板上,其中該第二前驅體為以下至少一者:三甲基矽烷基銻或三乙基矽烷基銻;以及 使用該沖洗氣體自該反應室沖洗該第二前驅體。
- 如請求項9之方法,其中執行該罩蓋層之原子層沉積包含: 將第一前驅體脈衝至該基板上,其中該第一前驅體為以下至少一者:TiCl x、TaF x、NbF x或金屬鹵化物; 使用沖洗氣體自該反應室沖洗該第一前驅體,其中該沖洗氣體包含以下至少一者:N 2、Ar或惰性氣體; 將第二前驅體脈衝至該基板上,其中該第二前驅體為以下至少一者:氨(NH 3)或矽烷;以及 使用該沖洗氣體自該反應室沖洗該第二前驅體。
- 如請求項9之方法,其中在一或多個源極/汲極區中的摻雜程度為約5x10 20/cm 3。
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TW201805998A (zh) | 2018-02-16 |
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