CN108987476A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN108987476A
CN108987476A CN201710403508.XA CN201710403508A CN108987476A CN 108987476 A CN108987476 A CN 108987476A CN 201710403508 A CN201710403508 A CN 201710403508A CN 108987476 A CN108987476 A CN 108987476A
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fin
separation layer
area
opening
semiconductor structure
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CN108987476B (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/993,974 priority patent/US10403549B2/en
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Priority to US16/516,594 priority patent/US11037836B2/en
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Abstract

本发明提供一种半导体结构及其形成方法，其中，形成方法包括：提供衬底，在所述衬底上形成第一隔离层；在所述第一隔离层内形成第一开口；在所述第一开口的侧壁形成第二隔离层；对所述第一隔离层的侧壁进行刻蚀，形成第二开口；在所述第一开口和所述第二开口内形成第二鳍部。所述形成方法增加了第二鳍部与所述第一隔离层的接触面积，改善自热效应，由此提高了半导体结构的电学稳定性和可靠性；同时通过第二隔离层厚度调节第二鳍部的第三宽度，提高了器件集成度。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展，平面晶体管的栅极尺寸也越来越短，传统的平面晶体管对沟道电流的控制能力变弱，产生短沟道效应，产生漏电流，最终影响半导体器件的电学性能。
为了克服晶体管的短沟道效应，抑制漏电流，现有技术提出了鳍式晶体管(FinFET)，鳍式晶体管是一种常见的多栅器件，鳍式晶体管的结构包括：位于半导体衬底表面的鳍部和介质层，所述介质层覆盖部分所述鳍部的侧壁，且介质层表面低于鳍部顶部；位于介质层表面，以及鳍部的顶部和侧壁表面的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
在常规平面晶体管中，沟道区域产生大量的热量通过横向扩散，由此散发到衬底的热阻很小。但是在鳍式晶体管中，由于横向绝缘，有更多的热阻散发到衬底，导致局部温度过高，影响器件的稳定性；同时由于热电子发射发生在漏区，在鳍式晶体管漏区发生的自热效应比在源区发生的自热效应更大，在漏区产生的热量通过扩散至其它鳍部以及衬底处，导致晶体管的局部温度升高，特别是随着半导体器件的密度提高和尺寸缩小，自热效应越严重，导致所形成的鳍式晶体管的电学性能变差，可靠性下降。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，通过在鳍部第一区上形成第二鳍部，不但自热效应得到解决，而且所形成的第二鳍部的鳍部宽度得到控制，由此提高了半导体结构的整体性能，利于提高器件集成度。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底具有初始鳍部，所述初始鳍部包括第一区，位于第一区上的第二区以及位于第二区上的第三区；在所述衬底上形成第一隔离层，所述第一隔离层暴露出所述初始鳍部的顶部表面；去除所述初始鳍部的第三区，在所述第一隔离层内形成第一开口；在所述第一开口的侧壁形成第二隔离层；在形成所述第二隔离层之后，去除第一开口底部的第二区，形成与第一开口底部贯通的初始第二开口和位于所述初始第二开口底部的第一鳍部；对所述初始第二开口的侧壁进行刻蚀以形成第二开口，所述第二开口的侧壁暴露所述第一隔离层；在所述第一开口和所述第二开口内形成第二鳍部；刻蚀所述第一隔离层和第二隔离层，暴露出所述第二鳍部的部分侧壁。
可选的，所述第二鳍部包括位于所述第二开口内的第四区以及所述第一开口内的第五区，且所述第四区位于所述第一鳍部上，所述第五区位于所述第四区上。
可选的，所述第一鳍部具有垂直于所述第一鳍部延伸方向的第一宽度；所述第四区具有垂直于所述第一鳍部延伸方向的第二宽度；所述第五区具有垂直于所述第一鳍部延伸方向的第三宽度；所述第二宽度大于所述第一宽度，所述第一宽度大于所述第三宽度。
可选的，采用第三刻蚀工艺对所述初始第二开口的侧壁进行刻蚀。
可选的，所述第三刻蚀工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
可选的，在所述第一开口的侧壁形成第二隔离层的工艺步骤包括：在所述第一隔离层上形成第二隔离膜，所述第二隔离膜还覆盖所述第一开口的侧壁和底部；去除第一开口底部和第一隔离层顶部的第二隔离膜，在所述第一开口的侧壁形成第二隔离层。
可选的，所述第二隔离膜的材料与所述第一隔离层的材料相同或不同。
可选的，去除所述第二隔离膜的工艺为各向异性的干法刻蚀工艺。
可选的，去除所述第一开口底部的第二区的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
可选的，在所述第一开口和所述第二开口内形成第二鳍部的步骤包括：在所述第一开口和所述第二开口填充半导体膜。
可选的，形成所述半导体膜的工艺为外延生长工艺。
可选的，所述半导体膜的材料包括SiB、SiGe、SiC、SiP、SiAs、SiGeB、SiCB、GaN、lnAs和InP。
可选的，去除所述初始鳍部的第三区的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
可选的，所述初始鳍部还包括掩膜结构，所述掩膜结构位于所述第三区上；去除所述第三区还包括去除所述掩膜结构。
可选的，所述第一隔离层的形成工艺步骤包括：在所述衬底上形成第一隔离膜，所述第一隔离膜覆盖所述初始鳍部的侧壁和顶部表面；对所述第一隔离膜进行平坦化，直至暴露出所述初始鳍部的顶部表面。
可选的，所述第一隔离层的材料包括氧化硅或氮氧化硅。
可选的，刻蚀所述第一隔离层和第二隔离层的工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
本发明还提供一种半导体结构，其特征在于，包括：衬底，所述衬底具有第一鳍部，所述第一鳍部具有垂直于所述第一鳍部延伸方向上的第一宽度；位于所述第一鳍部上的第二鳍部，所述第二鳍部包括位于所述第一鳍部上的第四区，以及位于第四区上的第五区；所述第四区具有垂直于所述第一鳍部延伸方向的第二宽度；所述第五区具有垂直于所述第一鳍部延伸方向的第三宽度；所述第二宽度大于所述第一宽度，所述第一宽度大于所述第三宽度；覆盖所述第五区的部分侧壁的第二隔离层；覆盖所述第一鳍部的侧壁、所述第二鳍部的第四区侧壁和所述第二隔离层侧壁的第一隔离层。
可选的，所述第一隔离层的材料包括氧化硅或氮氧化硅。
可选的，所述第二隔离膜的材料与所述第一隔离层的材料相同或不同。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体结构的形成方法中，在所述衬底上形成第一隔离层，通过对所述第一隔离层的侧壁进行刻蚀，后续形成的第四区具有的第二宽度大于所述第一鳍部具有的第一宽度，由此增加了第二鳍部与所述第一隔离层的接触面积，使得半导体结构工作时产生的热量更容易通过衬底向外扩散，从而改善自热效应，提高了半导体结构的电学稳定性和可靠性。
进一步，在所述第一开口的侧壁形成第二隔离层，通过第二隔离层的不同厚度，可以控制所述第二鳍部具有的第五区的第三宽度，有利于提高器件集成度。
进一步，采用第三刻蚀工艺对所述初始第二开口的侧壁进行刻蚀，通过控制第三刻蚀工艺的刻蚀时间，实现对所述第四区具有的第二宽度的调控，提高了工艺的灵活性，为改善半导体结构的电学稳定性和可靠性提供工艺窗口。
附图说明
图1至图4是一种半导体结构的形成过程的剖面结构示意图；
图5至图12是本发明实施例的半导体结构的形成过程的剖面结构示意图。
具体实施方式
如背景技术所述，随着半导体器件的密度提高，尺寸缩小，所形成的半导体结构的性能变差，可靠性下降。
现有技术形成的半导体结构，其所形成的第二鳍部的宽度与所述鳍部的宽度相同，在晶体管加电工作时容易产生自热效应，降低半导体器件的电学特性和稳定性。以下将结合附图进行说明。
图1至图4是一种半导体结构的形成过程的剖面结构示意图。
请参考图1，提供衬底100，所述衬底100具有初始鳍部110，所述初始鳍部110包括第一区111和位于所述第一区111上的第二区112；在所述衬底100上形成隔离层102，所述隔离层102覆盖所述第一区111和所述第二区112的侧壁且暴露出所述第二区112的顶部表面。
请参考图2，去除所述第二区112(如图1所示)，在所述隔离层102内形成初始开口130。
请参考图3，在所述初始开口130(如图2所示)内形成第二鳍部121，所述第二鳍部121位于所述第一区111上。
请参考图4，刻蚀所述隔离层102，暴露出所述第二鳍部121的部分侧壁。
随着半导体器件的密度提高，所述第二鳍部121可采用SiGe材料层作为上层沟道材料层，可以使晶体管在打开状态时具有较大的电流；所述第一区111可采用Si材料层作为下层沟道材料层，可以使晶体管在断开状态时具有较小的电流，由此使得晶体管的电学特性得到提高。但所述SiGe材料层的导热系数(随着Ge掺杂浓度呈现不同表现)小于所述Si材料层的导热系数(150W/mK)，在加电工作时，所述第二鳍部121所产生的热将得不到及时释放，堆积在沟道，导致沟道温度升高，发生自热效应。特别是随着半导体器件的尺寸愈小，器件的密集程度提高，所述自热效应将变得严重，引起器件的功率损失和电流输出能力下降，降低半导体器件的电学特性和稳定性，甚至引起功能失效。
为了解决上述技术问题，本发明提供了一种半导体结构的形成方法，在所述衬底上的第一隔离层内形成第一开口，并在第一开口的侧壁形成第二隔离层，通过对所述第一隔离层的侧壁进行刻蚀，由此增加了第二鳍部与所述第二隔离层的接触面积，从而改善自热效应。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图12是本发明实施例的半导体结构的形成过程的剖面结构示意图。
请参考图5，提供衬底200，所述衬底200上具有初始鳍部210，所述初始鳍部210包括第一区211，位于第一区211上的第二区212以及位于第二区212上的第三区213。
所述初始鳍部210还包括掩膜结构214，所述掩膜结构214位于所述第三区213上。
在本实施例中，所述掩膜结构214包括缓冲层201和位于缓冲层201上的硬掩膜层202。
在其他实施例中，所述掩膜结构214不包括缓冲层201。
在本实施例中，所述初始鳍部210的形成步骤包括：提供衬底200；在所述衬底200的表面形成缓冲膜，在所述缓冲膜上形成硬掩膜膜；在所述硬掩膜膜上形成初始图形化层，所述初始图形化层需要覆盖形成初始鳍部210的对应位置和形状；以所述初始图形化层为掩膜，刻蚀所述硬掩膜膜、所述缓冲膜和所述衬底200，形成所述初始鳍部210，所述初始鳍部210包括第一区211，位于第一区部211上的第二区212，位于第二区212上的第三区213以及位于所述第三区213上的掩膜结构214。
所述第一区211具有垂直于所述第一区211延伸方向的第一宽度D3，所述第一区211、第二区212和第三区213在垂直于所述第一区211延伸方向的宽度相同。
在本实施例中，所述初始图形化层为光刻胶层，采用涂布工艺和光刻工艺形成。在另一实施例中，为了缩小所述初始鳍部210的特征尺寸，以及相邻初始鳍部210之间的距离，所述光刻胶层采用多重图形化掩膜工艺形成。
所述衬底200的材料可以是单晶硅、多晶硅或者非晶硅，也可以是硅、锗、锗化硅、砷化镓等半导体材料；所述衬底200还可以是绝缘体上的硅、锗、锗化硅、砷化镓等半导体材料。
在本实施例中，所述半导体基底为单晶硅衬底。
在另一实施例中，所述第一区211、第二区212和第三区213通过刻蚀形成于所述衬底200表面的半导体层上；所述半导体层采用选择性外延沉积工艺形成于所述衬底200的表面。所述衬底为硅、锗、锗化硅等衬底，也可以为绝缘体上硅、锗、锗化硅等衬底；所述衬底还可以为玻璃衬底或者III-V族化合物衬底。所述半导体层的材料为硅、锗、碳化硅或硅锗。
所述掩膜结构214作为后续形成的第一隔离膜的研磨停止层，可以利用所述掩膜结构214与第一隔离膜之间的研磨速率差来判断研磨终点。一旦检测到研磨速率发生较大变化时，就表明研磨已经达到所述掩膜结构214，可以停止研磨，从而有效防止过研磨的发生。
所述掩膜结构214是单层和多层叠加结构中的一种。所述掩膜结构214的材料可以是氮化硅、氮氧化硅、非晶碳、氮化硼、氮化钛或其他可作为研磨停止层材料等中的一种或多种组合。
所述缓冲层201用于避免在所述衬底200上直接生长硬掩膜层202时产生位错，从而导致应力不匹配而产生膜层缺陷。
所述缓冲层201和所述硬掩膜层202的形成方法为化学气相沉积工艺、物理气相沉积工艺、热氧化生长和原子层沉积工艺的一种或多种组合。
请参考图6，在所述衬底200上形成第一隔离层203，所述第一隔离层203暴露出所述初始鳍部210的顶部表面。
所述第一隔离层203的形成工艺步骤包括：在所述衬底上200形成第一隔离膜，所述第一隔离膜覆盖所述初始鳍部210的侧壁和顶部表面；对所述第一隔离膜进行平坦化，直至暴露出所述初始鳍部210的顶部表面。
所述第一隔离层203的材料包括氧化硅或氮氧化硅。
在本实施例中，所述第一隔离层203的材料为氧化硅。所述隔离膜的形成工艺为流体化学气相沉积工艺(Flowable Chemical Vapor Deposition，简称FCVD)。
在其他实施例中，所述第一隔离膜还能够采用其他化学气相沉积工艺或物理气相沉积工艺形成；所述其他化学气相沉积工艺包括等离子体增强化学气相沉积工艺(PECVD)或者高深宽比化学气相沉积工艺(HARP)。
请参考图7，去除所述初始鳍部210(如图6所示)的掩膜结构214(如图6所示)和第三区213(如图6所示)，在所述第一隔离层内203形成第一开口215。
采用第一刻蚀工艺在所述第一隔离层203内形成所述第一开口215，所述第一开口215的侧壁用于后续形成第二隔离层。
所述第一刻蚀工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
在本实施例中，所述第一刻蚀工艺为各向异性的干法刻蚀工艺。
在另一实施例中，采用基于F的蚀刻气氛进行化学刻蚀，所述蚀刻气体可以选用C4F8、C4F6、C5F8和C3H8中的一种或多种组合，刻蚀功率为300W～400W，刻蚀压强为10mtorr～30mtorr。
请参考图8，在所述第一开口215的侧壁形成第二隔离层204。
通过所述第二隔离层204的不同厚度，可以控制后续形成的第五区具有的第三宽度，有利于提高器件集成度。
在所述第一开口215的侧壁形成第二隔离层204的形成步骤包括：在所述第一隔离层203上形成第二隔离膜，所述第二隔离膜还覆盖所述第一开口215的侧壁和底部；去除所述第一开口215底部和所述第一隔离层203顶部的第二隔离膜，在所述第一开口215的侧壁形成第二隔离层204。
所述第二隔离膜的形成工艺为化学气相沉积工艺和原子层沉积工艺的一种或两种组合。
在本实施例中，所述第二隔离膜的形成工艺为原子层沉积工艺；去除第一开口215底部和第一隔离层203顶部的第二隔离膜的工艺为各向异性的干法刻蚀工艺。
所述第二隔离层204的材料与所述第一隔离层203的材料相同或不同。
所述第二隔离层204的材料包括氮化硅、氧化硅或氮氧化硅。
在本实施例中，所述第二隔离层204的材料为氮化硅。
在本实施例中，所述第二隔离层204的厚度为20埃～50埃。所述第二隔离层204的厚度过小时，在干法刻蚀工艺的过程中等离子体容易造成所述第二隔离膜的损伤，由此在后续进行第三刻蚀工艺时所述第二隔离层204无法对所述第一开口215的侧壁形成有效保护，从而导致所述第一开口215侧壁的第一隔离层203被刻蚀，后续形成的第五区的侧壁形貌受到影响，对半导体器件工作时的电学特性产生不利影响；而当所述第二隔离层204的厚度过大时，所述第二隔离层204在后续去除第二区212的过程中将导致所述第二区212的残留，后续难以形成初始第二开口。
请参考图9，在形成所述第二隔离层204之后，去除第一开口215底部的所述第二区212(如图8所示)，形成与第一开口215底部贯通的初始第二开口216和位于所述初始第二开口216底部的第一鳍部230。
所述第一鳍部230具有垂直于所述第一鳍部延伸方向的第一宽度D3。
所述初始第二开口216暴露出所述第一鳍部230的顶部表面和所述第一隔离层203的部分侧壁。通过所述初始第二开口216对暴露出的所述第一隔离层203的部分侧壁进行刻蚀，用于形成后续的第二开口。
去除所述第一开口215底部的第二区212的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
在本实施例中，采用第二刻蚀工艺去除所述第一开口215底部的第二区212。
在本实施例中，所述第二刻蚀工艺为各向异性的干法刻蚀。
在另一实施例中，采用基于F的蚀刻气氛进行化学刻蚀，所述蚀刻气体可以选用C4F8、C4F6、C5F8和C3H8中的一种或多种组合，刻蚀功率为300W～400W，刻蚀压强为10mtorr～30mtorr。
请参考图10，对所述初始第二开口216(如图9所示)的侧壁进行刻蚀以形成第二开口217，所述第二开口217的侧壁暴露所述第一隔离层203。
所述第二开口217用于后续形成第四区。所述第二开口217具有垂直于所述第一鳍部延伸方向的第二宽度D4，对所述初始第二开口216的侧壁进行刻蚀，后续形成的第四区具有的第二宽度D4大于所述第一鳍部230具有的第一宽度D3，由此增加第二鳍部与所述第一隔离层203的接触面积，使得半导体结构工作时产生的热量更容易通过衬底向外扩散，由此改善自热效应，提高了半导体结构的电学稳定性和可靠性。
采用第三刻蚀工艺对所述初始第二开口216的侧壁进行刻蚀。通过控制第三刻蚀工艺的刻蚀时间，实现对后续形成的第四区的第二宽度的调控，提高了工艺的灵活性，为改善半导体结构的电学稳定性和可靠性提供工艺窗口。
所述第三刻蚀工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
在本实施例中，所述第三刻蚀工艺为湿法刻蚀工艺和干法蚀刻工艺的组合工艺。先采用湿法刻蚀对所述初始第二开口216进行清洗，确保后续形成的第二开口217内的清洁度；再采用干法刻蚀工艺对所述初始第二开口216的侧壁暴露出的第一隔离层203进行刻蚀，形成所述第二开口217。
请参考图11，在所述第一开口215(如图10所示)和所述第二开口216(如图10所示)内形成第二鳍部220。
所述第二鳍部220包括位于所述第二开口内的第四区222以及所述第一开口内的第五区221，且所述第四区222位于所述第一鳍部230上，所述第五区221位于所述第四区222上。
所述第一鳍部230具有垂直于所述第一鳍部延伸方向的第一宽度D3；所述第四区222具有垂直于所述第一鳍部延伸方向的第二宽度D4，所述第五区221具有垂直于所述第一鳍部延伸方向的第三宽度D5；所述第二宽度D4大于所述第一宽度D3，所述第一宽度D3大于所述第三宽度D5。
在所述第一开口215和所述第二开口216内形成第二鳍部220的步骤包括：在所述第一开口215和所述第二开口216内填充半导体膜。
所述半导体膜的材料包括SiB、SiGe、SiC、SiP、SiAs、SiGeB、SiCB、GaN、lnAs和InP。
在另一实施例中，所述半导体膜材料还包括Ge、GeSn、III-V化合物半导体和II-VI化合物半导体。在另一实施例中，所述半导体膜材料为SiC，其具有在0.2％至4.0％之间的替位碳的原子碳浓度。
形成所述半导体膜的工艺为外延生长工艺。所述外延生长工艺为减压外延、低温外延、选择外延、液相外延、异质外延、分子束外延中的一种或多种组合。
在本实施例中，所述半导体膜的材料为SiGe，形成所述半导体膜的工艺参数包括：采用的气体包括H2、HCl、二氯硅烷和GeH4，H2的气体流量为1000sccm～30000sccm，HCl的气体流量为10sccm～200sccm，二氯硅烷(SiH2Cl2，简称DCS)的气体流量为20sccm～2000sccm，GeH4的气体流量为10sccm～500sccm；压强为8torr～300torr，工艺温度为600℃～850℃。
在另一实施例中，所述外延生长工艺的同时还可以进行掺杂，例如在SiGe半导体膜掺杂B、P或As。在外延所述SiGe膜时通入GeH4，并选择H2作为载气，选择SiH2Cl2作为反应气体，外延得到的所述SiGe半导体膜中Si和Ge的含量比为10:1～6:4。在外延SiGe半导体膜的同时，还可以通入砷烷AsH3、磷烷PH3或者硼烷BH3进行掺杂。
在另一实施例中，在所述第一开口215和所述第二开口216内形成第二鳍部220的步骤还包括：对所述半导体膜进行CMP，暴露出所述第一隔离层203的顶部表面。
请参考图12，在形成所述第二鳍部220之后，刻蚀所述第一隔离层203和所述第二隔离层204，暴露出所述第五区221的部分侧壁。
刻蚀所述第一隔离层203和所述第二隔离层204的工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
在本实施例中，采用干法刻蚀工艺对所述第一隔离层203和所述第二隔离层204进行刻蚀。所述干法刻蚀工艺的工艺参数包括：采用的工艺气体包括He、NH3和NF3，所述He的气体流量为600sccm～～2000sccm，所述NH3的气体流量为200sccm～～500sccm，所述NF3的气体流量为20sccm～～200sccm，工艺压强为2torr～10torr，工艺时间为35秒～500秒。
在一实施例中，采用稀释的氢氟酸(DHF)对所述第一隔离层203和所述第二隔离层204进行刻蚀。
在另一实施例中，采用Siconi工艺刻蚀述第一隔离层206和第二隔离层208。所述Siconi工艺的工艺气体包括NF3和NH3，且所述Siconi工艺包括远程等离子体刻蚀和原位退火两个步骤：首先将NF3和NH3转变成氟化氨(NH4F)和二氟化氨(NH4F2)的等离子体，所述等离子体与所述第一隔离层203和所述第二隔离层204反应，形成六氟硅氨((NH4)SiF6)；其次，采用原位退火使得六氟硅氨分解为气态的四氟化硅(SiF4)、氨气(NH3)和氟化氢(HF)并被抽离。
相应的，本实施例还提供一种半导体结构，请参考图12，包括：衬底200，所述衬底200具有第一鳍部230，所述第一鳍部230具有垂直于所述第一鳍部延伸方向上的第一宽度D3；位于所述第一鳍部230上的第二鳍部220，所述第二鳍部220包括位于所述第一鳍部230上的第四区222，以及位于第四区222上的第五区221；所述第四区222具有垂直于所述第一鳍部延伸方向的第二宽度D4；所述第五区221具有垂直于所述第一鳍部延伸方向的第三宽度D5；所述第二宽度D4大于所述第一宽度D3，所述第一宽度D3大于所述第三宽度D5；覆盖所述第五区221的部分侧壁的第二隔离层204；覆盖所述第一鳍部230的侧壁、所述第二鳍部220的第四区222侧壁和所述第二隔离层204侧壁的第一隔离层203。
所述第二鳍部220的材料、尺寸和结构均参考前述实施例。
所述第一隔离层203的包括氧化硅或氮氧化硅。
所述第二隔离层204的材料与所述第一隔离层的材料相同或不同。
所述第一隔离层203和第二隔离层204的材料、尺寸和结构均参考前述实施例。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底具有初始鳍部，所述初始鳍部包括第一区，位于第一区上的第二区以及位于第二区上的第三区；
在所述衬底上形成第一隔离层，所述第一隔离层暴露出所述初始鳍部的顶部表面；
去除所述第三区，在所述第一隔离层内形成第一开口；
在所述第一开口的侧壁形成第二隔离层；
在形成所述第二隔离层之后，去除第一开口底部的第二区，形成与第一开口底部贯通的初始第二开口和位于所述初始第二开口底部的第一鳍部；
对所述初始第二开口的侧壁进行刻蚀以形成第二开口，所述第二开口的侧壁暴露所述第一隔离层；
在所述第一开口和所述第二开口内形成第二鳍部；
刻蚀所述第一隔离层和第二隔离层，暴露出所述第二鳍部的部分侧壁。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二鳍部包括位于所述第二开口内的第四区以及所述第一开口内的第五区，且所述第四区位于所述第一鳍部上，所述第五区位于所述第四区上。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述第一鳍部具有垂直于所述第一鳍部延伸方向的第一宽度；所述第四区具有垂直于所述第一鳍部延伸方向的第二宽度；所述第五区具有垂直于所述第一鳍部延伸方向的第三宽度；所述第二宽度大于所述第一宽度，所述第一宽度大于所述第三宽度。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，采用第三刻蚀工艺对所述初始第二开口的侧壁进行刻蚀。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，所述第三刻蚀工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述第一开口的侧壁形成第二隔离层的工艺步骤包括：在所述第一隔离层上形成第二隔离膜，所述第二隔离膜还覆盖所述第一开口的侧壁和底部；去除第一开口底部和第一隔离层顶部的第二隔离膜，在所述第一开口的侧壁形成第二隔离层。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述第二隔离膜的材料与所述第一隔离层的材料相同或不同。
8.如权利要求6所述的半导体结构的形成方法，其特征在于，去除所述第二隔离膜的工艺为各向异性的干法刻蚀工艺。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，去除所述第一开口底部的第二区的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述第一开口和所述第二开口内形成第二鳍部的步骤包括：在所述第一开口和所述第二开口填充半导体膜。
11.如权利要求10所述的半导体结构的形成方法，其特征在于，形成所述半导体膜的工艺为外延生长工艺。
12.如权利要求11所述的半导体结构的形成方法，其特征在于，所述半导体膜的材料包括SiB、SiGe、SiC、SiP、SiAs、SiGeB、SiCB、GaN、lnAs和InP。
13.如权利要求1所述的半导体结构的形成方法，其特征在于，去除所述第三区的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。
14.如权利要求1所述的半导体结构的形成方法，其特征在于，所述初始鳍部还包括掩膜结构，所述掩膜结构位于所述第三区上；去除所述第三区还包括去除所述掩膜结构。
15.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一隔离层的形成工艺步骤包括：在所述衬底上形成第一隔离膜，所述第一隔离膜覆盖所述初始鳍部的侧壁和顶部表面；对所述第一隔离膜进行平坦化，直至暴露出所述初始鳍部的顶部表面。
16.如权利要求15所述的半导体结构的形成方法，其特征在于，所述第一隔离层的材料包括氧化硅或氮氧化硅。
17.如权利要求1所述的半导体结构的形成方法，其特征在于，刻蚀所述第一隔离层和第二隔离层的工艺为湿法刻蚀工艺和干法刻蚀工艺的一种或两种组合。
18.一种半导体结构，其特征在于，包括：
衬底，所述衬底具有第一鳍部，所述第一鳍部具有垂直于所述第一鳍部延伸方向上的第一宽度；
位于所述第一鳍部上的第二鳍部，所述第二鳍部包括位于所述第一鳍部上的第四区，以及位于第四区上的第五区；所述第四区具有垂直于所述第一鳍部延伸方向的第二宽度；所述第五区具有垂直于所述第一鳍部延伸方向的第三宽度；所述第二宽度大于所述第一宽度，所述第一宽度大于所述第三宽度；
覆盖所述第五区的部分侧壁的第二隔离层；
覆盖所述第一鳍部的侧壁、所述第二鳍部的第四区侧壁和所述第二隔离层侧壁的第一隔离层。
19.如权利要求18所述的半导体结构的形成方法，其特征在于，所述第一隔离层的材料包括氧化硅或氮氧化硅。
20.如权利要求18所述的半导体结构的形成方法，其特征在于，所述第二隔离膜的材料与所述第一隔离层的材料相同或不同。
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