TWI431778B - 鰭式場效應電晶體及其製造方法 - Google Patents

鰭式場效應電晶體及其製造方法 Download PDF

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TWI431778B
TWI431778B TW100106853A TW100106853A TWI431778B TW I431778 B TWI431778 B TW I431778B TW 100106853 A TW100106853 A TW 100106853A TW 100106853 A TW100106853 A TW 100106853A TW I431778 B TWI431778 B TW I431778B
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top surface
fin
field effect
effect transistor
tapered
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TW201216467A (en
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Hung Ta Lin
Chu Yun Fu
Shin Yeh Huang
Shu Tine Yang
Hung Ming Chen
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Taiwan Semiconductor Mfg
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Description

鰭式場效應電晶體及其製造方法
本發明係有關於積體電路的製造，且特別是有關於一種鰭式場效應電晶體。
隨著半導體工業進展至奈米技術製程節點，為了追求更高的裝置密度、較高的性能、及較低的成本，其在製造及設計方面都面臨挑戰，因而發展出三維設計，例如鰭式場效應電晶體(FinFET)。典型鰭式場效應電晶體的製造為利用如蝕刻基板的部分矽層而形成延伸自基板的垂直薄鰭板(或鰭板結構)。在垂直鰭板中形成鰭式場效電晶體的通道。在鰭板上提供(例如為包覆)閘極。在通道的兩側都具有閘極使得閘極可由兩側控制通道。此外，在鰭式場效應電晶體的凹陷源極/汲極區中利用選擇性成長矽鍺(SiGe)應力材料，可以提升載子遷移率。
然而，在互補型金氧半(CMOS)製程中製造上述元件為一大挑戰。例如，應力材料不平均的分佈會造成應力不平均的施加在鰭式場效應電晶體的通道區，因此增加裝置不穩定及/或裝置失效的可能性。
據此，業界亟需一種改良的裝置及應力結構的製造方法。
在一實施例中，鰭式場效應電晶體(FinFET)包括具有頂表面的基板；具有漸細的頂表面(tapered top surface)的基板頂表面上之第一絕緣區及第二絕緣區；基板的鰭板延伸至基板頂表面上介於第一及第二絕緣區間，其中鰭板包括凹陷部分，其具有頂表面低於第一及第二絕緣區的漸細的頂表面，其中鰭板包括非凹陷部分，其具有頂表面高於漸細的頂表面；以及在鰭板非凹陷部分上的閘極堆疊。
在另一實施例中，鰭式場效應電晶體(FinFET)包括具有頂表面的基板；具有漸細的頂表面(tapered top surface)的基板頂表面上之第一絕緣區及第二絕緣區，其中漸細的頂表面包括在漸細的頂表面中間的最高點；基板的鰭板延伸至基板頂表面上介於第一及第二絕緣區間，其中鰭板包括凹陷部分，其具有頂表面低於第一及第二絕緣區的漸細的頂表面，其中鰭板包括非凹陷部分，其具有頂表面高於漸細的頂表面；以及在鰭板非凹陷部分上的閘極堆疊。
在另一實施例中，鰭式場效應電晶體(FinFET)的製造方法包括提供具有第一絕緣區及第二絕緣區的基板，第一及第二絕緣區具有個別的頂表面，以及鰭板介於第一及第二絕緣區，其中第一及第二絕緣區的頂表面低於鰭板的頂表面；在部分鰭板上及部分第一及第二絕緣區上形成閘極堆疊；凹陷鰭板上未被閘極堆疊覆蓋的部分，以在第一及第二絕緣區的頂表面下形成鰭板的凹陷部分；蝕刻第一及第二絕緣區未被閘極堆疊覆蓋的部分頂表面的角落，以形成第一及第二絕緣區的漸細的頂表面；以及在鰭板的凹陷部分及第一及第二絕緣區的漸細的頂表面上選擇性成長應力材料。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
因本發明之不同特徵而提供數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。以下將配合所附圖式詳述本發明之實施例，其中同樣或類似的元件將盡可能以相同的元件符號表示。在圖式中可能誇大實施例的形狀與厚度以便清楚表面本發明之特徵。在下文中將特別描述本發明裝置之元件或與之直接相關之元件。應特別注意的是，未特別顯示或描述之元件可以該技術人士所熟知之各種形式存在。此外，當某一層是被描述為在另一層(或基材)”上”時，其可代表該層與另一層(或基材)直接接觸，或兩者之間另有其他層存在。此外，此處為簡明起見，在不同例子中以重複的元件符號及/或字母表示，但並未代表所述各實施例及/或結構間的關係。
參照第1圖，顯示根據本發明數個實施例製造鰭式場效應電晶體(FinFET)的方法100之流程圖。在方法100中，首先為步驟102，提供基板。方法100接下來的步驟104為在基板中形成鰭板。方法100接下來的步驟106為在基板上沉積介電材料以及移除介電材料的頂部以形成第一及第二絕緣區，使得第一及第二絕緣區的頂表面低於鰭板的頂表面。方法100而後在步驟108中為在部分鰭板以及在部分第一及第二絕緣區上形成閘極堆疊。方法100接著在步驟110中為凹蝕鰭板未被閘極堆疊覆蓋的部分，以在第一及第二絕緣區下形成鰭板的凹陷部分。方法100之步驟112為蝕刻第一及第二絕緣區未被閘極堆疊覆蓋的頂表面的角落，以形成第一及第二絕緣區漸細的頂表面。方法100接下來的步驟114為在鰭板的凹陷部分以及第一及第二絕緣區之漸細的頂表面上選擇性成長應力材料。
在本發明中，鰭式場效應電晶體200為任何具鰭板、多閘極電晶體。鰭式場效應電晶體200可包括微處理器(microprocessor)、記憶體單元(memory cell)、及/或其他積體電路(IC)。應注意第1圖的方法並未製造完整的鰭式場效應電晶體200。完整的鰭式場效應電晶體200的製造可利用互補型金氧半(CMOS)技術製程。因此，應了解在第1圖的方法100之前、之間、及之後可提供額外的步驟，且部分其他製程在此可僅簡略的敘述。此外，為了更清楚的了解本發明的發明概念，第1至10C圖已簡化。例如，雖然圖式顯示鰭式場效應電晶體200，應了解積體電路可包括許多其他裝置包括電阻、電容、感應器、保險絲等。
參照第2A至10C圖，顯示本發明各實施例製造鰭式場效應電晶體200的各階段之各透視圖及剖面圖。
第2A圖為根據一實施例，具有基板202的鰭式場效應電晶體200在一製造階段的透視圖。第2B圖為第2A圖鰭式場效應電晶體沿著線a-a的剖面圖。在一實施例中，基板202包括多晶矽基板(例如晶圓)。基板202可根據設計需求而包括各摻雜區(例如為p型基板或n型基板)。在一些實施例中，摻雜區可為p型或n型摻質摻雜。例如，摻雜區可為p型摻質摻雜，例如為硼或BF2 ；n型摻質，例如為磷或砷；及/或前述之組合。摻雜區的配置可為了n型鰭式場效應電晶體，或者可為了p型鰭式場效應電晶體。
在一些其他實施例中，基板202的形成可由一些適合的元素半導體，例如鑽石或鍺；適合的化合物半導體，例如為砷化鎵(gallium arsenide)、碳化矽(silicon carbide)、砷化銦(indium arsenide)、或磷化銦(indium phosphide)；或適合的合金半導體，例如碳鍺矽(silicon germanium carbide)、磷砷鎵(gallium arsenic phosphide)、或磷銦鎵(gallium indium phosphide)。此外，基板202可包括磊晶層(epi-layer)，其可具有應變以提升效能，及/或可包括絕緣層上有矽(silicon-on-insulator;SOI)結構。
對基板202進行蝕刻以形成鰭板。在一實施例中，在半導體基板202上形成墊層204a及罩幕層204b。墊層204a可為薄膜包括例如以熱氧化製程(thermal oxidation process)形成氧化矽。墊層204a可作為介於半導體基板202及罩幕層204b的黏著層。墊層204a也可作為蝕刻罩幕層204b的蝕刻停止層。在至少一實施例中，以氮化矽形成罩幕層204b，例如利用低壓化學氣相沉積(低壓化學氣相沉積)或電漿輔助化學氣相沉積(PECVD)。在後續微影製程中，以罩幕層204b作為硬罩幕。在罩幕層204b上形成感光(photo-sensitive)層206，而後圖案化，以在感光層206中形成開口208。
第3A圖為根據一實施例鰭式場效應電晶體在一製造階段的透視圖，而第3B圖為鰭式場效應電晶體沿著第3A圖的線a-a的剖面圖。經由開口208蝕刻罩幕層204b及墊層204a以暴露出下方的半導體基板202。而後蝕刻暴露的半導體基板202以形成具有半導體基板202的頂表面202s的溝槽210。半導體基板202在溝槽210間的部分形成半導體鰭板212。溝槽210可為彼此平行的條狀(由鰭式場效應電晶體200的頂部來看)，且彼此間緊鄰相隔。溝槽210各具有寬度W、深度D、以及使相鄰溝槽分開的間隔S。例如，在溝槽210間的間隔S可小於30奈米。而後移除感光層206。接著，可進行清洗以移除半導體基板202的原生氧化物(native oxide)。可利用稀氫氟酸(DHF)進行清洗。
在一些實施例中，溝槽210的深度D的範圍可介於約2100埃至約2500埃，而溝槽210的寬度W的範圍可介於約200埃至約1500埃。在一實施例中，溝槽210的深寬比(D/W)可大於約7.0。在一些其他實施例中，深寬比甚至可大於約8.0。在又一些實施例中，深寬比低於約7.0或介於7.0至8.0。然而，本領域具通常知識者可了解所述尺寸及數值僅為舉例，可依照積體電路的不同尺寸而改變。
而後視需要在溝槽210中形成襯層氧化物(未顯示)。在一實施例中，襯層氧化物可為熱氧化物，具有厚度範圍介於約20埃至500埃。在一些實施例中，襯層氧化物的形成可利用臨場蒸氣產生技術(in-situ steam generation;ISSG)等。襯層氧化物的形成使溝槽210的角落變圓，而降低電場，且因此提升所得積體電路的性能。
第4A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第4B圖為鰭式場效應電晶體沿著第4A圖的線a-a的剖面圖。介電材料214填入溝槽210中。介電材料214可包括氧化矽，因此在本發明中也稱為氧化物214。在一些實施例中，也可用其他介電材料，例如氮化矽、氮氧化矽、氟摻雜矽玻璃(fluoride-doped silicate glass;FSG)、或低介電常數介電材料。在一實施例中，氧化物214的形成可利用高密度電漿(high-density-plasma;HDP)化學氣相沉積製程，利用矽烷(silane)及氧作為反應前驅物。在其他實施例中，氧化物214的形成可利用次壓化學氣相沉積(sub-atmospheric CVD;SACVD)製程或高深寬比製程(high aspect ratio process;HARP)，其中製程氣體可包括四乙氧基矽烷(tetraethylorthosilicate;TEOS)及/或臭氧(O3 )。在另一其他實施例中，氧化物214的形成可利用旋塗介電質(spin-on dielectric;SOD)製程，例如氫矽酸鹽(hydrogen silsesquioxane;HSQ)或甲基矽酸鹽(methyl silsesquioxane;MSQ)。
第4A及4B圖描繪在介電材料214沉積後所形成的結構。而後進行化學機械研磨，接著移除罩幕層204b及墊層204a。所形成的結構如第5A及5B圖所示。第5A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第5B圖為鰭式場效應電晶體沿著第5A圖的線a-a的剖面圖。在溝槽210中剩餘的氧化物214部分此後稱為絕緣區216。在至少一實施例中，由氮化矽形成罩幕層204b，罩幕層204b的移除可利用熱磷酸的濕製程，而墊層204a若為氧化矽所形成，則其移除可利用稀氫氟酸。在一些其他實施例中，在凹蝕絕緣區216之後可進行罩幕層204b及墊層204a的移除，凹蝕步驟如第6A及6B圖所示。
第5A及5B圖顯示化學機械研磨製程及移除罩幕層204b及墊層204a所形成的結構。而如第6A及6B圖所示，藉由蝕刻步驟凹蝕絕緣區216，形成凹陷218。在一實施例中，蝕刻步驟的進行可利用濕蝕刻製程，例如將基板浸泡在氫氟酸中。在另一實施例中，蝕刻步驟的進行可利用乾蝕刻製程，例如乾蝕刻製程的進行可利用三氟甲烷(CHF3 )或氟化硼(BF3 )作為蝕刻氣體。
剩餘的絕緣區216可包括平的頂表面216t。剩餘的絕緣區216可包括第一絕緣區216a及第二絕緣區216b。並且，半導體鰭板212的上方部分222突出超過剩餘的絕緣區216的平的頂表面216t，因此用以形成鰭式場效應電晶體200的通道區。半導體鰭板212的上方部分222可包括頂表面222t及側壁222s。半導體鰭板212的上方部分222的高度H可介於約15奈米至約50奈米。在一些實施例中，高度H大於50奈米或小於15奈米。為了簡化，在第一及第二絕緣區216a、216b間的半導體鰭板212的上方部分222之後稱為通道鰭板222a，以顯示半導體鰭板212的各個上方部分，其中，第一及第二絕緣區216a、216b的平的頂表面216t低於半導體鰭板212的頂表面222t。
製程步驟至此已提供基板202，其具有各具頂表面216t的第一絕緣區216a及第二絕緣區216b，以及介於第一及第二絕緣區216a、216b間的鰭板212，其中，第一及第二絕緣區的頂表面216t低於鰭板212的頂表面222t。
第7A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第7B圖為鰭式場效應電晶體沿著第7A圖的線a-a的剖面圖。在基板上的通道鰭板222a非凹陷部分的頂表面222t及側壁222s上形成閘極堆疊220，且延伸至第一及第二絕緣區216a、216b的平的頂表面216t。在一些實施例中，閘極堆疊220包括閘極介電層220a及在閘極介電層220a上的閘極電極層220b。
在第7A及7B圖中，形成閘極介電層220a以覆蓋通道鰭板222a的頂表面222t及側壁222s。在一些實施例中，閘極介電層220a可包括氧化矽、氮化矽、氮氧化矽、或高介電常數介電質。高介電常數介電質包括金屬氧化物。金屬氧化物作為高介電常數介電質的例子包括鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、鎦(Lu)之氧化物、及/或前述之混合。在本發明一實施例中，閘極介電層220a為高介電常數介電層，其厚度介於約10至30埃。閘極介電層220a的形成可利用適當的製程，例如原子層沉積(atomic layer deposition;ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化(thermal oxidation)、紫外線-臭氧氧化(UV-ozone oxidation)、或前述之組合。閘極介電層220a可更包括介面層(未顯示)以減少在閘極介電層220a及通道鰭板222a間的損害。介面層可包括氧化矽。
而後在閘極介電層220a上形成閘極電極層220b。在至少一實施例中，閘極電極層220b覆蓋一個以上的半導體鰭板212的上方部分222，使得所形成的鰭式場效應電晶體200包括一個以上的鰭板。在一些另外的實施例中，各個半導體鰭板212的上方部分222可用以形成個別的鰭式場效應電晶體200。在一些實施例中，閘極電極層220b可包括單層或多層。在本發明一實施例中，閘極電極層220b可包括多晶矽。再者，可平均或不平均的摻雜閘極電極層220b。在一些另外的實施例中，閘極電極層220b可包括金屬，例如為鋁、銅、鎢、鈦、鉭、氮化鈦、鋁化鈦、氮鋁化鈦、氮化鉭、矽化鎳、矽化鈷、其他與基板材料的功函數可相容的導電材料、或前述之組合。在本發明一實施例中，閘極電極層220b包括厚度介於約30奈米至約60奈米。閘極電極層220b的形成可利用適當的製程例如為原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍、或前述之組合。
仍舊參照第7A圖，鰭式場效應電晶體200更包括在基板202上及沿著閘極堆疊220的旁邊形成介電層224。在一些實施例中，介電層224可包括氧化矽、氮化矽、氮氧化矽、或其他適合的材料。介電層224可包括單層或多層。介電層224的毯覆層的形成可利用化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、或其他適當的技術。而後，在介電層224上進行非等向性蝕刻以在閘極堆疊220的兩側上形成介電層(一對間隙物)224。介電層224包括厚度介於約5至15奈米。
第8A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第8B圖為鰭式場效應電晶體沿著第8A圖的線b-b的剖面圖。凹蝕半導體鰭板212未被閘極堆疊220及介電層(間隙物)224覆蓋的部分，而形成半導體鰭板212的凹陷部分226，其頂表面212r低於第一及第二絕緣區216a、216b的平的頂表面216t。在一實施例中，利用一對介電層(間隙物)224作為硬罩幕，進行偏壓蝕刻(biased etching)製程以凹蝕通道鰭板222a的頂表面222t未被保護或暴露出來的部分，而形成半導體鰭板212的凹陷部分226。在一實施例中，進行蝕刻製程的壓力可介於約1 mTorr至1000 mTorr，功率約50 W至1000 W，偏壓約20 V至500 V，溫度約40℃至60℃，蝕刻氣體係利用溴化氫(HBr)或氯氣(Cl2 )。並且，在一提供的實施例中，可調整蝕刻製程中所使用的偏壓以更好的控制蝕刻方向，而使得半導體鰭板212的凹陷部分226可達到預先設計的樣式。
第9A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第9B圖為鰭式場效應電晶體沿著第9A圖的線b-b的剖面圖。在形成半導體鰭板212的凹陷部分226之後，蝕刻第一及第二絕緣區216a、216b的平的頂表面216t未被閘極堆疊220覆蓋的角落部分，以形成第一及第二絕緣區216a、216b的漸細的頂表面216u。在一實施例中，進行蝕刻步驟可利用濕蝕刻製程，例如將基板202浸入氫氟酸(HF)中。在另一實施例中，進行蝕刻步驟可利用無偏壓乾蝕刻(non-biased dry etching)製程，例如可利用三氟甲烷(CHF3 )或氟化硼(BF3 )為蝕刻氣體進行乾蝕刻製程。
在一實施例中，第一及第二絕緣區216a、216b的漸細的頂表面216u包括平的部分及坡度或斜面的側壁(如第9A及9B圖所示)。因此，漸細的頂表面216u之平的部分的寬度W2 小於漸細的頂表面216u的最大寬度W1 。在一實施例中，平的部分的寬度W2 對第一絕緣區216a的最大寬度W3 的比例介於0.05至0.95。此外，漸細的頂表面216u的最低點與基板202的頂表面202s的距離D1 範圍介於約100至200奈米。
第9C圖為另一鰭式場效應電晶體200之實施例的剖面圖。在第9C圖所顯示的實施例中，移除第一及第二絕緣區216a、216b的平的頂表面216t未被閘極堆疊220覆蓋的角落，直到漸細的頂表面216u的平的部分消失，而使漸細的頂表面216u形成弧形的頂表面(如第9C圖所示)。可看出鄰近的半導體鰭板212間的空間具有中間線228，而漸細的頂表面216u鄰近中間線228的弧形頂表面高於漸細的頂表面216u鄰近半導體鰭板222的弧形頂表面。亦即，漸細的頂表面216u包括在漸細的頂表面216u的中間的最高點P。此外，漸細的頂表面216u的最低點與基板202的頂表面202s的距離D2 範圍介於約100至200奈米。在一實施例中，平的頂表面216t與漸細的頂表面216u的最高點P共平面。在另一實施例中，平的頂表面216t高於漸細的頂表面216u的最高點P。平的頂表面216t與漸細的頂表面216u的最高點P間的距離D3 範圍介於約0.1至0.3奈米。在又一實施例中，半導體鰭板212更包括在閘極堆疊220下的非凹陷部分，其具有一頂表面222t高於漸細的頂表面216u。半導體鰭板212非凹陷部分的頂表面222t與漸細的頂表面216u的最高點P間的距離D4 範圍介於約100至200奈米。
第10A圖為根據一實施例製造鰭式場效應電晶體200的一製造階段的透視圖，而第10B圖為鰭式場效應電晶體沿著第10A圖的線b-b的剖面圖。第10C圖為鰭式場效應電晶體200的另一實施例的剖面圖，具有應力材料230形成在第9C圖所示的結構上。在第10A、10B、及10C圖所示結構的形成係在半導體鰭板212的凹陷部分226上選擇性成長應力材料230，並延伸至第一及第二絕緣區216a、216b的漸細的頂表面上。由於應力材料230的晶格常數與基板202不同，因而在半導體鰭板212的通道區施以應力(strained)或應變(stressed)，以增進裝置的載子遷移率，而提升裝置性能。在至少一實施例中，利用低壓化學氣相沉積製程磊晶成長應力材料230，例如為碳化矽，以形成n型鰭式場效應電晶體的源極及汲極區。低壓化學氣相沉積製程的進行係在溫度約400至800℃，且壓力在約1至200 Torr下，利用丙矽烷(Si3 H8 )及甲基矽烷(SiH3 CH3 )為反應氣體。在至少一實施例中，利用低壓化學氣相沉積製程磊晶成長應力材料230，例如為矽鍺，以形成p型鰭式場效應電晶體的源極及汲極區。低壓化學氣相沉積製程的進行係在溫度約400至800℃，且壓力在約1至200 Torr下，利用甲矽烷(SiH4 )及甲鍺烷(GeH4 )為反應氣體。
在本發明一實施例中，持續進行應力材料230的磊晶成長，直到應力材料230垂直延伸至基板202的表面202a上方約10至100奈米的範圍，且側向延伸至第一及第二隔離區216a、216b的漸細的頂表面216u上。應注意在半導體鰭板212不同的凹陷部分226選擇性成長應力材料230時，第一及第二絕緣區216a、216b的漸細的頂表面216u更容易讓成長的前驅物到達成長表面，而消除在合併的應力材料230(merged strained material)下的空隙。在一些實施例中，所合併的應力材料230下的空隙降低應力材料230的應力效率，亦即，相較於其中沒有空隙形成的應力材料230，具有空隙的應力材料230在鰭式場效應電晶體的通道區提供較少的應力，因此使得裝置的不穩定性及/或裝置失效的可能性增加。在本發明一實施例中，當在不同凹陷部分226成長的應力材料230時，應力材料230實質上具有平的表面。據此，本發明鰭式場效應電晶體的製造方法，可製造降低空隙的應力結構，以增強載子遷移率及裝置性能。
應了解鰭式場效應電晶體200可進一步進行化學機械研磨製程以形成各種元件，例如接觸插塞/通孔、內連線金屬層、介電層、保護層等。經改良的絕緣及應力結構在鰭式場效應電晶體的通道區提供一定程度的應力，因此提升裝置的性能。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．方法
102、104、106、108、110、112、114．．．步驟
200．．．鰭式場效應電晶體
202．．．基板
204a．．．墊層
204b．．．罩幕層
206．．．感光層
208．．．開口
202s、216t、222t、212r．．．頂表面
210．．．溝槽
212．．．半導體鰭板
W、W1 、W2 、W3 ．．．寬度
D．．．深度
S．．．間隔
214．．．介電材料、氧化物
216．．．絕緣區
218．．．凹陷
216a．．．第一絕緣區
216b．．．第二絕緣區
222．．．上方部分
222s．．．側壁
H．．．高度
222a．．．通道鰭板
220．．．閘極堆疊
220a．．．閘極介電層
220b．．．閘極電極層
224．．．介電層
226．．．凹陷部分
216u．．．漸細的頂表面
D1 、D2 ．．．距離
228．．．中間線
P．．．最高點
230．．．應力材料
第1圖為根據本發明數個實施例，顯示鰭式場效應電晶體的製造方法的流程圖。
第2A、2B、3A、3B、4A、4B、5A、5B、6A、6B、7A、7B、8A、8B、9A~9C、10A~10C圖為根據本發明數個實施例，鰭式場效應電晶體的不同製造階段的透視圖及剖面圖。
200．．．鰭式場效應電晶體
202．．．基板
202s．．．頂表面
216a．．．第一絕緣區
216b．．．第二絕緣區
212．．．半導體鰭板
216u．．．漸細的頂表面
226．．．凹陷部分
230．．．應力材料

Claims (10)

  1. 一種鰭式場效應電晶體，包括：一基板，包括一頂表面；一第一絕緣區及一第二絕緣區，在該基板頂表面上，該第一及第二絕緣區具有漸細的頂表面；該基板的一鰭板，延伸超過該第一及第二絕緣區之間的該基板頂表面，其中該鰭板包括一凹陷部分，其具有一頂表面低於該第一及第二絕緣區的該漸細的頂表面，其中該鰭板包括一非凹陷部分，其具有一頂表面高於該漸細的頂表面；以及一閘極堆疊，在該鰭板的該非凹陷部分上。
  2. 如申請專利範圍第1項所述之鰭式場效應電晶體，其中該漸細的頂表面包括一平的部分及漸細的側壁。
  3. 如申請專利範圍第1項所述之鰭式場效應電晶體，其中該漸細的頂表面包括一弧形頂表面。
  4. 如申請專利範圍第1項所述之鰭式場效應電晶體，其中該漸細的頂表面包括在該漸細的頂表面的中間的一最高點。
  5. 如申請專利範圍第1項所述之鰭式場效應電晶體，其中該第一絕緣區更包括在該閘極堆疊下具有一平的頂表面的部分。
  6. 如申請專利範圍第5項所述之鰭式場效應電晶體，其中該漸細的頂表面的一平的部分的寬度小於該平的頂表面的最大寬度。
  7. 如申請專利範圍第5項所述之鰭式場效應電晶體，其中該平的頂表面與該漸細的頂表面的一最高點共平面。
  8. 如申請專利範圍第5項所述之鰭式場效應電晶體，其中該平的頂表面高於該漸細的頂表面的一最高點。
  9. 一種鰭式場效應電晶體的製造方法，包括：提供具有一第一絕緣區及一第二絕緣區的一基板，該第一及第二絕緣區分別具有頂表面，以及一鰭板介於該第一及第二絕緣區間，其中該第一及第二絕緣區的該頂表面低於該鰭板的一頂表面；在該鰭板的一部分上以及在該第一及第二絕緣區的一部分上形成一閘極堆疊；凹蝕該鰭板未被該閘極堆疊覆蓋的部分，以在該第一及第二絕緣區的該頂表面下形成該鰭板的一凹陷區；蝕刻該第一及第二絕緣區的該頂表面未被該閘極堆疊覆蓋的角落，以形成該第一及第二絕緣區的漸細的頂表面；以及在該鰭板的該凹陷部分上及該第一及第二絕緣區的該漸細的頂表面上選擇性成長一應力材料。
  10. 如申請專利範圍第9項所述之鰭式場效應電晶體的製造方法，其中該應力材料形成具有一大體上平的表面。
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US9379215B2 (en) 2016-06-28
US20160379977A1 (en) 2016-12-29
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