TWI625858B - 鰭式場效電晶體、半導體裝置及其製造方法 - Google Patents
鰭式場效電晶體、半導體裝置及其製造方法 Download PDFInfo
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- TWI625858B TWI625858B TW102143708A TW102143708A TWI625858B TW I625858 B TWI625858 B TW I625858B TW 102143708 A TW102143708 A TW 102143708A TW 102143708 A TW102143708 A TW 102143708A TW I625858 B TWI625858 B TW I625858B
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Classifications
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
Abstract
本發明係關於一半導體裝置之一接觸結構。在一實施例中,此半導體裝置之結構包含:一絕緣區於一基材上;一包含一閘極中線之閘極電極層於此絕緣層上;一包含一第一中線之第一接觸結構,位於此絕緣區上並鄰接此閘極電極;其中此第一中線與此閘極中線具有一第一距離;一包含一第二中線之第二接觸結觸結構,位於此絕緣區上及此閘極電極層之相對於此第一接觸結構之另一側上,其中此第二中線及此閘極中線具有一大於此第一距離之第二距離。
Description
本揭露係有關於積體電路之製造,且特別關於一具有接觸結構之半導體裝置。
隨著半導體工業踏入奈米製程節點以追求更高的裝置密度、更佳的效能及更低的成本,來自製造及設計上的挑戰造就了朝向立體(3D)設計發展的半導體裝置,例如鰭式場效電晶體(FinFET)。一般而言,鰭式場效電晶體係具有一薄而垂直的鰭狀物(或鰭式結構)自基材延伸,其可藉由例如蝕刻基材之部分的矽層形成。鰭式場效電晶體之通道形成於此垂直鰭狀物中。閘極係提供(例如包覆)於鰭狀物的三側上。閘極位於通道之兩側,以使閘極可同時由通道之兩側控制通道。此外,場效電晶體之源/汲極(S/D)部分中的應變材料係使用選擇性磊晶成長之鍺化矽,其可用以增進載子移動率。
然而,實際上在實施互補式金氧半場效電晶體(CMOS)製造中的這些製程及元件時,仍面臨挑戰。例如,如閘極包覆鰭狀物時,在源/汲極接觸結構及閘極之間的寄生電容會顯著增加,因而降低裝置效能。
本發明之一實施例係提供一種半導體裝置,包含:一絕緣區於一基材上;一包含一閘極中線之閘極電極層於此絕
緣層上;一包含一第一中線之第一接觸結構,位於此絕緣區上並鄰接此閘極電極;其中此第一中線與此閘極中線具有一第一距離;一包含一第二中線之第二接觸結觸結構,位於此絕緣區上及此閘極電極層之相對於此第一接觸結構之另一側上,其中此第二中線及此閘極中線具有一大於此第一距離之第二距離。
本發明之另一實施例亦提供一種鰭式場效電晶體,包含:一基材,包含一主要表面;一此基材之一第一鰭狀物及一此基材之一第二鰭狀物,其包含鰭頂面並自基材之此主要表面向上延伸;一包含一絕緣頂面之絕緣區,位於此主要表面上並位於此第一鰭狀物及此第二鰭狀物之間,其中此絕緣頂面低於此鰭頂面;一閘極電極層,位於此第一鰭狀物及此第二鰭狀物之間並延伸至此絕緣區上,其中位於此絕緣區上之一部分的此閘極電極層包含一閘極中線;一包含一第一中線之第一接觸結構,位於此絕緣區上並與此閘極電極層鄰接,其中此第一中線與此閘極中線具有一第一距離;以及一包含一第二中線之第二接觸結構,位於此絕緣區之相對於此閘極電極層之相對於此第一接觸結構之另一側上,其中此第二中線及此閘極中線具有一大於此第一距離之第二距離。
本發明之又一實施例更提供一種半導體裝置之製造方法,包含:提供一基材;形成此基材之一第一鰭狀物及此基材之一第二鰭狀物,其自此基材之一主要表面延伸向上,其中此第一鰭狀物及此第二鰭狀物包含鰭頂面;形成一絕緣區於此主要表面上及此第一鰭狀物及此第二鰭狀物之間,其中此絕緣區包含一絕緣表面低於這些鰭頂面;形成一閘極電極層,其位
於此第一鰭狀物及此第二鰭狀物之通道區部分上並延伸至一部分的此絕緣區上,其中位於此部分的此絕緣區上之一部分的此閘極電極層包含一閘極中線;形成一層間介電層環繞此絕緣區上之此閘極電極層;形成一第一開口及一第二開口於此絕緣區之此層間介電層上,其中此第一開口之一第一中線與此閘極中線之間之距離係與此第二開口之一第二中線與此閘極中線之間之距離不同;以及形成一金屬層於此第一開口及此第二開口中,以形成第一接觸結構及一第二接觸結構。
20‧‧‧基材
20s‧‧‧基材主要表面
200‧‧‧鰭式場效電晶體
202‧‧‧鰭式結構
202a‧‧‧第一鰭狀物
202b‧‧‧第二鰭狀物
202c‧‧‧通道部分
202d‧‧‧汲極部分
202s‧‧‧源極部分
202t‧‧‧鰭頂面
202u‧‧‧鰭式結構之上部部分
204‧‧‧絕緣區
204s‧‧‧絕緣頂面
206a‧‧‧溝槽
206b‧‧‧凹陷
208‧‧‧應變材料
210‧‧‧閘極堆疊
212‧‧‧閘極介電層
214‧‧‧閘極電極層
214b‧‧‧閘極底面
214m‧‧‧閘極中線
214s‧‧‧閘極電極層之上表面
216‧‧‧側壁間隔物
218‧‧‧層間介電層
220a‧‧‧第一接觸結構
220b‧‧‧第二接觸結構
220c‧‧‧第一底面
220d‧‧‧第二底面
222‧‧‧開口
222a‧‧‧第一開口
222b‧‧‧第二開口
222m‧‧‧第一中線
222n‧‧‧第二中線
224‧‧‧金屬層
D1‧‧‧第一距離
D2‧‧‧第二距離
H1‧‧‧第一高度
H2‧‧‧第二高度
第1圖顯示為依照本揭露實施例之半導體裝置之接觸結構之製造方法之流程圖。
第2圖顯示為依照本揭露實施例之包含接觸結構之半導體裝置之立體圖。
第3A-10A、3B-10B、3C-10C圖顯示為依照本揭露實施例之包含接觸結構之半導體裝置於各製程階段之剖面圖。
可理解的是,本揭露接下來將提供許多不同的實施例以實施本揭露的不同特徵。為簡化本揭露,將在以下敘述元件及設置的特定範例,然而這些僅為範例且並不意圖限定本揭露。例如,當敘述一第一元件形成於一第二元件上時,可包含第一元件與第二元件直接接觸之實施例,或也可包含該第一元件與第二元件之間更有其他額外元件,而使該第一元件與第二元件無直接接觸之實施例。為簡明起見,本揭露之各種特徵
可任意繪製成不同尺寸。此外,於本揭露各實施例中,可能會有重複的參考標號及/或符號。然而,這些重複的參考標號及/或符號僅是為了簡潔表示,不代表在各個實施例及/或圖式之間有何特定的關連。
第1圖顯示為依照本揭露實施例半導體裝置之接觸結構之製造方法100之流程圖。方法100起始於步驟102,其係為提供一基材。接著,進行方法100步驟104,形成基材之第一鰭狀物及第二鰭狀物於此基材之主要表面上,其中第一鰭狀物及第二鰭狀物自基材之主要表面延伸向上並包含鰭頂面。接著,進行方法100之步驟106,形成絕緣區於基材之主要表面上及第一鰭狀物及第二鰭狀物之間。其中此絕緣區包含一低於鰭頂面之絕緣頂面。接著,進行方法100之步驟108,形成一閘極電極層於第一鰭狀物及第二鰭狀物之通道部分上及延伸至一部分的絕緣區上,其中位於該部分的絕緣區上之部分的閘極電極層係包含閘極中線。
接著,進行方法100之步驟110,形成環繞閘極電極層之層間介電層於絕緣區上。接著,進行方法100之步驟112,形成第一開口及第二開口於絕緣區上之層間介電層中,其中閘極中線至第一開口之距離與閘極中線至第二開口之距離不同。接著,進行方法100之步驟114,形成金屬層於第一開口及第二開口中,以形成第一接觸結構及第二接觸結構。下述之討論係以可依第1圖之方法100製造之半導體裝置為例。
第2圖顯示為依照本揭露實施例之包含接觸結構之半導體裝置200之立體圖。第3A至10C圖顯示為依照本揭露
實施例之半導體裝置200於各製程階段之剖面圖。為了便於說明,每一標題具有字母“A”之圖式係顯示沿第2圖之線段a-a(閘極之長度方向)之實施例,且每一標題具有字母“B”之圖式係顯示沿第2圖之線段b-b(鰭狀物之長度方向)之實施例,且每一標題具有字母“C”之圖式係顯示依第2圖之線段c-c(位於該些鰭狀物之間)之實施例。如本揭露中,所述之半導體裝置200係指鰭式場效電晶體(FinFET)。鰭式場效電晶體係指任何以鰭狀物為主並具有複數閘極之電晶體。在本揭露之考慮範圍中,亦包含其他電晶體結構及類比結構。半導體裝置200可被包含於微處理器、記憶胞及/或其他積體電路(IC)中。
需注意的是,在某些實施例中,如僅進行第1圖所述之操作係不會製造出完整的半導體裝置200,完整的半導體裝置200可由CMOS技術製程製造。因此,可理解的是,可在第1圖之方法100之前、之後及/或進行期間加入額外的製程,且某些其他製程在此僅會簡略描述。並且,第2至10C圖係為簡化之圖式,以使本揭露之概念能更易被瞭解。例如,雖然圖式中僅有顯示半導體裝置200,可理解的是,IC可包含許多其他裝置,例如包含電阻器、電容器、電感器及熔絲等。
第2圖顯示為使用第1圖所示步驟所製造之半導體裝置200。半導體裝置200包含鰭式場效電晶體(以下亦稱為鰭式場效電晶體200)。舉例而言,鰭式場效電晶體200包含鰭式結構202(包含基材20之第一鰭狀物202a及基材20之第二鰭狀物202b)、位於第一鰭狀物202a及第二鰭狀物202b之間的絕緣區204、橫向置於第一鰭狀物202a及第二鰭狀物202b之上的閘
極電極層214、及位於應變材料208上並鄰接閘極電極層214之一側之接觸結構220。在某些實施例中,鰭式場效電晶體200可包含少於或多於兩個鰭,例如一個鰭或三個鰭。
參見第3A、3B、3C圖及第1圖之步驟102,提供一基材20。第3A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第3B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第3C圖顯示為鰭式場效電晶體沿200第2圖之線段c-c之剖面圖。
在至少一實施例中,基材20包含結晶矽基材(例如晶圓)。基材20可依設計需求(例如p型基材或n型基材)包含各種摻雜區。在某些實施例中,摻雜區可摻雜p型或n型摻質。例如,摻雜區可摻雜p型摻質(例如硼或二氟化硼)、n型摻質(例如磷或砷)及/或前述之組合。摻雜區可用於n型鰭式場效電晶體,或用於p型鰭式場效電晶體。
或者,基材20可由某些其他合適的元素半導體(例如鑽石或鍺)、合適的化合物半導體(例如鉮化鎵、碳化矽、鉮化銦或磷化銦)或合適的合金半導體(例如碳鍺化矽、磷砷化鎵或磷鎵化銦)製成。此外,基材20可包含磊晶層(epi-layer)、可為應變以增加效能及/或可包含絕緣體上覆矽(SOI)結構。
請繼續參見第3A、3B及3C圖,第3A、3B及3C圖所示之結構可由形成鰭式結構202(包含基材20之第一鰭狀物202a及基材20之第二鰭狀物202b)而產生(第1圖之步驟104),其中此鰭式結構202自基材20之主要表面20s延伸向上並包含鰭頂面202t。在某些實施例中,鰭式結構202可更包含一蓋層(未
繪示)設置於該些鰭狀物上,其可為一矽蓋層。
鰭式結構202可由任意合適製程形成,包含各種沉積、微影及/或蝕刻製程。在一實施例中,微影製程可包含形成一感光層覆於基材20上(例如覆於矽層上)、曝光此感光層以形成圖案、進行曝光後烘烤製程、及將此感光層顯影,以形成包含該感光層之罩幕元件。接著,使用反應性離子蝕刻(RIE)及/或其他合適製程蝕刻此矽層,以形成溝槽206a及基材20之主要表面20s。基材20之每一位於這些溝槽206a之間的部分係形成一半導體鰭狀物。在所述實施例中,包含鰭頂面202t之鰭式結構202(包含基材20之第一鰭狀物202a及基材20之第二鰭狀物202b)自基材20之主要表面20s延伸向上。接著,移除感光層。接下來,可進行清潔製程,以移除半導體基材20之原生氧化物(native oxide)。可使用稀氫氟酸進行此清潔製程。
接著,可視需要於溝槽206a中形成內襯氧化物(未繪示)。在一實施例中,內襯氧化物可為厚度為約20Å至約500Å之熱氧化物。在某些實施例中,可使用原位水氣生成(in-situ steam generation,ISSG)及其類似方法形成此內襯氧化物。形成內襯氧化物可圓化溝槽206a之角落,其可降低電場並因此改善最終形成之積體電路之效能。
第4A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第4B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第4C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。第4A、4B及4C圖所示之結構可由形成一絕緣區204於基材
20主要表面20s上及第一鰭狀物202a及第二鰭狀物202b之間產生,其中此絕緣區204包含一低於鰭頂面202t之絕緣頂面204s(第1圖之步驟106)。
在所述實施例中,溝槽22填有介電材料,以形成絕緣區204,以定義及電性絕緣該鰭式結構202之各鰭狀物。在一實施例中,絕緣區204包含淺溝槽隔離區(STI)。絕緣區204包含氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(FSG)、低介電常數介電材料及/或前述之組合。前述之組合。絕緣區204及在本實施例所述之淺溝槽隔離區204可由任意合適製程形成。在一實施例中,淺溝槽隔離區204之形成可包含在各鰭狀物之間的溝槽填充介電材料(例如,使用化學氣相沉積製程)。在某些實施例中,經填充之溝槽可具有多層結構,例如具有熱氧化襯層,並填充氮化矽或氧化矽。
接著,進行化學機械研磨(CMP),直至暴露出或到達鰭式結構202之上表面,並接著以蝕刻步驟凹蝕介電材料,使凹陷206b暴露鰭式結構202之上部部分202u,以形成絕緣區204。鰭式結構202之每一上部部分202u包含兩源極/汲極(S/D)部分202s、202d及一通道區202c於兩源極/汲極(S/D)部分202s、202d之間。如此,絕緣區204係位於基材之主要表面20s上及位於該第一鰭狀物202a及第二鰭狀物202b之間,且絕緣區204包含一低於鰭頂面202t之絕緣頂面204s。在一實施例中,可使用濕蝕刻製程進行蝕刻步驟。例如,可將基材20浸至氫氟酸中(HF)。在另一實施例中,可使用乾蝕刻製程進行蝕刻步驟,例如可使用CHF3或BF3作為蝕刻氣體進行該乾蝕刻製程。
如第5A、5B及5C圖所示,在形成該絕緣區204之後,第5A、5B及5C圖所示之結構可由形成一閘極電極層214於第一鰭狀物202a及第二鰭狀物202b之通道部分202c上並延伸至一部分的該絕緣區204上而產生,其中位於該部分的絕緣區204上之一部分的該閘極電極層214包含一閘極中線214m(第1圖之步驟108)。第5A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第5B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第5C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。
在某些實施例中,閘極電極層214位於閘極介電層212上。閘極電極層214及閘極介電層212形成一閘極堆疊210。在某些實施例中,可在閘極堆疊210之兩側形成一對側壁間隔物216。在所述實施例中,可使用任意合適製程形成閘極堆疊210,包含在此所述之製程。
在一實施例中,閘極介電層212及閘極電極層214依續沉積於基材20上。在某些實施例中,閘極介電層212可包含氧化矽、氮化矽、氮氧化矽或高介電常數(high-k)介電質。高介電常數介電質包含金屬氧化物。例如,用於高介電常數介電質的金屬氧化物可包含Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu之氧化物或前述之混合物。在本實施例中,閘極介電層212為厚度為約10Å至約30Å之高介電常數介電層。閘極介電層212可由合適製程形成,例如原子層沉積(ALD)、化學氣
相沉積(CVD)、物理氣相沉積(PVD)、熱氧化法、UV-臭氧氧化法或前述之組合。閘極介電層212可更包含界面層(未繪示),以減少該閘極介電層212及鰭式結構202之間的損傷。界面層可包含氧化矽。
在某些實施例中,閘極電極層214可包含單層或多層結構。在至少一實施例中,該閘極電極層214包含多晶矽。此外,閘極電極層214可為具有均勻或不均勻摻雜之多晶矽。在其他實施例中,閘極電極層214包含N型功函數金屬,例如擇自W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn及Zr組成之族群之金屬。在另一實施例中,閘極電極層214包含P型功函數金屬,例如擇自TiN、WN、TaN及Ru組成之族群之金屬。在本實施例中,閘極電極層214之厚度為約30nm至約60nm。可使用合適製程形成閘極電極層214,例如原子層沉積、化學氣相沉積、物理氣相沉積或前述之組合。
接著,以合適製程形成光阻層(未顯示)於閘極電極層214上(例如使用旋轉塗佈),並以合適之微影圖案化方法將其圖案化,以形成圖案化光阻元件。在至少一實施例中,圖案化光阻元件之寬度為約5nm至約45nm。接著,可使用乾蝕刻製程將圖案化光阻元件之圖案轉移至底下膜層(即閘極電極層214及該閘極介電層212),以形成閘極堆疊210。隨後,可剝除此光阻層。
請繼續參見第5A、5B及5C圖,鰭式場效電晶體200更包含一介電層形成於閘極堆疊210及基材20上,並覆蓋閘極堆疊210之兩側壁上。此介電層可包含氧化矽、氮化矽、或氮
氧化矽。此介電層可包含單層或多層結構。此介電層可由化學氣相沉積、物理氣相沉積、原子層沉積或其他合適技術形成。此介電層之厚度為約5nm至約15nm。接著,對該介電層進行非等向性蝕刻,以形成一對側壁間隔物216於閘極堆疊210之兩側上。
第6A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第6B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第6C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。如第6A、6B及6C圖所示,在形成閘極電極層214之後,磊晶成長形成應變材料208於源/汲極部分202s、202d上並延伸至絕緣區204上,形成如第6A、6B及6C圖所示之可選擇之結構,其中應變材料208之晶格常數與基材20之晶格常數不同。因此,鰭式場效電晶體200之通道部分202c係為應變(strained)或被施予應力,以增加裝置之載子遷移率。
在某些實施例中,應變材料208包含Si、Ge、SiGe、SiC、SiP或III-V族半導體材料。在所述之實施例中,可以氫氟酸或其他合適溶液進行預清潔製程,以清潔源/汲極部分202s、202d。接著,以低壓化學氣相沉積(LPCVD)製程在源/汲極部分202s、202d上選擇性成長該應變材料208,例如鍺化矽。在所述實施例中,此低壓化學氣相沉積製程是在溫度約400至約800℃及壓力在約1至約15Torr下進行,並使用SiH2Cl2、HCl、GeH4、B2H6及H2作為反應氣體。
如第7A、7B、7C圖及第1圖之用以製造鰭式場效電
晶體200之接觸結構(例如第10圖所示之接觸結構220)之步驟110所述,第7A、7B及7C圖之結構是由形成層間介電層218圍繞絕緣區204上之閘極電極層214(及該對側壁間隔物216)並延伸至該兩源/汲極部分202s、202d所產生。第7A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第7B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第7C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。
層間介電層218包含介電材料。此介電材料可包含氧化矽、氮化矽、氮氧化矽、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、旋轉塗佈(SOG)、氟摻雜矽玻璃(FSG)、碳摻雜氧化矽(例如SiCOH)及/或前述之組合。在某些實施例中,層間介電層218可由化學氣相沉積、高密度電漿(HDP)化學氣相沉積、次大氣壓化學氣相沉積(SACVD)、旋轉塗佈、濺鍍或其他合適方法形成於該應變材料208上。在本實施例中,層間介電層218之厚度為約4000Å至約8000Å。可理解的是,層間介電層218可包含一或多種介電材料及/或一或多層介電層。
隨後,使用化學機械研磨製程平坦化此層間介電層218,直至暴露出或到達閘極電極層214之上表面214s(如第8A、8B及8C圖所示)。此化學機械研磨製程具有高選擇性,以提供閘極電極層214及層間介電層218實質上平坦之表面。第8A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第8B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第8C圖顯示為鰭
式場效電晶體200沿第2圖之線段c-c之剖面圖。
進行至此,製程步驟已提供一基材20,其具有層間介電層218於兩源/汲極部分202s、202d上。在某些應用中,兩對稱之源/汲極接觸結構係穿透層間介電層218並形成於閘極電極層214之兩側上,以提供鰭式場效電晶體200之源/汲極部分202s、202d電性接觸。然而,如閘極電極層214包覆鰭狀物202,並與這兩對稱之源/汲極接觸結構具有設計法則距離(design-rule distance),在源/汲極接觸結構及閘極電極層214之間的寄生電容(parasitic capacitance)會顯著增加,並因此會降低裝置效能。
因此,下述如第9A-10C圖所述之製程,可形成兩非對稱之源/汲極接觸結構於閘極電極層214之兩側上,以取代閘極電極層214之兩側上之兩對稱之源/汲極接觸結構。因此,如增加的寄生電容量為可接受的,閘極電極層214與兩非對稱之源/汲極接觸結構其中一者之距離可為設計法則距離,且如增加的寄生電容量為不能接受的,閘極電極層214與兩非對稱之源/汲極接觸結構之另一者之距離為大於設計法則距離。因此,可增加裝置效能。
隨後,對第8A、8B及8C圖所示之鰭式場效電晶體200進行CMOS製程,包含形成開口貫穿層間介電層218,以提供電性接觸至鰭式場效電晶體200之源/汲極部分202s、202d。參見第9A、9B及9C圖,如第9A、9B及9C圖所示之結構係由形成開口222(包含第一開口222a及第二開口222b)於絕緣區204上之層間介電層218上所產生,其中第一開口222a至閘極中線
214m之間的第一距離D1與該第二開口222b至閘極中線214m之間的第二距離D2不同(第1圖之步驟112)。第9A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第9B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第9C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。
在一實施例中,該開口222之形成包含:以合適製程形成一光阻層(未繪示)於層間介電層218上(例如旋轉塗佈)、接著以合適的微影方法圖案化該光阻層以形成圖案化光阻層、蝕刻暴露的層間介電層218(例如使用乾蝕刻、濕蝕刻及/或電漿蝕刻製程),以移除部分的該層間介電層218並暴露一部分位於該絕緣區204上之應變材料208。隨後,可剝除此圖案化光阻層。
第10A圖顯示為依照本揭露一實施例之鰭式場效電晶體200於一製程階段之沿第2圖所示之線段a-a之剖面圖,第10B圖顯示為鰭式場效電晶體200沿第2圖之線段b-b之剖面圖,及第10C圖顯示為鰭式場效電晶體200沿第2圖之線段c-c之剖面圖。請參照第10A、10B及10C圖及第1圖之步驟114,於層間介電層218中形成開口222之後,可於第一開口222a及第二開口222b中形成金屬層224,以形成第一接觸結構220a及第二接觸結構220b,形成如第10A、10B及10C圖所示之結構。此後,第一接觸結構220a及第二接觸結構220b係一併稱為接觸結構220。
在某些實施例中,金屬層224包含W、Al或Cu。在某些實施例中,金屬層224可由化學氣相沉積、物理氣相沉積、
電鍍、原子層沉積或其他合適技術形成。在某些實施例中,金屬層224可包含層疊結構。此該層疊結構可更包含一金屬阻障層、一內襯金屬層或一潤濕金屬層。此外,此金屬層224之厚度將依開口222之深度決定。金屬層224係沉積直至實質上填滿或超出該開口222,並由進行另一化學機械研磨製程移除一部分超出該開口222的金屬層224。該化學機械研磨製程可於到達層間介電層218時停止,並因此提供實質上平坦之表面。
在某些實施例中,半導體裝置200包含此絕緣區204於此基材20上;此包含閘極中線214m之此閘極電極層214於此絕緣區204上;此包含第一中線之此第一接觸結構220a於此絕緣區204上並鄰接此閘極電極層214,其中此第一中線222m與此閘極中線214m之間具有第一距離D1;以及此包含第二中線222n之第二接觸結構220b位於絕緣區204上並位於此閘極電極層214之相對於第一接觸結構220a之另一側上,其中此第二中線222n與此閘極中線214m之間具有大於該第一距離D1之第二距離D2。
在某些實施例中,鰭式場效電晶體200包含此基材20,其包含該主要表面20s;包含鰭頂面202t之此基材20之第一鰭狀物202a及此基材20之該第二鰭狀物202b自基材主要表面20s延伸向上;包含此絕緣頂面202t之此絕緣區204位於此主要表面20s上及此第一鰭狀物202a及此第二鰭狀物202b之間;此閘極電極層214位於此第一鰭狀物202a及此第二鰭狀物202b上並延伸至此絕緣區204上,其中位於此絕緣區204上之此閘極電極層214包含此閘極中線214m;包含此第一中線222m之此第一
接觸結構220a位於此絕緣區204上並鄰接此閘極電極層214,其中此第一中線222m與此閘極中線214m之間具有第一距離D1;以及包含此第二中線222n之此第二接觸結構220b位於此絕緣區204上及此閘極電極層214之相對於該第一接觸結構220a之另一側上,其中此第二中線222n與此閘極中線214m之間具有大於此第一距離D1之第二距離D2。
在某些實施例中,此第二距離D2與此第一距離D1之比例為約1.1至約5。在某些實施例中,此閘極電極層21包含一閘極底面214b,且此第一接觸結構220包含一高於此閘極底面214b之第一底面220c,其中此第一底面220c至此閘極底面214b之一第一高度H1為約1至約50nm。在某些實施例中,該閘極電極層214包含一閘極底面214b,且此第二接觸結構220b包含一高於此閘極底面214b之第二底面220d,其中此第二底面220d至此閘極底面214b的第二高度H2為約1nm至約50nm。在某些實施例中,一半導體層(亦即該應變材料208)位於此第一接觸結構220a及該絕緣區204之間。
在所述之實施例中,此閘極堆疊210可使用前閘極(gate first)製程製造。在其他實施例中,此閘極堆疊210可由後閘極(gate last)製程製造,其包含形成一虛置閘極堆疊。在某些實施例中,後閘極製程包含形成一層間介電層環繞虛置閘極堆疊、移除一虛置閘極電極層以形成溝槽於該層間介電層中、並接著以導電閘極電極層填充該溝槽。在某些實施例中,此後閘極製程包含形成一層間介電層環繞該虛置閘極堆疊,移除一虛置閘極電極層及一虛置閘極介電層以形成溝槽於層間介電
層中、並接著以導電閘極電極層填充該溝槽。
在進行如第1圖及第3A至10C圖所教示之步驟之後,可繼續進行後續製程,例如包含內連線製程,以完成鰭式場效電晶體200之製造。可觀察到的是,由於第二中線222n及閘極中線214m具有第二距離D2大於第一距離D1(亦即設計法則距離),可具有較低的寄生電容及可增進裝置效能。
雖然本揭露已以數個較佳實施例揭露如上,然其並非用以限定本揭露,任何所屬技術領域中具有通常知識者,在不脫離本揭露之精神和範圍內,當可作任意之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
Claims (10)
- 一種半導體裝置,包含:一鰭板形成於一基底上,該鰭板具有沿著一第一方向之一長軸;一絕緣區於該基材上;一閘極電極層於該絕緣區及該鰭板上;一第一閘極間隔物於該閘極電極層之一第一側上且位於該鰭板上;一第二閘極間隔物於該閘極電極層之相對於該第一側之一第二側上,且該第二閘極間隔物位於該鰭板上;一源極區於朝向該第一閘極間隔物的該鰭板中,且橫向地延伸遠離該閘極電極層;一汲極區於朝向該第二閘極間隔物的該鰭板中,且橫向地延伸遠離該閘極電極層;該源極區的一第一接觸結構,包括一第一導電插塞,該第一導電插塞延伸穿過形成於該鰭板及該絕緣區之上的一絕緣層,其中該第一導電插塞包含位於該絕緣區之正上方的一部分,其中該第一接觸結構的該第一導電插塞的該部分的一第一中線以及該閘極電極層的一閘極中線之間為一第一距離;以及該汲極區的一第二接觸結構,包括一第二導電插塞,該第二導電插塞延伸穿過形成於該鰭板及該絕緣區之上的該絕緣層,其中該第二導電插塞包含位於該閘極電極層之相對於該第一接觸結構之一側且位於該絕緣區之正上方的一部 分,其中該第二接觸結構的該第二導電插塞的該部分的一第二中線以及該閘極電極層的閘極中線之間為一第二距離,且該第二距離大於該第一距離。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二距離與該第一距離之比例為約1.1至約5。
- 如申請專利範圍第1項所述之半導體裝置,其中該閘極電極層包含一閘極底面,且該第一接觸結構包含一高於該閘極底面之第一底面。
- 如申請專利範圍第3項所述之半導體裝置,其中該第一底面至該閘極底面之一第一高度為約1nm至約50nm。
- 如申請專利範圍第1項所述之半導體裝置,其中該閘極電極層包含一閘極底面,且該第二接觸結構包含一高於該閘極底面之第二底面。
- 如申請專利範圍第1項所述之半導體裝置,更包含一半導體層位於該第一接觸結構及該絕緣區之間。
- 一種半導體裝置之製造方法,包含:提供一基材;形成該基材之一第一鰭狀物及該基材之一第二鰭狀物,其自該基材之一主要表面延伸向上,其中該第一鰭狀物及該第二鰭狀物包含鰭頂面;形成一絕緣區於該主要表面上及該第一鰭狀物及該第二鰭狀物之間,其中該絕緣區包含一絕緣表面低於該些鰭頂面;形成一閘極電極層,其位於該第一鰭狀物及該第二鰭狀物之通道區部分上並延伸至一部分的該絕緣區上,其中位於該 部分的該絕緣區上之一部分的該閘極電極層包含一閘極中線;形成一層間介電層環繞該絕緣區上之該閘極電極層;形成一第一開口及一第二開口於該絕緣區之該層間介電層上,其中該第一開口之一第一中線與該閘極中線之間之距離係與該第二開口之一第二中線與該閘極中線之間之距離不同;以及形成一金屬層於該第一開口及該第二開口中,以形成第一接觸結構及一第二接觸結構。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,更包含:在形成一閘極電極層之後,磊晶成長一應變材料於該些鰭狀物之源/汲極部分上並延伸至該絕緣區上,其中該應變材料之晶格常數與該基材之晶格常數不同。
- 一種半導體裝置之製造方法,包含:於一基材中形成一第一溝槽和一第二溝槽,該基板位於該第一溝槽和該第二溝槽之間的一部分形成一鰭狀物;於該第一溝槽中形成一絕緣區,該絕緣區的一頂面低於該鰭狀物的一頂面;於該鰭狀物的一通道部分上方形成一閘極電極層,該閘極電極層延伸至該絕緣區上方;分別於該閘極電極層的一第一側和一第二側上形成一第一閘極間隔物和一第二閘極間隔物,該第一閘極間隔物延伸至該鰭狀物上方,該第二閘極間隔物延伸至該鰭狀物上 方,該閘極電極層的該第一側為該閘極電極層的該第二側的相反側;於該第一閘極間隔物所在位置之該鰭狀物中形成一汲極區,該汲極區橫向地遠離該閘極電極層,且於該第二閘極間隔物所在位置之該鰭狀物中形成一源極區,該源極區橫向地遠離該閘極電極層;形成一層間介電層環繞該閘極電極層,且該層間介電層形成於該絕緣區上方;於位於該絕緣區上方和位於該鰭狀物中的該汲極區上方的該層間介電層中形成一第一開口,且於位於該絕緣區上方和位於該鰭狀物中的該源極區上方的該層間介電層中形成一第二開口,其中該第一開口之一第一中線與該閘極電極層的一閘極中線之間之一第一距離大於該第二開口之一第二中線與該閘極電極層該閘極中線之間之一第二距離;以及於該第一開口及該第二開口中形成一金屬層,以形成一第一接觸結構及一第二接觸結構。
- 如申請專利範圍第9項所述之半導體裝置之製造方法,更包含:在形成一閘極電極層之後,於該汲極區上方磊晶成長一第一應變材料,且於該源極區上方磊晶成長一第二應變材料,該第一應變材料和該第二應變材料各別延伸至該絕緣區上方,其中該第一應變材料之晶格常數和該第二應變材料之晶格常數與該基材之晶格常數不同。
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