TW201730939A - 鰭式場效應電晶體的製造方法 - Google Patents

鰭式場效應電晶體的製造方法 Download PDF

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TW201730939A
TW201730939A TW105142020A TW105142020A TW201730939A TW 201730939 A TW201730939 A TW 201730939A TW 105142020 A TW105142020 A TW 105142020A TW 105142020 A TW105142020 A TW 105142020A TW 201730939 A TW201730939 A TW 201730939A
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semiconductor
semiconductor fin
dummy gate
finfet
stack structure
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TWI740869B (zh
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蕭茹雄
鄭志成
吳啟明
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台灣積體電路製造股份有限公司
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Abstract

一種鰭式場效應電晶體（FinFET）包括半導體基底、多個絕緣體、閘極堆疊結構以及應變材料。半導體基底包括位於其上的至少一個半導體鰭。半導體鰭包括源極/汲極區以及通道區，且源極/汲極區的寬度大於通道區的寬度。絕緣體設置於半導體基底上並且半導體鰭夾置於絕緣體之間。閘極堆疊結構位於半導體鰭的通道區上方和部分絕緣體上方。應變材料覆蓋半導體鰭的源極/汲極區。此外，提供了鰭式場效應電晶體的製造方法。

Description

鰭式場效應電晶體的製造方法
本發明實施例是有關於鰭式場效應電晶體及其製造方法，且特別是有關於一種源極/汲極區以及通道區具有不同寬度的鰭式場效應電晶體及其製造方法。
隨著半導體裝置在尺寸上不斷減小，目前已經開發出諸如鰭式場效應電晶體（FinFET）的三維多閘極結構，以替代平面的互補金屬氧化物半導體（CMOS）裝置。FinFET的結構特徵是具有從半導體基底的表面垂直向上延伸且以矽為基礎的鰭，以及包裹在由鰭所形成的導電通道周圍的閘極，以進一步提供了對通道有更好的電控制。源極/汲極（S/D）和通道的輪廓對於裝置的性能是至關重要的。
根據本發明的一些實施例，一種鰭式場效應電晶體（FinFET）的製造方法至少包括以下步驟。圖案化半導體基底以在半導體基底中形成多個溝槽並且在溝槽之間形成至少一個半導體鰭。在溝槽中形成多個絕緣體。在部分半導體鰭上方和部分絕緣體上方形成虛擬閘極堆疊結構。在被虛擬閘極堆疊結構暴露出的部分半導體鰭上方形成應變材料。移除部分虛擬閘極堆疊結構以形成暴露出部分半導體鰭的凹部。移除位於凹部中的部分半導體鰭。在凹部中形成閘極介電材料並填入閘極材料以形成閘極堆疊結構。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
本發明的實施例描述了示範例性的FinFET的製造過程以及由該製程所製造出的FinFET。在本發明的某些實施例中，FinFET可以形成在矽基底上。此外，可以選擇性地在絕緣體上矽（SOI）基底、絕緣體上鍺（GOI）基底、SiGe基底或III-V族半導體基底上形成FinFET。並且，根據一些實施例，矽基底可包括其他導電層或諸如電晶體、二極體等的其他半導體元件。在本文中，實施例不被限制。
請參照圖1，其繪示了根據本發明的一些實施例的FinFET的製造方法的流程圖。該方法至少包括步驟S10、步驟S12、步驟S14、步驟S16、步驟S18、步驟S20、步驟S22和步驟S24。首先，在步驟S10中，圖案化半導體基底以在半導體基底中形成多個溝槽並且在溝槽之間形成至少一個半導體鰭。然後，在步驟S12中，在半導體基底上形成絕緣體，且此絕緣體位於溝槽中。舉例來說，絕緣體是用以絕緣或隔離半導體鰭的淺溝槽隔離（STI）結構。其後，在步驟S14中，在部分半導體鰭上方和絕緣體上方形成虛擬閘極堆疊結構。隨後，在步驟S16中，形成應變材料（或高摻雜的低電阻材料）以覆蓋被虛擬閘極堆疊結構暴露出的半導體鰭。然後，在步驟S18中，在應變材料以及絕緣體上方形成層間介電層。然後，在步驟S20中，移除部分虛擬閘極堆疊結構以形成暴露出部分半導體鰭的凹部。此後，在步驟22中，移除位於凹部中的部分半導體鰭。隨後，如步驟S24所示，在凹部中填入閘極介電材料以及閘極材料以得到閘極堆疊結構。如圖1所示，應變材料是在虛擬閘極堆疊結構形成之後才形成。然而，在本發明實施例中並不限制虛擬閘極堆疊結構（步驟S14）以及應變材料（步驟S16）的形成順序。
圖2A是FinFET的製造方法中的多個階段之一的立體圖，且圖3A是沿著圖2A的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S10中，並且如圖2A和圖3A所示，提供半導體基底200。在一個實施例中，半導體基底200包括晶體矽基底（例如晶圓）。半導體基底200可以包括取決於設計需求的（例如，p型半導體基底或n型半導體基底）的多種摻雜區。在一些實施例中，摻雜區可以摻雜有p型或n型摻質。例如，摻雜區可以摻雜有諸如硼或BF2 的p型摻質；諸如磷或砷的n型摻雜劑；和/或它們的組合。摻雜區可以配置為用於n型FinFET，或可選地配置為用於p型FinFET。在一些可選擇的實施例中，半導體基底200可以由以下材料製成：合適的元素半導體，諸如金剛石或鍺；合適的化合物半導體，諸如砷化鎵、碳化矽、砷化銦或磷化銦；或合適的合金半導體材料，諸如碳化矽鍺、磷砷化鎵或磷銦化鎵。
在一個實施例中，依序在半導體基底200上形成襯層202a和罩幕層202b。襯層202a可以是透過例如熱氧化製程而形成的氧化矽薄膜。襯層202a可以充當半導體基底200和罩幕層202b之間的黏合層。襯層202a也可以充當蝕刻罩幕層202b的蝕刻停止層。在至少一個實施例中，罩幕層202b是透過例如低壓化學氣相沉積（LPCVD）或等離子體增強化學氣相沉積（PECVD）而形成的氮化矽層。在後續的微影製程期間，罩幕層202b可作為硬罩幕（hard mask）。在罩幕層202b上形成具有預定圖案的圖案化的光阻層204。
圖2B是FinFET的製造方法中的多個階段之一的立體圖，且圖3B是沿著圖2B的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S10中，並且如圖2A至2B和圖3A至3B所示，依序蝕刻未被圖案化的光阻層204覆蓋的罩幕層202b和襯層202a，以形成圖案化的罩幕層202b’和圖案化的襯層202a’，並暴露出下面的半導體基底200。透過使用圖案化的罩幕層202b’、圖案化的襯層202a’以及圖案化的光阻層204作為罩幕，半導體基底200的部分會被暴露並被蝕刻掉以形成溝槽206和半導體鰭208。圖案化的罩幕層202b’、圖案化的襯層202a’以及圖案化的光阻層204覆蓋半導體鰭208。兩個相鄰的溝槽206被間距間隔開。例如，溝槽206之間的間距可以小於約30 nm。換言之，兩個相鄰的溝槽206被相應的半導體鰭208間隔開。
半導體鰭208的高度和溝槽206的深度在約5 nm至約500 nm的範圍內。在形成溝槽206和半導體鰭208之後，移除圖案化的光阻層204。在一個實施例中，可以實施清潔製程以移除半導體基底200a和半導體鰭208的原生氧化物（native oxide）。可以使用稀釋的氫氟（DHF）酸或其他合適的清潔溶液來進行清潔製程。
圖2C是FinFET的製造方法中的多個階段之一的立體圖，且圖3C是沿著圖2C的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S12中，並且如圖2B至2C和圖3B至3C所示，在半導體基底200a上方形成絕緣材料210以覆蓋半導體鰭208並且填充溝槽206。除了半導體鰭208之外，絕緣材料210進一步覆蓋圖案化的襯層202a’和圖案化的罩幕層202b’。絕緣材料210可以包括氧化矽、氮化矽、氮氧化矽、旋塗介電材料或低k介電材料。值得注意的是，低k介電材料通常是具有低於3.9的介電常數的介電材料。可透過高密度等離子體化學氣相沉積（HDP-CVD）、次大氣壓CVD（SACVD）或旋塗形成絕緣材料210。
圖2D是FinFET的製造方法中的多個階段之一的立體圖，且圖3D是沿著圖2D的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S12中，並且如圖2C至2D和圖3C至3D所示，進行例如化學機械研磨（CMP）製程或是濕蝕刻製程以移除部分絕緣材料210、圖案化的罩幕層202b’以及圖案化的襯層202a’，直到暴露出半導體鰭208。如圖2D和圖3D所示，在研磨絕緣材料210之後，被研磨的絕緣材料210的頂面與半導體鰭208的頂面T2實質上共面。
圖2E是FinFET的製造方法中的多個階段之一的立體圖，且圖3E是沿著圖2E的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S12中，並且如圖2D至2E和圖3D至3E所示，透過蝕刻製程部分地移除填充在溝槽206中的研磨的絕緣材料210，以使得所形成的絕緣體210a形成在半導體基底200a上方並且每個絕緣體210a均位於兩個相鄰的半導體鰭208之間。在一個實施例中，蝕刻製程可以是利用氫氟酸（HF）的濕蝕刻製程或乾蝕刻製程。絕緣體210a的頂面T1低於半導體鰭208的頂面T2。半導體鰭208從絕緣體210a的頂面T1突出。半導體鰭208的頂面T2與絕緣體210a的頂面T1之間的高度差在約15 nm至約50 nm的範圍之間。
圖2F是FinFET的製造方法中的多個階段之一的立體圖，且圖3F是沿著圖2F的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S14中，並且如圖2E至2F和圖2F至3F所示，在部分半導體鰭208和部分絕緣體210a上方形成虛擬閘極堆疊結構212。在一個實施例中，例如，虛擬閘極堆疊結構212的延伸方向D1垂直於半導體鰭208的延伸方向D2以覆蓋半導體鰭208的中間部M（如圖3F所示）。虛擬閘極堆疊結構212包括虛擬閘極介電層212a和設置在虛擬閘極介電層212a上方的虛擬閘極212b。虛擬閘極212b設置在部分半導體鰭208上方和部分絕緣體210a上方。根據一些實施例，在半導體鰭208（如圖2E所示）形成之後，形成虛擬閘極介電層212a以分離半導體鰭208和虛擬閘極212b並且作為蝕刻停止層。
所形成的虛擬閘極介電層212a覆蓋半導體鰭208的中間部M。在一些實施例中，虛擬閘極介電層212a可以包括氧化矽、氮化矽或氮氧化矽。可使用諸如原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、熱氧化、UV-臭氧氧化或它們的組合等合適的製程形成虛擬閘極介電層212a。
接著，在虛擬閘極介電層212a上形成虛擬閘極212b。在一些實施例中，虛擬閘極212b可以包括單層或多層結構。在一些實施例中，虛擬閘極212b包括諸如多晶矽、非晶矽或它們的組合的含矽材料，且是在應變材料214形成之前形成。在一些實施例中，虛擬閘極212b包括在約30 nm至約90 nm的範圍內的厚度。可以使用諸如ALD、CVD、PVD、鍍覆或它們的組合等合適的製程形成虛擬閘極212b。
此外，虛擬閘極堆疊結構212可以進一步包括設置在虛擬閘極介電層212a以及虛擬閘極212b的側壁上的一對間隙壁212c。這一對間隙壁212c可進一步覆蓋部分半導體鰭208。間隙壁212c可以由諸如氧化矽、氮化矽、碳氮化矽（SiCN）、SiCON或它們的組合等介電材料形成。間隙壁212c可以包括單層或多層結構。在下文中，將未被閘極堆疊結構212覆蓋的部分半導體鰭208稱為暴露的部分E。
圖2G是FinFET的製造方法中的多個階段之一的立體圖，且圖3G是沿著圖2G的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S16中，並且如圖2F至2G和圖3F至3G所示，移除半導體鰭208的暴露的部分E並且使其凹陷而形成凹陷部R。例如，透過非等向性蝕刻（anisotropic etching）、等向性蝕刻（isotropic etching）或它們的組合移除暴露的部分E。在一些實施例中，半導體鰭208的暴露的部分E凹進至絕緣體210a的頂面T1下方。凹陷部R的深度小於絕緣體210a的厚度。換言之，半導體鰭208的暴露的部分E並未被完全移除，且位於凹陷部R中的剩餘的半導體鰭208構成源極/汲極區220。如圖2G以及3G所示，當使半導體鰭208的暴露的部分E凹陷時，被虛擬閘極堆疊結構212覆蓋的部分半導體鰭208並未被移除。被虛擬閘極堆疊結構212覆蓋的部分半導體鰭208在虛擬閘極堆疊結構212的側壁處暴露出。
圖2H是FinFET的製造方法中的多個階段之一的立體圖，且圖3H是沿著圖2H的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S16中，並且如圖2G至2H和圖2G至3H所示，在半導體鰭208的凹陷部R上方生長應變材料214（或高摻雜的低電阻材料），且應變材料214延伸超過絕緣體210a的頂面T1以使半導體鰭208受到應變或應力。換言之，在半導體鰭208的源極/汲極區220上方形成應變材料214。因此，應變材料214包括設置在虛擬閘極堆疊結構212的一側處的源極和設置在虛擬閘極堆疊結構212的另一側處的汲極。源極覆蓋半導體鰭208的一端並且汲極覆蓋半導體鰭208的另一端。
應變材料214可摻雜有導電摻質。在一個實施例中，諸如SiGe等應變材料214磊晶生長（epitaxial growth）有p型摻質以使p型FinFET應變。也就是說，應變材料214摻雜有p型摻質以成為p型FinFET的源極和汲極。p型摻雜劑包括硼或BF2 ，並且應變材料214可以透過利用原位摻雜的LPCVD製程磊晶生長。在另外的實施例中，諸如SiC、SiP、SiC/SiP的組合或SiCP等應變材料214磊晶生長n型摻質以使n型FinFET應變。也就是說，應變材料214摻雜有n型摻質以成為n型FinFET的源極和汲極。n型摻雜劑包括砷和/或磷，並且應變材料214可以透過利用原位摻雜的LPCVD製程磊晶生長。應變材料214可以是單層或多層。
圖2I是FinFET的製造方法中的多個階段之一的立體圖，且圖3I是沿著圖2I的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S18中，並且如圖2I和圖3I所示，在應變材料214以及絕緣體210a上方形成層間介電層300。換言之，形成層間介電層300而與間隙壁212c相鄰。層間介電層300包括氧化矽、氮化矽、氮氧化矽、磷矽酸鹽玻璃（PSG）、硼磷矽酸鹽玻璃（BPSG）、旋塗玻璃（SOG），氟化矽玻璃（FSG），碳摻雜的氧化矽（例如，SiCOH），聚醯亞胺、和/或它們的組合。在一些其他的實施例中，層間介電層300包括低k介電材料。低k介電材料例如是包括Black Diamond®（加利福尼亞州聖克拉拉的應用材料公司）、乾凝膠（Xerogel）、氣凝膠（Aerogel）、非晶質氟化碳（amorphous fluorinated carbon）、聚對二甲苯（Parylene）、BCB（雙-苯並環丁烯）、Flare、SILK®（密西根州米蘭的陶氏化學公司）、氫倍半矽氧烷（HSQ）或氟化矽氧化物（SiOF）、和/或它們的組合。應當理解的是，層間介電層300可以包括一種或多種介電材料和/或一層或多層介電層。在一些實施例中，可以透過可流動CVD（FCVD）、CVD、HDPCVD、SACVD、旋塗、濺鍍（sputtering）或其它合適的方法形成具有合適厚度的層間介電層300。具體來說，首先形成層間介電材料層（未繪示）以覆蓋絕緣體210a以及虛擬閘極堆疊結構212。隨後，減薄層間介電材料層的厚度直到暴露出虛擬閘極堆疊結構212的頂面為止，以形成層間介電層300。可透過化學機械研磨（CMP）製程、蝕刻製程或其它合適的製程以實現減薄層間介電材料層的厚度的製程。
圖2J是FinFET的製造方法中的多個階段之一的立體圖，且圖3J是沿著圖2J的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S20中，並且如圖2J和圖3J所示，移除部分虛擬閘極堆疊結構212以形成暴露出部分半導體鰭208的凹部H。詳細來說，移除虛擬閘極212b和虛擬閘極介電層212a以使得凹部H暴露出半導體鰭208的部分中間部M。值得注意的是，被凹部H暴露出的半導體鰭208可以充當通道區230。
在一些實施例中，透過蝕刻製程或其它合適的製程移除虛擬閘極212b以及虛擬閘極介電層212a。舉例來說，可通過濕蝕刻或乾蝕刻移除虛擬閘極212b以及虛擬閘極介電層212a。濕蝕刻的實例包括化學蝕刻且乾蝕刻的實例包括電漿蝕刻，但本發明實施例不限於此。其他習知的蝕刻方法也可以適用於虛擬閘極212b以及虛擬閘極介電層212a的移除。值得注意的是，在此階段，半導體鰭208具有實質上均勻的寬度w1。換言之，位於凹部H中的半導體鰭208的寬度和被間隙壁212c、層間介電層300以及應變材料214覆蓋的半導體鰭208的寬度實質上相同。如圖2J所示，半導體鰭208的源極/汲極區220的寬度也是w1。
圖2K以及圖2L是FinFET的製造方法中的多個階段之一的立體圖，且圖3K以及圖3L分別是沿著圖2K以及圖2L的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S22中，並且如圖2K-2L和圖3K-3L所示，移除位於凹部H中的半導體鰭208的部分通道區230。詳細來說，如圖2K和3K所示，對被凹部H暴露出的半導體鰭208的通道區230進行氧化處理以形成犧牲氧化物層402。可透過例如將含氧氣體通入到半導體鰭208以氧化被凹部H暴露的半導體鰭208的表面來實現氧化處理。在一些實施例中，含氧氣體可包括臭氧（O3 ）、過氧化氫（H2 O2 ）或其它包含氧原子的合適氣體。具體來說，在含氧氣體到達半導體鰭208的通道區230的表面之後，氣體中的氧原子將與半導體鰭208中的元素反應而形成氧化物。舉例來說，若半導體鰭208的材料是矽，生成的犧牲氧化物層402可以包括二氧化矽。值得注意的是，由於氧化處理是乾處理，移除虛擬閘極介電層212a的步驟以及半導體鰭208的氧化處理可以透過原位（in-situ）製程完成。換言之，若移除虛擬閘極介電層212a的步驟是透過乾蝕刻來達成，那麼移除製程和氧化處理製程是原位製程且可以在單個腔室中進行。
如圖2L和圖3L所示，在氧化半導體鰭208的表面以形成犧牲氧化物層402之後，移除犧牲氧化物層402以得到較薄的通道區230。在一些實施例中，可以使用稀釋的氫氟（DHF）酸或其他合適的溶液進行犧牲氧化物層402的移除。值得注意的是，由於被凹部H暴露出的部分半導體鰭208轉換成犧牲氧化物層402並且在後續被移除，因此通道區230的寬度w2小於半導體鰭208的源極/汲極區220的寬度w1。
圖2M是FinFET的製造方法中的多個階段之一的立體圖，且圖3M是沿著圖2M的剖線I-I’所截取的FinFET的剖面圖。在圖1中的步驟S22中，並且如圖2M和圖3M所示，在凹部H中填入閘極介電材料以及閘極材料以形成閘極堆疊結構216。具體來說，閘極堆疊結構216包括閘極介電層216a、閘極216b以及間隙壁212c。在半導體鰭208的通道區230上方設置閘極介電層216a，在閘極介電層216a上方設置閘極216b，且在閘極介電層216a以及閘極216b的側壁上設置間隙壁212c。閘極介電層216a的材料可以與虛擬閘極介電層212a的材料相同或不同。舉例來說，閘極介電層216a包括氧化矽、氮化矽、氮氧化矽、高k介電材料或它們的組合。高k介電材料包括諸如Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、和/或它們的組合的氧化物的金屬氧化物。在一些實施中，閘極介電層216a具有在約10埃至30埃的範圍內的厚度。可使用諸如原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、可流動化學氣相沉積（PCVD）、熱氧化、UV-臭氧氧化或它們的組合等合適的製程形成閘極介電層216a。閘極介電層216a可以進一步包括介面層（未繪示）。舉例來說，可以使用介面層以在半導體鰭208以及閘極216b之間創建良好的介面，且同時抑制半導體裝置的通道載流子（channel carrier）的遷移率的退化。此外，通過熱氧化製程、化學氣相沉積（CVD）製程或原子層沉積（ALD）製程形成介面層。介面層的材料包括諸如氧化矽層或氮氧化矽層的介電材料。
閘極216b的材料包括金屬、金屬合金或金屬氮化物。舉例來說，在一些實施例中，閘極216b可以包括TiN、WN、TaN、Ru、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。此外，閘極216b可以進一步包括阻障層（barrier layer）、功函數層（work function layer）或它們的組合。如上所述，介面層可以被包括在閘極216b以及半導體鰭208之間，但本發明實施例不限於此。在一些替代性實施例中，襯墊層（liner layer）、晶種層、黏著層或它們的組合也可以被包括在閘極216b和半導體鰭208之間。在圖1中的步驟S22中所示出的製程通常被稱為金屬替代製程（metal replacement process）。具體來說，在一些實施例中，包括多晶矽的虛擬閘極堆疊結構212被包括金屬的閘極堆疊結構216取代。由於虛擬閘極堆疊結構212被閘極堆疊結構216所取代，故可以實現形成金屬互連結構（未繪示）的後續製程。舉例來說，可形成其他導電線路（未繪示）以電性連接閘極216b與半導體裝置中的其它元件。
圖4是根據一些實施例的FinFET中的半導體鰭以及閘極的俯視圖。值得注意的是，為了清楚地示出閘極216b以及半導體鰭208之間的關係，在圖4中僅繪示出這兩個元件而省略了FinFET中的其他元件。如上所述，由於被凹部H（如圖2J至2K所示）暴露的半導體鰭208的通道區230會受到氧化處理，故半導體鰭208的源極/汲極區220的寬度w1大於半導體鰭208的通道230的寬度w2。換言之，如圖4所示，FinFET中的每個半導體鰭208呈現出狗骨頭形狀（dog-bone shape）。在一些實施例中，源極/汲極區220的較大的寬度w1允許應變材料214的較大的尺寸，因此能夠增強裝置的性能。類似地，通道區230的較小的寬度w2有利於更好的閘極控制，故也有助於裝置的性能。此外，由於閘極216b是填充到凹部H（如圖2L至圖3M所示），閘極216b與半導體鰭208的通道區230會對齊。換言之，閘極216b與半導體鰭208的通道區230是自對準（self-aligned）的，因此能夠使得FinFET的製程更加方便。
圖5是根據一些可選實施例的FinFET的立體圖。在實施例中，FinFET的製造步驟包括進行與圖2A至2F、圖2I至2M和圖3A至3F、圖3I至3M中所示的步驟相同或相似的製程步驟。換言之，在一些實施例中，省略了形成凹陷部R的步驟。在此情況下，FinFET中的半導體鰭208也呈現出狗骨形狀，故能夠增強裝置的性能且實現閘極216b的自對準。
根據本發明的一些實施例，一種鰭式場效應電晶體（FinFET）的製造方法至少包括以下步驟。圖案化半導體基底以在所述半導體基底中形成多個溝槽並且在所述溝槽之間形成至少一個半導體鰭。在所述溝槽中形成多個絕緣體。在部分所述半導體鰭上方和部分所述絕緣體上方形成虛擬閘極堆疊結構。在被所述虛擬閘極堆疊結構暴露出的部分所述半導體鰭上方形成應變材料。移除部分所述虛擬閘極堆疊結構以形成暴露出部分所述半導體鰭的凹部。移除位於所述凹部中的部分所述半導體鰭。在所述凹部中形成閘極介電材料並填入閘極材料以形成閘極堆疊結構。
根據本發明的一些實施例，所述虛擬閘極堆疊結構包括虛擬閘極、虛擬閘極介電層以及多個間隙壁，且移除部分所述虛擬閘極堆疊結構的步驟以及移除位於所述凹部中的部分所述半導體鰭的步驟至少包括以下步驟。首先，移除所述虛擬閘極。接著，移除所述虛擬閘極介電層以暴露出所述半導體鰭。然後，對被暴露出的所述半導體鰭進行氧化處理以形成犧牲氧化物層。移除所述犧牲氧化物層。
根據本發明的一些實施例，移除所述虛擬閘極介電層的步驟包括進行濕蝕刻製程且進行所述氧化處理的步驟包括通入含氧氣體以氧化所述半導體鰭的表面。
根據本發明的一些實施例，移除所述虛擬閘極介電層的步驟包括進行乾蝕刻製程且進行所述氧化處理的步驟包括通入含氧氣體以氧化所述半導體鰭的表面。
根據本發明的一些實施例，移除所述虛擬閘極介電層的步驟以及進行所述氧化處理的步驟是原位（in-situ）製程。
根據本發明的一些實施例，鰭式場效應電晶體的製造方法更包括以下步驟。移除被所述虛擬閘極堆疊結構暴露出的所述半導體鰭以形成所述半導體鰭的凹陷部，並將所述應變材料填充到所述凹陷部中以覆蓋被所述虛擬閘極堆疊結構暴露出的所述半導體鰭。
根據本發明的一些實施例，鰭式場效應電晶體的製造方法更包括以下步驟。在所述應變材料以及所述絕緣體上方形成層間介電層，其中所述層間介電層暴露出所述虛擬閘極堆疊結構。
根據本發明的一些替代性實施例，一種鰭式場效應電晶體（FinFET）的製造方法至少包括以下步驟。圖案化半導體基底以在所述半導體基底中形成多個溝槽並且在所述溝槽之間形成至少一個半導體鰭。在所述溝槽中形成後多個絕緣體。在部分所述半導體鰭上方和部分所述絕緣體上方形成虛擬閘極堆疊結構以暴露出所述半導體鰭的源極/汲極區，且所述虛擬閘極堆疊結構包括虛擬閘極、虛擬閘極介電層以及多個間隙壁。在所述半導體鰭的源極/汲極區上方形成應變材料。移除所述虛擬閘極介電層以及所述虛擬閘極以暴露出所述半導體鰭的通道區。移除所述半導體鰭的部分所述通道區。在所述半導體鰭的所述通道區上方形成閘極介電材料以及閘極材料以形成閘極堆疊結構。
根據本發明的一些替代性實施例，移除所述半導體鰭的部分所述通道區的步驟至少包括以下步驟。對所述半導體鰭的所述通道區進行氧化處理以形成犧牲氧化物層。移除所述犧牲氧化物層。
根據本發明的一些替代性實施例，移除所述虛擬閘極介電層的步驟包括進行濕蝕刻製程且進行所述氧化處理的步驟包括通入含氧氣體以氧化所述半導體鰭的表面。
根據本發明的一些替代性實施例，移除所述虛擬閘極介電層的步驟包括進行乾蝕刻製程且進行所述氧化處理的步驟包括通入含氧氣體以氧化所述半導體鰭的表面。
根據本發明的一些替代性實施例，移除所述虛擬閘極介電層的步驟以及進行所述氧化處理的步驟是原位（in-situ）製程。
根據本發明的一些替代性實施例，鰭式場效應電晶體的製造方法更包括以下步驟。移除部分所述半導體鰭以形成所述半導體鰭的凹陷部，並將所述應變材料填充到所述凹陷部中以覆蓋所述半導體鰭的所述源極/汲極區。
根據本發明的一些替代性實施例，所述半導體鰭的所述源極/汲極區的寬度大於所述半導體鰭的所述通道區的寬度。
根據本發明的一些實施例，鰭式場效應電晶體的製造方法更包括以下步驟。在所述應變材料以及所述絕緣體上方形成層間介電層，其中所述層間介電層暴露出所述虛擬閘極堆疊結構。
根據本發明的另一些替代性實施例，一種鰭式場效應電晶體（FinFET）包括半導體基底、多個絕緣體、閘極堆疊結構以及應變材料。所述半導體基底包括位於其上的至少一個半導體鰭。所述半導體鰭包括源極/汲極區以及通道區，且所述源極/汲極區的寬度大於所述通道區的寬度。所述絕緣體設置於所述半導體基底上且所述半導體鰭夾置於所述絕緣體之間。所述閘極堆疊結構位於所述半導體鰭的所述通道區上方和部分所述絕緣體上方。所述應變材料覆蓋所述半導體鰭的所述源極/汲極區。
根據本發明的另一些替代性實施例，所述閘極堆疊結構包括閘極介電層、閘極以及多個間隙壁。閘極介電層設置於所述半導體鰭的所述通道區上方。閘極設置於所述閘極介電層上方。間隙壁設置於所述閘極介電層以及所述閘極的側壁上。
根據本發明的另一些替代性實施例，所述閘極的材料包括金屬、金屬合金或金屬氮化物。
根據本發明的另一些替代性實施例，所述半導體鰭更包括凹陷部，且所述應變材料填充到所述凹陷部中以覆蓋所述半導體鰭的所述源極/汲極區。
根據本發明的另一些替代性實施例，所述閘極與所述半導體鰭的所述通道區對齊。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
S10、S12、S14、S16、S18、S20、S22、S24‧‧‧步驟 200、200a‧‧‧半導體基底 202a‧‧‧襯層 202a’‧‧‧圖案化的襯層 202b‧‧‧罩幕層 202b’‧‧‧圖案化的罩幕層 204‧‧‧光阻層 206‧‧‧溝槽 208‧‧‧半導體鰭 210‧‧‧絕緣材料 210a‧‧‧絕緣體 212‧‧‧虛擬閘極堆疊結構 212a‧‧‧虛擬閘極介電層 212b‧‧‧虛擬閘極 212c‧‧‧間隙壁 214‧‧‧應變材料 216‧‧‧閘極堆疊結構 216a‧‧‧閘極介電層 216b‧‧‧閘極 220‧‧‧源極/汲極區 230‧‧‧通道區 300‧‧‧層間介電層 402‧‧‧犧牲氧化物層 D1、D2‧‧‧延伸方向 E‧‧‧暴露的部分 H‧‧‧凹部 M‧‧‧中間部 R‧‧‧凹陷部 T1、T2‧‧‧頂面 w1、w2‧‧‧寬度
圖1是根據一些實施例所繪示的FinFET的製造方法的流程圖。 圖2A至2M是根據一些實施例的FinFET的製造方法的立體圖。 圖3A至3M是根據一些實施例的FinFET的製造方法的剖面圖。 圖4是根據一些實施例的FinFET中的半導體鰭以及閘極的俯視圖。 圖5是根據一些實施例的FinFET的立體圖。
200a‧‧‧半導體基底
210a‧‧‧絕緣體
212c‧‧‧間隙壁
214‧‧‧應變材料
216‧‧‧閘極堆疊結構
216a‧‧‧閘極介電層
216b‧‧‧閘極
220‧‧‧源極/汲極區
300‧‧‧層間介電層
D1、D2‧‧‧延伸方向
w1‧‧‧寬度

Claims (1)

  1. 一種鰭式場效應電晶體（FinFET）的製造方法，包括： 圖案化半導體基底以在所述半導體基底中形成多個溝槽並且在所述溝槽之間形成至少一個半導體鰭； 在所述溝槽中形成多個絕緣體； 在部分所述半導體鰭上方和部分所述絕緣體上方形成虛擬閘極堆疊結構； 在被所述虛擬閘極堆疊結構暴露出的部分所述半導體鰭上方形成應變材料； 移除部分所述虛擬閘極堆疊結構以形成暴露出部分所述半導體鰭的凹部； 移除位於所述凹部中的部分所述半導體鰭；以及 在所述凹部中形成閘極介電材料並填入閘極材料以形成閘極堆疊結構。
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