CN107123598A - 鳍式场效应晶体管及其制造方法 - Google Patents

鳍式场效应晶体管及其制造方法 Download PDF

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CN107123598A
CN107123598A CN201610754909.5A CN201610754909A CN107123598A CN 107123598 A CN107123598 A CN 107123598A CN 201610754909 A CN201610754909 A CN 201610754909A CN 107123598 A CN107123598 A CN 107123598A
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萧茹雄
吴启明
郑志成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

鳍式场效应晶体管(FinFET)包括半导体衬底、多个绝缘体、栅极堆叠件和应变材料。半导体衬底包括位于半导体衬底上的至少一个半导体鳍。半导体鳍包括源极/漏极区和沟道区，并且源极/漏极区的宽度大于沟道区的宽度。绝缘体设置在半导体衬底上并且绝缘体将半导体鳍夹在绝缘体中间。栅极堆叠件位于半导体鳍的沟道区上方和部分绝缘体上方。应变材料覆盖半导体鳍的源极/漏极区。此外，提供了用于制造FinFET的方法。

Description

鳍式场效应晶体管及其制造方法
技术领域
本发明的实施例涉及鳍式场效应晶体管及其制造方法。
背景技术
随着半导体器件在尺寸上不断减小，诸如鳍式场效应晶体管(FinFET)的三维多栅极结构已经发展以替代平面的互补金属氧化物半导体(CMOS)器件。FinFET的结构特征是硅基鳍，硅基鳍从衬底表面垂直延伸，并且包绕由鳍形成的导电沟道的栅极进一步提供了对沟道的更好的电控制。源极/漏极(S/D)和沟道的轮廓对于器件性能是至关重要的。
发明内容
本发明的实施例提供了一种制造鳍式场效应晶体管(FinFET)的方法，包括：图案化半导体衬底以在所述半导体衬底中形成多个沟槽并且在所述沟槽之间形成至少一个半导体鳍；在所述沟槽中形成多个绝缘体；在部分所述半导体鳍上方和部分所述绝缘体上方形成伪栅极堆叠件；在由所述伪栅极堆叠件暴露的部分所述半导体鳍上方形成应变材料；去除部分所述伪栅极堆叠件以形成暴露部分所述半导体鳍的凹部；去除位于所述凹部中的部分所述半导体鳍；以及在所述凹部中形成栅极介电材料并且填充栅极材料以形成栅极堆叠件。
本发明的另一实施例提供了一种制造鳍式场效应晶体管(FinFET)的方法，包括：图案化半导体衬底以在所述半导体衬底中形成多个沟槽并且在所述沟槽之间形成至少一个半导体鳍；在所述沟槽中形成多个绝缘体；在部分所述半导体鳍上方和部分所述绝缘体上方形成伪栅极堆叠件以暴露所述半导体鳍的源极/漏极区，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件；在所述半导体鳍的所述源极/漏极区上方形成应变材料；去除所述伪栅极和所述伪栅极介电层以暴露所述半导体鳍的沟道区；去除所述半导体鳍的部分所述沟道区；以及在所述半导体鳍的所述沟道区上方形成栅极介电材料和栅极材料以形成栅极堆叠件。
本发明的又一实施例提供了一种鳍式场效应晶体管(FinFET)，包括：半导体衬底，包括位于所述半导体衬底上的至少一个半导体鳍，其中，所述半导体鳍包括源极/漏极区和沟道区，并且所述源极/漏极区的宽度大于所述沟道区的宽度；多个绝缘体，设置在所述半导体衬底上，所述绝缘体将所述半导体鳍夹在中间；栅极堆叠件，位于所述半导体鳍的所述沟道区上方和部分所述绝缘体上方；以及应变材料，覆盖所述半导体鳍的所述源极/漏极区。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例的示出用于制造FinFET的方法的流程图。
图2A至2M是根据一些实施例的用于制造FinFET的方法的立体图。
图3A至3M是根据一些实施例的用于制造FinFET的方法的截面图。
图4是根据一些实施例的FinFET中的半导体鳍和栅极的俯视图。
图5是根据一些实施例的FinFET的立体图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
本发明的实施例描述了FinFET的示例性制造工艺以及由其制造的FinFET。在本发明的某些实施例中，可在块状硅衬底上形成FinFET。仍然地，可选地，可在绝缘体上硅(SOI)衬底、绝缘体上锗(GOI)衬底、SiGe衬底或III-V族半导体衬底上形成FinFET。并且，根据实施例，硅衬底可包括其它导电层或诸如晶体管、二极管等的其它半导体元件。在本文中，实施例不被限制。
参照图1，示出根据本发明的一些实施例的示出用于制造FinFET的方法的流程图。该方法至少包括步骤S10、步骤S12、步骤S14、步骤S16、步骤S18、步骤S20、步骤S22和步骤S24。首先，在步骤S10中，图案化半导体衬底以在半导体衬底中形成多个沟槽并且在沟槽之间形成至少一个半导体鳍。然后，在步骤S12中，绝缘体形成在半导体衬底上并且位于沟槽中。例如，绝缘体是用于绝缘或隔离半导体鳍的浅沟槽隔离(STI)结构。其后，在步骤S14中，在部分半导体鳍上方和绝缘体上方形成伪栅极堆叠件。随后，在步骤S16中，形成应变材料(或高掺杂的低电阻材料)以覆盖由伪栅极堆叠件暴露的半导体鳍。然后，在步骤S18中，在应变材料和绝缘体上方形成层间介电层。然后，在步骤S20中，去除部分伪栅极堆叠件以形成凹部，凹部暴露部分半导体鳍。此后，在步骤22中，去除位于凹部中的部分半导体鳍。随后，如步骤S24所示，在凹部中填充栅极介电材料和栅极材料以得到栅极堆叠件。如图1示出，在伪栅极堆叠件形成之后形成应变材料部分。然而，在本发明中不限制伪栅极堆叠件(步骤S14)和应变材料(步骤S16)的形成顺序。
图2A是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3是沿着图2A的线I-I’截取的FinFET的截面图。在图1中的步骤S10中并且如图2A和图3A所示，提供了半导体衬底200。在一个实施例中，半导体衬底200包括晶体硅衬底(例如晶圆)。半导体衬底200可以包括依据设计需求的各个掺杂区(例如，p型半导体衬底或n型半导体衬底)。在一些实施例中，掺杂区可以掺杂有p型或n型掺杂剂。例如，掺杂区可以掺杂有诸如硼或BF2的p型掺杂剂；诸如磷或砷的n型掺杂剂；和//或它们的组合。掺杂区可以配置为用于n型FinFET，或可选地配置为用于p型FinFET。在一些可选实施例中，半导体衬底200可以由诸如金刚石或锗的一些其它合适的元素半导体；诸如砷化镓、碳化硅、砷化铟或磷化铟的合适的化合物半导体；或诸如碳化硅锗、磷化镓砷、磷化镓铟的合适的合金半导体制成。
在一个实施例中，依次在半导体衬底200上形成垫层202a和掩模层202b。垫层202a可以是通过例如热氧化工艺形成的氧化硅薄膜。垫层202a可以充当半导体衬底200和掩模层202b之间的粘合层。垫层202a也可以充当蚀刻掩模层202b的蚀刻停止层。在至少一个实施例中，掩模层202b是通过例如低压化学汽相沉积(LPCVD)或等离子体增强的化学汽相沉积(PECVD)形成的氮化硅层。在后续光刻工艺期间，掩模层202b用作硬掩模。在掩模层202b上形成具有预定图案的图案化的光刻胶层204。
图2B是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3B是沿着图2B的线I-I’截取的FinFET的截面图。在图1中的步骤S10中并且如图2A至2B和图3A至3B所示，依次蚀刻未被图案化的光刻胶层204覆盖的掩模层202b和垫层202a以形成图案化的掩模层202b’和图案化的垫层202a’以暴露下面的半导体衬底200。通过使用图案化的掩模层202b’、图案化的垫层202a’和图案化的光刻胶层204作为掩模，暴露和蚀刻部分半导体衬底200以形成沟槽206和半导体鳍208。图案化的掩模层202b’、图案化的垫层202a’和图案化的光刻胶层204覆盖半导体鳍208。两个相邻的沟槽206间隔开一定间距。例如，沟槽206之间的间距可以小于约30nm。换言之，两个相邻的沟槽206由相应的半导体鳍208间隔开。
半导体鳍208的高度和沟槽206的深度在从约5nm至约500nm的范围。在形成沟槽206和半导体鳍208之后，然后去除图案化的光刻胶层204。在一个实施例中，可以实施清洁工艺以去除半导体衬底200a和半导体鳍208的原生氧化物。可以使用稀释的氢氟(DHF)酸或其他合适的清洁溶液实施清洁工艺。
图2C是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3C是沿着图2C的线I-I’截取的FinFET的截面图。在图1中的步骤S12中并且如图2B至2C和图3B至3C所示，在半导体衬底200a上方形成绝缘材料210以覆盖半导体鳍208并且填充沟槽206。除了半导体鳍208，绝缘材料210进一步覆盖图案化的垫层202a’和图案化的掩模层202b’。绝缘材料210可以包括氧化硅、氮化硅、氮氧化硅、旋涂介电材料或低K介电材料。应当注意，低K介电材料通常是具有低于3.9的介电常数的介电材料。可通过高密度等离子体化学汽相沉积(HDP-CVD)、次大气压CVD(SACVD)或旋涂形成绝缘材料210。
图2D是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3D是沿着图2D的线I-I’截取的FinFET的截面图。在图1中的步骤S12中并且如图2C至2D和图3C至3D所示，实施例如化学机械抛光(CMP)工艺和湿蚀刻工艺以去除部分绝缘材料210、图案化的掩模层202b’和图案化的垫层202a’，直到暴露半导体鳍208。如图2D和图3D所示，在抛光绝缘材料210之后，抛光的绝缘材料210的顶面与半导体鳍208的顶面T2大致共面。
图2E是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3E是沿着图2E的线I-I’截取的FinFET的截面图。在图1中的步骤S12中并且如图2D至2E和图3D至3E所示，通过蚀刻工艺部分地去除填充在沟槽206中的抛光的绝缘材料210，使得在半导体衬底200a上形成绝缘体210a，并且每个绝缘体210a都位于两个相邻的半导体鳍208之间。在一个实施例中，蚀刻工艺可以是具有氢氟酸(HF)的湿蚀刻工艺或干蚀刻工艺。绝缘体210a的顶面T1低于半导体鳍208的顶面T2。半导体鳍208从绝缘体210a的顶面T1突出。半导体鳍208的顶面T2与绝缘体210a的顶面T1之间的高度差在从约15nm至约50nm的范围。
图2F是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3F是沿着图2F的线I-I’截取的FinFET的截面图。在图1中的步骤S14中并且如图2E至2F和图2F至3F所示，在部分半导体鳍208和部分绝缘体210a上方形成伪栅极堆叠件212。在一个实施例中，例如，伪栅极堆叠件212的延伸方向D1垂直于半导体鳍208的延伸方向D2以覆盖半导体鳍208的中间部M(如图3F所示)。伪栅极堆叠件212包括伪栅极介电层212a和设置在伪栅极介电层212a上方的伪栅极212b。伪栅极212b设置在部分半导体鳍208上方和部分绝缘体210a上方。根据一些实施例，在半导体鳍208(如图2E所示)之后，形成伪栅极介电层212a以分离半导体鳍208和伪栅极212b并且作为蚀刻停止层。
形成伪栅极介电层212a以覆盖半导体鳍208的中间部M。在一些实施例中，伪栅极介电层212a可以包括氧化硅、氮化硅或氮氧化硅。可使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化或它们的组合的合适的工艺形成伪栅极介电层212a。
然后在伪栅极介电层212a上形成伪栅极212b。在一些实施例中，伪栅极212b可以包括单层或多层结构。在一些实施例中，伪栅极212b包括诸如多晶硅、无定形硅或它们的组合的含硅材料，并且在应变材料214形成之前形成。在一些实施例中，伪栅极212b包括在约30nm至约90nm的范围内的厚度。可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的工艺形成伪栅极212b。
此外，伪栅极堆叠件212可以进一步包括设置在伪栅极介电层212a和伪栅极212b的侧壁上的一对间隔件212c。这一对间隔件212c可进一步覆盖部分半导体鳍208。间隔件212c由诸如氧化硅、氮化硅、碳氮化硅(SiCN)、SiCON或它们的组合的介电材料形成。间隔件212c可以包括单层或多层结构。未被栅极堆叠件212覆盖的部分半导体鳍208在下文中称为暴露的部分E。
图2G是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3G是沿着图2G的线II-II’截取的FinFET的截面图。在图1中的步骤S16中并且如图2F至2G和图3F至3G所示，去除和凹陷半导体鳍208的暴露的部分E以形成凹进部R。例如，通过各向异性蚀刻、各向同性蚀刻或它们的组合去除暴露的部分E。在一些实施例中，半导体鳍208的暴露的部分E凹进至绝缘体210a的顶面T1下方。凹进部R的深度小于绝缘体210a的厚度。换言之，未完全去除半导体鳍208的暴露的部分E，以及位于凹进部R中的剩余的半导体鳍208组成源极/漏极区220。如图2G和3G所示，当凹陷半导体鳍208的暴露的部分E时，未去除被伪栅极堆叠件212覆盖的部分半导体鳍208。在伪栅极堆叠件212的侧壁处暴露由伪栅极堆叠件212覆盖的部分半导体鳍208。
图2H是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3H是沿着图2H的线II-II’截取的FinFET的截面图。在图1中的步骤S16中并且如图2G至2H和图2G至3H所示，在半导体鳍208的凹进部R上方生长应变材料214(或高掺杂的低电阻材料)并且延伸超过绝缘体210a的顶面T1以使半导体鳍208受到应变或应力。换言之，在半导体鳍208的源极/漏极区220上方形成应变材料214。因此，应变材料214包括设置在伪栅极堆叠件212的一侧处的源极和设置在伪栅极堆叠件212的另一侧处的漏极。源极覆盖半导体鳍208的一端并且漏极覆盖半导体鳍208的另一端。
应变材料214可由导电掺杂剂掺杂。在一个实施例中，诸如SiGe的应变材料214外延生长有用于使p型FinFET应变的p型掺杂剂。就是说，掺杂有p型掺杂剂的应变材料214成为p型FinFET的源极和漏极。p型掺杂剂包括硼或BF2，并且应变材料214可以通过利用原位掺杂的LPCVD工艺外延生长。在另外的实施例中，诸如SiC、SiP、SiC/SiP的组合或SiCP的应变材料214外延生长有用于使n型FinFET应变的n型掺杂剂。就是说，掺杂有n型掺杂剂的应变材料214成为n型FinFET的源极和漏极。n型掺杂剂包括砷和/或磷，并且应变材料214可以通过利用原位掺杂的LPCVD工艺外延生长。应变材料214可以是单层或多层。
图2I是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3I是沿着图2I的线II-II’截取的FinFET的截面图。在图1中的步骤S18中并且如图2I和图3I所示，在应变材料214和绝缘体210a上方形成层间介电层300。换言之，与间隔件212c相邻形成层间介电层300。层间介电层300包括氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、旋涂玻璃(SOG)，氟化硅玻璃(FSG)，碳掺杂的氧化硅(例如，SiCOH)，聚酰亚胺、和/或它们的组合。在一些其它实施例中，层间介电层300包括低K介电材料。低K介电材料的实例包括Black(加利福尼亚州圣克拉拉的应用材料公司)、干凝胶、气凝胶、无定形氟化碳、聚对二甲苯、BCB(双-苯并环丁烯)、Flare、(密西根州米兰的陶氏化学公司)、氢倍半硅氧烷(HSQ)或氟化硅氧化物、和/或它们的组合。应当理解，层间介电层300可以包括一种或多种介电材料和/或一个或多个介电层。在一些实施例中，通过可流动CVD(FCVD)、CVD、HDPCVD、SACVD、旋涂、溅射或其它合适的方法以合适的厚度形成层间介电层300。特别地，首先形成层间介电材料层(未示出)以覆盖绝缘体210a和伪栅极堆叠件212。随后，减小层间介电材料层的厚度直到暴露伪栅极堆叠件212的顶面，以形成层间介电层300。通过化学机械抛光(CMP)工艺、蚀刻工艺或其它合适的工艺实现减小层间介电材料层的厚度的工艺。
图2J是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3J是沿着图2J的线I-I’截取的FinFET的截面图。在图1中的步骤S20中并且如图2J和图3J所示，去除部分伪栅极堆叠件212以形成暴露部分半导体鳍208的凹部H。详细地，去除伪栅极212b和伪栅极介电层212a，并且凹部H暴露半导体鳍208的部分中间部M。应当注意，由凹部H暴露的半导体鳍208可以充当沟道区230。
在一些实施例中，通过蚀刻工艺或其它合适的工艺去除伪栅极212b和伪栅极介电层212a。例如，可通过湿蚀刻或干蚀刻去除伪栅极212b和伪栅极介电层212a。湿蚀刻的实例包括化学蚀刻，并且干蚀刻的实例包括等离子体蚀刻，但是它们不解释为限制本发明。其他公知的蚀刻方法也可以适用于实施伪栅极212b和伪栅极介电层212a的去除。应当注意，在这个阶段处，半导体鳍208具有大致均匀的厚度w1。换言之，位于凹部H中的半导体鳍208的宽度和由间隔件212c、层间介电层300和应变材料214覆盖的半导体鳍208的宽度大致相同。如图2J所示，半导体鳍208的源极/漏极区220的宽度也是w1。
图2K和图2L是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3K和图3L分别是沿着图2K和2L的线I-I’截取的FinFET的截面图。在图1中的步骤S22中并且如图2K-2L和图3K-3L所示，去除位于凹部H中的半导体鳍208的部分沟道区230。详细地，如图2K和3K所示，对由凹部H暴露的半导体鳍208的沟道区230实施氧化处理以形成牺牲氧化物层402。通过例如将含氧气体传输到半导体鳍208以氧化由凹部H暴露的半导体鳍208的表面来实现氧化处理。在一些实施例中，含氧气体可包括臭氧(O3)、过氧化氢(H2O2)或其它合适的包含氧原子的气体。特别地，在含氧气体到达半导体鳍208的沟道区230的表面之后，气体中的氧原子将与半导体鳍208中的元素反应形成氧化物。例如，如果半导体鳍208的材料是硅，生成的牺牲氧化物层402可以包括二氧化硅。应当注意，由于氧化处理是干处理，伪栅极介电层212a的去除和半导体鳍208的氧化处理可以通过原位工艺完成。换言之，如果通过干蚀刻实施伪栅极介电层212a的去除，那么去除工艺和氧化处理是原位工艺并且可以在单个室中实施。
如图2L和图3L所示，在氧化半导体鳍208的表面以形成牺牲氧化物层402之后，去除牺牲氧化物层402以得到更薄的沟道区230。在一些实施例中，可以使用稀释的氢氟(DHF)酸或其它合适的溶液实施牺牲氧化物层402的去除。应当注意，由于由凹部H暴露的部分半导体鳍208转换成牺牲氧化物层402并且后续被去除，因此沟道区230的宽度w2小于半导体鳍208的源极/漏极区220的宽度w1。
图2M是在制造方法的各个阶段的一个阶段处的FinFET的立体图，以及图3M是沿着图2M的线I-I’截取的FinFET的截面图。在图1中的步骤S22中并且如图2M和图3M所示，在凹部H中填充栅极介电材料和栅极材料以形成栅极堆叠件216。特别地，栅极堆叠件216包括栅极介电层216a、栅极216b和间隔件212c。在半导体鳍208的沟道区230上方设置栅极介电层216a，在栅极介电层216a上方设置栅极216b，以及在栅极介电层216a和栅极216b的侧壁上设置间隔件212c。栅极介电层216a的材料可以与伪栅极介电层212a的材料相同或不同。例如，栅极介电层216a包括氧化硅、氮化硅、氮氧化硅、高K介电材料或它们的组合。高K介电材料包括诸如Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、和/或它们的组合的氧化物的金属氧化物。在一些实施中，栅极介电层216a具有在约10埃至30埃的范围内的厚度。使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、可流动化学汽相沉积(PCVD)、热氧化、UV-臭氧氧化或它们的组合的合适的工艺形成栅极介电层216a。栅极介电层216a可以进一步包括界面层(未示出)。例如，可以使用界面层以在半导体鳍208和栅极216b之间创建良好的界面，以及抑制半导体器件的沟道载流子的迁移率的退化。此外，通过热氧化工艺、化学汽相沉积(CVD)工艺或原子层沉积(ALD)工艺形成界面层。界面层的材料包括诸如氧化硅层或氮氧化硅层的介电材料。
栅极216b的材料包括金属、金属合金或金属氮化物。例如，在一些实施例中，栅极216b可以包括TiN、WN、TaN、Ru、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。此外，栅极216b可以进一步包括阻挡件、功函数层或它们的组合。如上所述，界面层可以包括在栅极216b和半导体鳍208之间，但是它解释为不限制本发明。在一些可选实施例中，衬垫层、晶种层、粘合层或它们的组合也可以包括在栅极216b和半导体鳍208之间。在图1中的步骤S22中示出的工艺通常称为金属替代工艺。特别地，在一些实施例中，包括多晶硅的伪栅极堆叠件212由包括金属的栅极堆叠件216替代。由于栅极堆叠件216替代伪栅极堆叠件212，所以可以实现形成金属互连(未示出)的后续工艺。例如，形成其它导电线(未示出)以电连接栅极216b和半导体器件中的其它元件。
图4是根据一些实施例的FinFET中的半导体鳍和栅极的俯视图。应当注意，为了清楚地示出栅极216b和半导体鳍208之间的关系，在图4中仅示出两个元件并且省略了FinFET中的其它组件。如上所述，由于由凹部H(如图2J至2K所示)暴露的半导体鳍208的沟道区230遭受氧化处理，因此半导体鳍208的源极/漏极区220的宽度w1大于半导体鳍208的沟道230的宽度w2。换言之，如图4所示，FinFET中的每个半导体鳍208展示出狗骨形状。在一些实施例中，源极/漏极区220的较大的宽度w1允许应变材料214的较大的尺寸，因此增强了器件的性能。同样地，沟道区230的较小的宽度w2有利于更好的栅极控制，并且因此也有助于器件的性能。此外，由于栅极216b填充到凹部H(如图2L至图3M所示)，栅极216b与半导体鳍208的沟道区230对准。换言之，栅极216b与半导体鳍208的沟道区230是自对准的，并且因此FinFET的制造工艺更方便。
图5是根据一些可选实施例的FinFET的立体图。在实施例中，FinFET的制造步骤包括实施与图2A至2F、图2I至2M和图3A至3F、图3I至3M中所示的步骤相同或相似的工艺步骤。换言之，在一些实施例中省略了形成凹进部R的步骤。这样，FinFET中的半导体鳍208也展示出狗骨形状，并且因此可增强器件性能，以及可以实现栅极216b的自对准。
根据本发明的一些实施例，制造FinFET的方法包括至少以下步骤。图案化半导体衬底以在半导体衬底中形成多个沟槽并且在沟槽之间形成至少一个半导体鳍。在沟槽中形成多个绝缘体。在部分半导体鳍上方和部分绝缘体上方形成伪栅极堆叠件。在由伪栅极堆叠件暴露的部分半导体鳍上方形成应变材料。去除部分伪栅极堆叠件以形成暴露部分半导体鳍的凹部。去除位于凹部中的部分半导体鳍。在凹部中填充栅极介电材料和栅极材料以形成栅极堆叠件。
在上述方法中，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件，并且去除部分所述伪栅极堆叠件的步骤和去除位于所述凹部中的部分所述半导体鳍的步骤包括：去除所述伪栅极；去除所述伪栅极介电层以暴露所述半导体鳍；对暴露的半导体鳍实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层。
在上述方法中，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件，并且去除部分所述伪栅极堆叠件的步骤和去除位于所述凹部中的部分所述半导体鳍的步骤包括：去除所述伪栅极；去除所述伪栅极介电层以暴露所述半导体鳍；对暴露的半导体鳍实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施湿蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
在上述方法中，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件，并且去除部分所述伪栅极堆叠件的步骤和去除位于所述凹部中的部分所述半导体鳍的步骤包括：去除所述伪栅极；去除所述伪栅极介电层以暴露所述半导体鳍；对暴露的半导体鳍实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施干蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
在上述方法中，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件，并且去除部分所述伪栅极堆叠件的步骤和去除位于所述凹部中的部分所述半导体鳍的步骤包括：去除所述伪栅极；去除所述伪栅极介电层以暴露所述半导体鳍；对暴露的半导体鳍实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施干蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面，去除所述伪栅极介电层的步骤和实施所述氧化处理的步骤是原位工艺。
在上述方法中，还包括：去除由所述栅极堆叠件暴露的所述半导体鳍以形成所述半导体鳍的凹进部，并且将所述应变材料填充到所述凹进部以覆盖由所述伪栅极堆叠件暴露的所述半导体鳍。
在上述方法中，还包括：在所述应变材料和所述绝缘体上方形成层间介电层，其中，所述层间介电层暴露所述伪栅极堆叠件。
根据本发明的一些实施例，制造FinFET的方法包括至少以下步骤。图案化半导体衬底以在半导体衬底中形成多个沟槽并且在沟槽之间形成至少一个半导体鳍。在沟槽中形成后多个绝缘体。在部分半导体鳍上方和部分绝缘体上方形成伪栅极堆叠件以暴露半导体鳍的源极/漏极区，并且伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件。在半导体鳍的源极/漏极区上方形成应变材料。去除伪栅极介电层和伪栅极以暴露半导体鳍的沟道区。去除半导体鳍的部分沟道区。在半导体鳍的沟道区上方形成栅极介电材料和栅极材料以形成栅极堆叠件。
在上述方法中，其中，去除所述半导体鳍的部分所述沟道区的步骤包括：对所述半导体鳍的所述沟道区实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层。
在上述方法中，其中，去除所述半导体鳍的部分所述沟道区的步骤包括：对所述半导体鳍的所述沟道区实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施湿蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
在上述方法中，其中，去除所述半导体鳍的部分所述沟道区的步骤包括：对所述半导体鳍的所述沟道区实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施干蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
在上述方法中，其中，去除所述半导体鳍的部分所述沟道区的步骤包括：对所述半导体鳍的所述沟道区实施氧化处理以形成牺牲氧化物层；以及去除所述牺牲氧化物层，其中：去除所述伪栅极介电层的步骤包括实施干蚀刻工艺；以及实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面，去除所述伪栅极介电层的步骤和实施所述氧化处理的步骤是原位工艺。
在上述方法中，还包括：去除部分所述半导体鳍以形成所述半导体鳍的凹进部，并且将所述应变材料填充到所述凹进部以覆盖所述半导体鳍的所述源极/漏极区。
在上述方法中，其中，所述半导体鳍的所述源极/漏极区的宽度大于所述半导体鳍的所述沟道区的宽度。
在上述方法中，还包括：在所述应变材料和所述绝缘体上方形成层间介电层，其中，所述层间介电层暴露所述伪栅极堆叠件。
根据本发明的一些实施例，鳍式场效应晶体管(FinFET)包括半导体衬底、多个绝缘体、栅极堆叠件和应变材料。半导体衬底包括其上的至少一个半导体鳍。半导体鳍包括源极/漏极区和沟道区，并且源极/漏极区的宽度大于沟道区的宽度。绝缘体设置在半导体衬底上并且半导体鳍被绝缘体夹在中间。栅极堆叠件位于半导体鳍的沟道区上方和部分绝缘体上方。应变材料覆盖半导体鳍的源极/漏极区。
在上述鳍式场效应晶体管中，其中，所述栅极堆叠件包括：栅极介电层，设置在所述半导体鳍的所述沟道区上方；栅极，设置在所述栅极介电层上方；以及多个间隔件，设置在所述栅极介电层和所述栅极的侧壁上。
在上述鳍式场效应晶体管中，其中，所述栅极堆叠件包括：栅极介电层，设置在所述半导体鳍的所述沟道区上方；栅极，设置在所述栅极介电层上方；以及多个间隔件，设置在所述栅极介电层和所述栅极的侧壁上，所述栅极的材料包括金属、金属合金或金属氮化物。
在上述鳍式场效应晶体管中，其中，所述半导体鳍还包括凹进部，并且将所述应变材料填充到所述凹进部中以覆盖所述半导体鳍的所述源极/漏极区。
在上述鳍式场效应晶体管中，其中，所述栅极与所述半导体膜的所述沟道区对准。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造鳍式场效应晶体管(FinFET)的方法，包括：
图案化半导体衬底以在所述半导体衬底中形成多个沟槽并且在所述沟槽之间形成至少一个半导体鳍；
在所述沟槽中形成多个绝缘体；
在部分所述半导体鳍上方和部分所述绝缘体上方形成伪栅极堆叠件；
在由所述伪栅极堆叠件暴露的部分所述半导体鳍上方形成应变材料；
去除部分所述伪栅极堆叠件以形成暴露部分所述半导体鳍的凹部；
去除位于所述凹部中的部分所述半导体鳍；以及
在所述凹部中形成栅极介电材料并且填充栅极材料以形成栅极堆叠件。
2.根据权利要求1所述的方法，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件，并且去除部分所述伪栅极堆叠件的步骤和去除位于所述凹部中的部分所述半导体鳍的步骤包括：
去除所述伪栅极；
去除所述伪栅极介电层以暴露所述半导体鳍；
对暴露的半导体鳍实施氧化处理以形成牺牲氧化物层；以及
去除所述牺牲氧化物层。
3.根据权利要求2所述的方法，其中：
去除所述伪栅极介电层的步骤包括实施湿蚀刻工艺；以及
实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
4.根据权利要求2所述的方法，其中：
去除所述伪栅极介电层的步骤包括实施干蚀刻工艺；以及
实施所述氧化处理的步骤包括传输含氧气体以氧化所述半导体鳍的表面。
5.根据权利要求4所述的方法，其中，去除所述伪栅极介电层的步骤和实施所述氧化处理的步骤是原位工艺。
6.根据权利要求1所述的方法，还包括：
去除由所述栅极堆叠件暴露的所述半导体鳍以形成所述半导体鳍的凹进部，并且将所述应变材料填充到所述凹进部以覆盖由所述伪栅极堆叠件暴露的所述半导体鳍。
7.根据权利要求1所述的方法，还包括：
在所述应变材料和所述绝缘体上方形成层间介电层，其中，所述层间介电层暴露所述伪栅极堆叠件。
8.一种制造鳍式场效应晶体管(FinFET)的方法，包括：
图案化半导体衬底以在所述半导体衬底中形成多个沟槽并且在所述沟槽之间形成至少一个半导体鳍；
在所述沟槽中形成多个绝缘体；
在部分所述半导体鳍上方和部分所述绝缘体上方形成伪栅极堆叠件以暴露所述半导体鳍的源极/漏极区，其中，所述伪栅极堆叠件包括伪栅极、伪栅极介电层和多个间隔件；
在所述半导体鳍的所述源极/漏极区上方形成应变材料；
去除所述伪栅极和所述伪栅极介电层以暴露所述半导体鳍的沟道区；
去除所述半导体鳍的部分所述沟道区；以及
在所述半导体鳍的所述沟道区上方形成栅极介电材料和栅极材料以形成栅极堆叠件。
9.根据权利要求8所述的方法，其中，去除所述半导体鳍的部分所述沟道区的步骤包括：
对所述半导体鳍的所述沟道区实施氧化处理以形成牺牲氧化物层；以及
去除所述牺牲氧化物层。
10.一种鳍式场效应晶体管(FinFET)，包括：
半导体衬底，包括位于所述半导体衬底上的至少一个半导体鳍，其中，所述半导体鳍包括源极/漏极区和沟道区，并且所述源极/漏极区的宽度大于所述沟道区的宽度；
多个绝缘体，设置在所述半导体衬底上，所述绝缘体将所述半导体鳍夹在中间；
栅极堆叠件，位于所述半导体鳍的所述沟道区上方和部分所述绝缘体上方；以及
应变材料，覆盖所述半导体鳍的所述源极/漏极区。
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