US20230124471A1 - Finfet having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins - Google Patents
Finfet having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins Download PDFInfo
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- US20230124471A1 US20230124471A1 US18/083,576 US202218083576A US2023124471A1 US 20230124471 A1 US20230124471 A1 US 20230124471A1 US 202218083576 A US202218083576 A US 202218083576A US 2023124471 A1 US2023124471 A1 US 2023124471A1
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- dielectric layer
- semiconductor fins
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- thickness
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Definitions
- FinFET fin-type field effect transistor
- FIG. 1 is an exemplary flow chart showing the process steps of a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.
- FIGS. 2 to 12 B are the perspective views and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some embodiments of the disclosure.
- FIGS. 13 to 16 B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- FIGS. 17 to 21 B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- FIGS. 22 to 25 are the perspective views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- FIGS. 26 to 29 are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- FIG. 30 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure.
- FIG. 31 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the fins may be patterned by any suitable method.
- the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- the embodiments of the present disclosure describe the exemplary manufacturing processes of a three-dimensional structure with height differences and the structure(s) fabricated there-from. Certain embodiments of the present disclosure describe the exemplary manufacturing processes of fin field-effect transistor (FinFET) devices and the FinFET devices fabricated there-from.
- the FinFET device may be formed on a monocrystalline semiconductor substrate, such as a bulk silicon substrate in certain embodiments of the present disclosure.
- the FinFET device may be formed on a silicon-on-insulator (SOI) substrate or a GOI (germanium-on-insulator) substrate as alternatives.
- the silicon substrate may include other conductive layers, doped regions or other semiconductor elements, such as transistors, diodes or the like. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.
- FIG. 1 is an exemplary flow chart showing the process steps of a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.
- the various process steps of the process flow illustrated in FIG. 1 may comprise multiple process steps as discussed below.
- FIG. 2 to FIG. 12 B are the perspective views and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some embodiments of the disclosure. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a semiconductor device, such as a FinFET device.
- FIG. 2 is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- a semiconductor substrate 200 is provided.
- the semiconductor substrate 200 comprises a crystalline silicon substrate (e.g., wafer).
- the semiconductor substrate 200 may comprise various doped regions depending on design requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate).
- the doped regions may be doped with p-type or n-type dopants.
- the doped regions may be doped with p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof.
- the doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET.
- the semiconductor substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.
- a pad layer 202 a and a mask layer 202 b are sequentially formed on the semiconductor substrate 200 .
- the pad layer 202 a may be a silicon oxide thin film formed, for example, by thermal oxidation process.
- the pad layer 202 a may act as an adhesion layer between the semiconductor substrate 200 and the mask layer 202 b .
- the pad layer 202 a may also act as an etch stop layer for etching the mask layer 202 b .
- the mask layer 202 b is a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the mask layer 202 b is used as a hard mask during subsequent photolithography processes.
- a patterned photoresist layer 204 having a predetermined pattern is formed on the mask layer 202 b .
- FIG. 3 is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- the substrate 200 is patterned to form trenches 206 in the substrate 200 and fins 208 are formed between the trenches 206 .
- the mask layer 202 b and the pad layer 202 a which are not covered by the patterned photoresist layer 204 are sequentially etched to form a patterned mask layer 202 b ′ and a patterned pad layer 202 a ′ so as to expose the underlying semiconductor substrate 200 .
- the patterned mask layer 202 b ′, the patterned pad layer 202 a ′ and the patterned photoresist layer 204 are exposed and etched to form the trenches 206 and the semiconductor fins 208 .
- the semiconductor fins 208 are covered by the patterned mask layer 202 b ′, the patterned pad layer 202 a ′ and the patterned photoresist layer 204 .
- Two adjacent trenches 206 are spaced apart by a spacing.
- the spacing between trenches 206 may be smaller than about 30 nm.
- two adjacent trenches 206 are spaced apart by a corresponding semiconductor fin 208 .
- the number of the fins 208 shown in FIG. 3 is merely for illustration, in some alternative embodiments, two or more parallel semiconductor fins may be formed in accordance with actual design requirements.
- a height of the semiconductor fins 208 and the depth of the trench 206 range from about 5 nm to about 500 nm.
- the patterned photoresist layer 204 is then removed.
- a cleaning process may be performed to remove a native oxide of the semiconductor substrate 200 a and the semiconductor fins 208 .
- the cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions.
- FIG. 4 and FIG. 5 are perspective views of the semiconductor device at one of various stages of the manufacturing method.
- a plurality of insulators 210 a are formed in the trenches 206 of the semiconductor substrate 200 a .
- an insulating material 210 is first formed over the semiconductor substrate 200 a to cover the semiconductor fins 208 and to fill up the trenches 206 .
- the insulating material 210 is also covering the patterned pad layer 202 a ′ and the patterned mask layer 202 b ′.
- the insulating material 210 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material. It should be noted that the low-K dielectric materials are generally dielectric materials having a dielectric constant lower than 3.9.
- the insulating material 210 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD) or by spin-on processes.
- etching processes are performed to remove a portion of the insulating material 210 , the patterned mask layer 202 b ′ and the patterned pad layer 202 a ′ until the semiconductor fins 208 are exposed.
- the insulating material 210 filled in the trenches 206 is partially removed by the etching process such that the insulators 210 a are formed on the semiconductor substrate 200 a .
- each insulator 210 a is located between two adjacent semiconductor fins 208 .
- the etching process may be a wet etching process with hydrofluoric acid (HF) or a dry etching process.
- the top surfaces 201 T of the insulators 210 a are lower than the top surfaces 208 T of the semiconductor fins 208 .
- the semiconductor fins 208 protrude from the top surfaces 201 T of the insulators 210 a .
- the height difference between the top surfaces 208 T of the semiconductor fins 208 and the top surfaces 201 T of the insulators 210 a ranges from about 15 nm to about 50 nm.
- the protruded portions of the semiconductor fins 208 include a channel region 208 A and source/drain regions 208 B located aside the channel region 208 A.
- the source/drain regions 208 B of the semiconductor fins 208 are of substantially the same height as that of the channel region 208 A of the fins 208 .
- FIG. 6 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 6 B is a sectional view illustrating the semiconductor device of FIG. 6 A taken along the line A-A′.
- a liner structure 212 is formed on the plurality of insulators 210 a and across the semiconductor fins 208 .
- the liner structure 212 includes a cap portion 212 A, sidewall portions 212 B and base portions 212 C.
- the cap portion 212 A is covering the top surfaces 208 T of the semiconductor fins 208 and joined with the sidewall portions 212 B.
- the sidewall portions 212 B are covering sidewalls 208 SD of the semiconductor fins 208 .
- the sidewall portions 212 B may include a first sidewall portion 212 B- 1 and a second sidewall portion 212 B- 2 covering opposite sidewalls 208 SD of a semiconductor fin 208 .
- the cap portion 212 A may be joining the first sidewall portion 212 B- 1 to the second sidewall portion 212 B- 2 .
- the base portions 212 C are covering the insulators 210 a and joined with the sidewall portions 212 B.
- the base portions 212 C may be joined with the first sidewall portion 212 B- 1 and/or the second sidewall portion 212 B- 2 .
- a maximum thickness of the cap portion 212 A is T 1
- a thickness of the sidewall portions 212 B is T 2
- a thickness of the base portions 212 C is T 3 .
- the maximum thickness T 1 of the cap portion 212 A is greater than the thickness T 2 of the sidewall portions 212 B.
- the maximum thickness T 1 and the thickness T 2 satisfies the relationship: 0.08 ⁇ [(T 1 -T 2 )/T 2 ] ⁇ 0.26.
- the thickness T 3 of the base portions 212 C is substantially equal to the thickness T 2 of the sidewall portions 212 B.
- the thicknesses of the cap portion 212 A, the sidewall portions 212 B and the base portions 212 C T 1 , T 2 and T 3 in such a range, an issue of over-etching on the semiconductor fins 208 or the formation of pits on the semiconductor fins 208 may be prevented.
- [(T 1 -T 2 )/T 2 ] is smaller than 0.08, then the impact on the formation of pits on the semiconductor fins 208 becomes worse.
- [(T 1 -T 2 )/T 2 ] is greater than 0.26, then it increases the manufacturing time during subsequent etching process, and increases the manufacturing cost.
- the liner structure 212 is formed by performing a deposition process and a plasma treatment process, for example.
- the deposition process includes introducing a plurality of precursors over a surface of the plurality of insulators 210 a and on the semiconductor fins 208 to form a liner layer (not shown).
- the deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, and the plurality of precursors is silicon-containing precursors.
- the silicon-containing precursors is SAM-24 (H 2 Si[N(C 2 H 5 ) 2 ] 2 ).
- the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 15 W to 800 W. In certain embodiments, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 500 W to 650 W to form the liner layer. The plasma-enhanced atomic layer deposition process is performed at a plasma power of 500 W to 650 W so that the liner layer having the desired thickness is ensured. In one embodiment, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 600 W.
- the plasma treatment process includes treating the liner layer with a plasma selected from the group consisting of helium, argon, oxygen and hydrogen for 20 to 40 seconds under a source power of 500 W to 1500 W to form the liner structure 212 .
- the plasma treatment process includes a decoupled plasma oxidation process to form an oxide layer (e.g. such as silicon oxide) constituting the liner structure 212 .
- the plasma treatment process is performed to increase the thickness of the cap portion 212 A of the liner structure 212 .
- the liner structure 212 including the cap portion 212 A, the sidewall portions 212 B, and the base portions 212 C may be formed.
- FIG. 7 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 7 B is a sectional view illustrating the semiconductor device of FIG. 7 A taken along the line B-B′.
- a dielectric layer 214 is conformally formed over the liner structure 212 and across the semiconductor fins 208 .
- a thickness of the dielectric layer 214 is maintained to be the same along the base portions 212 C, the sidewall portions 212 B and the cap portion 212 A of the liner structure 212 .
- a thickness of the dielectric layer 214 on the sidewall portions 212 B is the same as a thickness of the dielectric layer 214 on the cap portion 212 A.
- the dielectric layer 214 is formed to cover the channel region 208 A and the source/drain regions 208 B of the semiconductor fins 208 .
- the liner structure 212 is sandwiched in between the insulators 210 a and the dielectric layer 214 , or sandwiched in between the semiconductor fins 208 and the dielectric layer 214 .
- the material of the dielectric layer 214 may be silicon oxide, silicon nitride, silicon carbonitride or the like.
- the method of forming the dielectric layer 214 may be an atomic layer deposition method. In some alternative embodiments, the formation of a dielectric layer 214 on the insulators 210 a may be omitted.
- FIG. 8 is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- a dummy gate stack 216 is formed on the dielectric layer 214 and across the semiconductor fins 208 .
- the dummy gate stack 216 may include a polysilicon strip 216 A and a hard mask strip 216 B.
- the dummy gate stack 216 is formed by forming a dummy layer (including a polysilicon layer and a hard mask layer) over the dielectric layer 214 and across the semiconducfigtor fins 208 , and patterning the dummy layer to form the polysilicon strip 216 A and the hard mask strip 216 B.
- the number of dummy gate stack 216 is not limited to one and may be more than one.
- the extension direction of the dummy gate stack 216 (the polysilicon strip 216 A and the hard mask strip 216 B) is arranged to be perpendicular to the extension direction of the semiconductor fins 208 , and the dummy gate stack 216 is arranged across the semiconductor fins 208 and covers the channel region 208 A of the semiconductor fins 208 .
- the material of the hard mask strip 216 B includes silicon nitride, silicon oxide or the combination thereof.
- spacer structures 218 are formed on two opposite sides of the dummy gate stack 216 .
- the spacer structures 218 are located on the dielectric layer 214 and are covering sidewalls of the polysilicon strip 216 A and the hard mask strip 216 B.
- the spacer structures 218 may be formed by conformally forming a spacer material layer over the dielectric layer 214 and over the dummy gate stack 216 , then performing an etching process on the spacer material layer to form the spacer structures 218 .
- the spacer material layer is formed of one or more dielectric materials, such as silicon nitride, silicon carbon oxynitride (SiCON), silicon carbonitride (SiCN) or combinations thereof.
- the spacer material layer may be a single layer or a multilayered structure.
- the spacer material layer is formed by depositing a blanket layer of one or more dielectric materials.
- the spacer material layer has a thickness ranging from 3 nm to 10 nm.
- FIG. 9 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 9 B is a sectional view illustrating the semiconductor device of FIG. 9 A taken along the line C-C′.
- the dielectric layer 214 is patterned so that side surfaces 214 SD of the dielectric layer 214 are aligned with side surfaces of the spacer structure 218 .
- portions of the dielectric layer 214 not covered by the dummy gate stack 216 and the spacer structures 218 are removed.
- the dielectric layer 214 may be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes.
- ALE atomic layer etching
- the liner structure 212 still includes the cap portion 212 A, sidewall portions 212 B and the base portions 212 C, wherein the cap portion 212 A has the greatest thickness T 1 .
- portions of the liner structure 212 located on the source/drain regions 208 B (see FIG. 5 ) of the semiconductor fins 208 may be patterned and removed along with the dielectric layer 214 . For example, after the patterning process, the cap portion 212 A, the sidewall portions and the base portions 212 C of the liner structure 212 located on the source/drain regions 208 B are removed.
- the liner structure 212 on the source/drain regions 208 B may be removed by selective etching processes to reveal the semiconductor fins 208 .
- side surfaces 212 SD of the liner structure 212 may be aligned with the side surfaces 214 SD of the dielectric layer 214 after the patterning process.
- FIG. 10 is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- strained material portions 220 may be formed on the source/drain regions 208 B (see FIG. 5 ) of the semiconductor fins 208 .
- the strained material portions 220 are formed over portions of the semiconductor fins 208 that are revealed by the dummy gate stack 216 .
- the strained material portions 220 covers and contacts the semiconductor fins 208 .
- the strained material portions 220 are located on two opposite sides of the dummy gate stack 216 .
- the strained material portions 220 (or a high doped low resistance material) is grown on the source/drain regions 208 B of the semiconductor fins 208 to strain or stress the semiconductor fins 208 .
- the strained material portions 220 comprises a source disposed at a side of the dummy stack gate 216 and a drain disposed at the other side of the dummy gate stack 216 .
- the source covers an end of the semiconductor fins 208 and the drain covers the other end of the semiconductor fins 208 .
- the strained material portions 220 may be doped with a conductive dopant.
- the strained material portions 220 include materials such as SiGe, and is epitaxial-grown with a p-type dopant for straining a p-type FinFET. That is, the strained material portions 220 is doped with the p-type dopant to be the source and the drain of the p-type FinFET.
- the p-type dopant comprises boron or BF 2
- the strained material portions 220 may be epitaxial-grown by LPCVD process with in-situ doping.
- the strained material portions 220 include materials such as SiC, SiP, a combination of SiC/SiP, or SiCP, and is epitaxial-grown with an n-type dopant for straining an n-type FinFET. That is, the strained material portions 220 is doped with the n-type dopant to be the source and the drain of the n-type FinFET.
- the n-type dopant comprises arsenic and/or phosphorus
- the strained material portions 220 may be epitaxial-grown by LPCVD process with in-situ doping.
- the strained material portions 220 may be a single layer or a multi-layer.
- FIG. 11 is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- an interlayer dielectric layer 222 is formed on the insulators 210 a and covering the strained material portions 220 .
- the interlayer dielectric layer 222 is formed adjacent to the spacer structures 218 .
- the interlayer dielectric layer 222 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), polyimide, and/or a combination thereof.
- the interlayer dielectric layer 222 includes low-K dielectric materials.
- low-K dielectric materials examples include BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SILK® (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF), and/or a combination thereof.
- the interlayer dielectric layer 222 may include one or more dielectric materials and/or one or more dielectric layers.
- the interlayer dielectric layer 222 is formed to a suitable thickness by flowable CVD (FCVD), CVD, high density plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods.
- FCVD flowable CVD
- CVD high density plasma CVD
- SACVD sub-atmospheric CVD
- an interlayer dielectric material layer (not illustrated) is formed to cover the insulators 210 a and the dummy gate stack 216 first. Subsequently, the thickness of the interlayer dielectric material layer is reduced until a top surface of the dummy gate stack 216 is exposed, so as to form the interlayer dielectric layer 222 .
- the process of reducing the thickness of the interlayer dielectric material layer is achieved by a chemical mechanical polishing (CMP) process, an etching process, or other suitable process.
- CMP chemical mechanical polishing
- FIG. 12 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 12 B is a sectional view illustrating the semiconductor device of FIG. 12 A taken along the line D-D′.
- a gate stack 224 is formed by replacing the dummy gate stack 216 with the gate stack 224 .
- the polysilicon strip 216 A and the hard mask strip 216 B located on the channel region 208 A of the semiconductor fins 208 are removed.
- the polysilicon strips 216 A and the hard mask strips 216 B are removed by anisotropic etching, whereas the spacer structures 218 , the liner structure 212 and the dielectric layer 214 are retained.
- a gate stack 224 is formed over the channel region 208 A of the semiconductor fins 208 , and over the liner structure 212 and on the dielectric layer 214 .
- the gate stack 224 includes a gate dielectric layer 224 A and a gate electrode layer 224 B, and the gate stack 224 is located in between the spacer structures 218 .
- the gate dielectric layer 224 A is formed within the recesses between the spacer structures 218 and on the dielectric layer 214 , and over the channel regions 208 A of the semiconductor fins 208 .
- the gate dielectric layer 224 A is conformally formed on the dielectric layer 214 and over the liner structure 212 .
- a thickness of the gate dielectric layer 224 A is maintained to be the same along the base portions 212 C, the sidewall portions 212 B and the cap portion 212 A of the liner structure 212 .
- the material of the gate dielectric layer 224 A includes silicon oxide, silicon nitride or the combination thereof.
- the gate dielectric layer 224 A includes a high-k dielectric material, and the high-k dielectric material has a k value greater than about 3.9 and includes a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof.
- the gate dielectric layer 224 A is formed by atomic layered deposition, molecular beam deposition (MBD), physical vapor deposition (PVD) or thermal oxidation.
- the gate electrode layer 224 B is formed on the gate dielectric layer 224 A, over the channel region 208 A of the semiconductor fins 208 and fills the remaining recesses between the spacer structures 218 .
- the gate dielectric layer 224 A is formed in between the gate electrode layer 224 B and the dielectric layer 214 .
- the gate electrode layer 224 B includes a metal-containing material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof.
- a metal-containing material such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof.
- the materials of the gate dielectric layer 224 A and/or the gate electrode layer 224 B are appropriately chosen.
- a chemical mechanical polishing (CMP) process is performed to remove the excess portions of gate dielectric layer 224 A and the gate electrode layer 224 B.
- the spacer structures 218 are located on sidewalls of the gate dielectric layer 224 A and the gate electrode layer 224 B.
- the dummy gate stack 216 is replaced, and the gate stack 224 is formed.
- the gate stack 216 is a replacement metal gate, but the structure(s) of the gate stack(s) or the fabrication processes thereof are not limited by these embodiments. Up to here, a semiconductor device SM 1 according to some embodiments of the present disclosure is accomplished.
- FIG. 13 to FIG. 16 B are perspective and sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- the embodiment shown in FIG. 13 to FIG. 16 B is similar to the embodiment shown in FIG. 2 to FIG. 12 B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is that the dielectric layer 214 is omitted.
- the same steps described in FIG. 2 to FIG. 6 B may be performed to form the liner structure 212 over the insulators 210 a and across the semiconductor fins 208 .
- a dummy gate stack 216 is formed on the liner structure 212 and across the semiconductor fins 208 .
- the dummy gate stack 216 covers the channel region 208 A of the semiconductor fins 208 .
- spacer structures 218 are formed over the liner structure 212 on two opposite sides of the dummy gate stack 216 .
- the liner structure 212 is patterned so that side surfaces 212 SD of the liner structure 212 are aligned with side surfaces of the spacer structure 218 .
- portions of the liner structure 212 not covered by the dummy gate stack 216 and the spacer structures 218 are removed.
- the liner structure 212 may be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes.
- ALE atomic layer etching
- the same steps may be performed to form strained material portions 220 on the source/drain regions 208 B of the semiconductor fins 208 , whereby the strained material portions 220 covers and contacts the semiconductor fins 208 .
- an interlayer dielectric layer 222 is formed on the insulators 210 a and covering the strained material portions 220 .
- FIG. 16 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 16 B is a sectional view illustrating the semiconductor device of FIG. 16 A taken along the line E-E′.
- the dummy gate stack 216 may be removed and replaced with gate stack 224 .
- a semiconductor device SM 2 according to some other embodiments of the present disclosure is accomplished.
- the liner structure 212 still includes the cap portion 212 A, sidewall portions 212 B and the base portions 212 C.
- the liner structure 212 is sandwiched in between the semiconductor fins 208 and the gate dielectric layer 224 A.
- FIG. 17 to FIG. 21 B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- the embodiment shown in FIG. 13 to FIGS. 16 is similar to the embodiment shown in FIG. 2 to FIG. 12 B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is in the material of the semiconductor fins 208 .
- the same steps described in FIG. 2 to FIG. 5 may be performed to form the semiconductor fins 208 , and insulators 210 a in between the semiconductor fins 208 .
- the semiconductor fins 208 may be silicon fins, for example.
- the disclosure is not limited thereto, and in FIG. 17 to FIG. 21 B , the semiconductor fins 208 are silicon-germanium (SiGe) fins, for example.
- SiGe silicon-germanium
- an additional capping layer 211 may be formed to cover the semiconductor fins 208 .
- the capping layer 211 may be a silicon capping layer.
- the capping layer 211 is formed over the semiconductor fins 208 by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the capping layer 211 covers the top surfaces 208 T and sidewalls 208 SD of the semiconductor fins 208 .
- the capping layer 211 (silicon capping layer) is used to prevent the oxidation on the semiconductor fins 208 during the formation of the liner structure 212 performed in a subsequent step.
- the capping layer 211 prevents the formation of silicon germanium oxide (SiGeOx), which may affect the mobility of the semiconductor device.
- the same steps described in FIG. 6 A to FIG. 8 may be performed to form the liner structure 212 over the capping layer 211 , and to form the dielectric layer 214 over the liner structure 212 . Thereafter, a dummy gate stack 216 and spacer structures 218 are formed on the dielectric layer 214 , whereby the dummy gate stack 216 is located in between the spacer structures 218 .
- FIG. 19 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 19 B is a sectional view illustrating the semiconductor device of FIG. 19 A taken along the line F-F′.
- the dielectric layer 214 is patterned so that side surfaces 214 SD of the dielectric layer 214 are aligned with side surfaces of the spacer structure 218 .
- portions of the liner structure 212 located on the source/drain regions 208 B (see FIG. 5 ) of the semiconductor fins 208 may be patterned and removed along with the dielectric layer 214 .
- the liner structure 212 still includes the cap portion 212 A, sidewall portions 212 B and the base portions 212 C. Furthermore, in some embodiments, the capping layer 211 may be retained on the source/drain regions 208 B (see FIG. 5 ) of the semiconductor fins 208 . However, the disclosure is not limited thereto. For example, in some alternative embodiments, the capping layer 211 on the source/drain regions 208 B may be removed to reveal the semiconductor fins 208 before forming the strained material portions 220 . As illustrated in FIG. 19 A and FIG.
- the capping layer 211 is sandwiched in between the liner structure 212 and the channel region 208 A of the semiconductor fins 208 .
- the liner structure 212 is sandwiched in between the capping layer 211 and the dielectric layer 214 .
- the same steps may be performed to form strained material portions 220 on the source/drain regions 208 B of the semiconductor fins 208 , whereby the strained material portions 220 covers and contacts the capping layer 211 (silicon capping layer).
- an interlayer dielectric layer 222 is formed on the insulators 210 a and covering the strained material portions 220 .
- FIG. 21 A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
- FIG. 21 B is a sectional view illustrating the semiconductor device of FIG. 21 A taken along the line G-G′.
- the dummy gate stack 216 may be removed and replaced with gate stack 224 .
- a semiconductor device SM 3 according to some other embodiments of the present disclosure is accomplished.
- the liner structure 212 still includes the cap portion 212 A, sidewall portions 212 B and the base portions 212 C.
- the liner structure 212 is located in between the capping layer 211 and the gate stack 224 .
- the liner structure 212 is sandwiched in between the capping layer 211 and the dielectric layer 214 .
- FIG. 22 to FIG. 25 are the perspective views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- the embodiment shown in FIG. 22 to FIG. 25 is similar to the embodiment shown in FIG. 2 to FIG. 12 B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is in the way of patterning the liner structure 212 .
- FIG. 22 is a stage of manufacturing a semiconductor device similar to that described in FIG. 8 , whereby a dummy gate stack 216 and spacer structures 218 are formed on the dielectric layer 214 .
- the dielectric layer 214 is patterned so that side surfaces 214 SD of the dielectric layer 214 are aligned with side surfaces of the spacer structure 218 .
- portions of the liner structure 212 located on the source/drain regions 208 B (see FIG. 5 ) of the semiconductor fins 208 may be patterned and removed along with the dielectric layer 214 .
- the liner structure 212 includes the cap portion 212 A located on the source/drain regions 208 B of the semiconductor fins 208 , whereas the sidewall portions and the base portions 212 C are removed.
- sidewalls of the fins 208 are also revealed after the patterning process.
- a thickness of the cap portion 212 A on the source/drain regions 208 B is also reduced.
- the cap portion 212 A since the cap portion 212 A initially has a thickness greater than that of the sidewall portions 212 B and the base portions 212 C, the cap portion 212 A may be retained on the semiconductor fins 208 after the patterning/etching processes.
- the same steps may be performed to form strained material portions 220 on the source/drain regions 208 B of the semiconductor fins 208 , whereby the cap portion 212 A may be covered by the strained material portions 220 .
- the cap portion 212 A of the liner structure 212 is disposed over the source/drain regions 208 B of the semiconductor fins 208 and sandwiched in between the strained material portions 220 and the semiconductor fin 208 .
- an interlayer dielectric layer 222 is formed on the insulators 210 a and covering the strained material portions 220 .
- the dummy gate stack 216 may be removed and replaced with gate stack 224 .
- a semiconductor device SM 4 according to some other embodiments of the present disclosure is accomplished.
- FIG. 26 to FIG. 29 are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure.
- the embodiment shown in FIG. 26 to FIG. 29 is similar to the embodiment shown in FIG. 2 to FIG. 12 B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is in the design of the semiconductor fins 208 .
- FIG. 26 is a stage of manufacturing a semiconductor device similar to that described in FIG. 9 A , whereby the liner structure 212 and the dielectric layer 214 are pattered so that their side surfaces ( 212 SD / 214 SD) may be aligned with side surfaces of the spacer structure 218 .
- the semiconductor fins 208 exposed by the dummy gate stack 216 and the spacer structures 218 are removed/recessed to form a plurality of recessed portions Rc.
- portions of the semiconductor fins 208 may be removed by, anisotropic etching, isotropic etching, or a combination thereof.
- portions of the semiconductor fins 208 are recessed below the top surfaces of the insulators 210 a .
- a depth of the recessed portions Rc is less than a thickness of the insulators 210 a .
- the semiconductor fins 208 exposed by the dummy gate stack 216 and the spacer structures 218 are not entirely removed, and the remaining semiconductor fins 208 located in the recessed portion Rc form the source/drain regions of the semiconductor fins 208 .
- strained material portions 220 may be formed over the recessed portions Rc of the semiconductor fins 208 .
- the strained material portions 220 extends beyond the top surfaces of the insulators 210 a .
- the strained material portions 220 is similar to that described in FIG. 10 , thus its detailed discussion will be omitted herein.
- FIG. 29 the same steps may be performed to form an interlayer dielectric layer 222 on the insulators 210 a and covering the strained material portions 220 .
- the dummy gate stack 216 may be removed and replaced with gate stack 224 .
- a semiconductor device SM 5 according to some other embodiments of the present disclosure is accomplished.
- FIG. 30 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure.
- the semiconductor device illustrated in FIG. 30 is similar to the semiconductor device SM 1 illustrated in FIG. 12 B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is in the design of the liner structure 212 .
- the liner structure 212 is formed with a cap portion 212 A having a substantially planar top surface.
- the disclosure is not limited thereto.
- the cap portion 212 A of the liner structure 212 has a curved top surface.
- a tip of the cap portion 212 A has the maximum thickness T 1
- a side of the cap portion 212 A joined with the first sidewall portion 212 B- 1 has thickness T 13
- another side of the cap portion 212 A joined with the second sidewall portion 212 B- 2 has thickness T 12 .
- the thicknesses T 12 and T 13 being smaller than the thickness T 1 .
- a thickness of the liner structure 212 increases from the first sidewall portion 212 B- 1 to the cap portion 212 A and decreases from the cap portion 212 A to the second sidewall portion 212 B- 2 .
- FIG. 31 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure.
- the semiconductor device illustrated in FIG. 31 is similar to the semiconductor device SM 1 illustrated in FIG. 12 B and similar to the semiconductor device illustrate in FIG. 30 , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein.
- the difference between the embodiments is in the design of the liner structure 212 .
- the liner structure 212 is formed with sidewall portions 212 B having substantially the same thickness along the sidewalls of the semiconductor fins 208 .
- the disclosure is not limited thereto.
- a side of the first sidewall portion 212 B- 1 and the second sidewall portion 212 B- 2 joined with the base portions 212 C has a thickness T 21
- another side of the first sidewall portion 212 B- 1 and the second sidewall portion 212 B- 2 joined with the cap portion 212 A has a thickness T 23 .
- the thickness T 21 being smaller than the thickness T 2
- the thickness T 23 is greater than the thickness T 2 .
- a thickness of the liner structure 212 gradually increases from the base portion 212 C to the first sidewall portion 212 B- 1 and to the cap portion 212 A, and gradually decreases from the cap portion 212 A to the second sidewall portion 212 B- 2 and to the base portion 212 C.
- the liner structure may act to prevent over-etching on the semiconductor fins or the formation of pits on the semiconductor fins. Furthermore, in situations where the semiconductor fins need to be further recessed, over-etching of the semiconductor fins or uneven etching of the semiconductor fins may be prevented when forming the recess. In other words, the strained material portion may be formed over the semiconductor fins having more smooth and planar surfaces due to liner structure protection. Overall, a semiconductor device having less defects and improved performance may be achieved.
- a semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack.
- the substrate has fins and trenches in between the fins.
- the insulators are disposed within the trenches of the substrate.
- the liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T 1 of the cap portion is greater than a thickness T 2 of the sidewall portions.
- the gate stack is disposed on the liner structure and across the fins.
- a semiconductor device includes a substrate, insulators, a liner structure, a gate stack and strained material portions.
- the substrate includes at least one fin, wherein the fin comprises a channel region and source/drain regions.
- the insulators are disposed on the substrate and located on two sides of the fin.
- the liner structure is disposed on the insulators and over the channel region of the fin, wherein the liner structure comprises a first sidewall portion, a second sidewall portion and a cap portion, the first sidewall portion and the second sidewall portion are covering sidewalls of the fin, the cap portion is covering a top surface of the fin and joining the first sidewall portion to the second sidewall portion, and a thickness of the liner structure increases from the first sidewall portion to the cap portion and decreases from the cap portion to the second sidewall portion.
- the gate stack is disposed on the liner structure and across the channel region of the fin.
- the strained material portions are disposed on the source/drain regions of the fin.
- a method of fabricating a semiconductor device includes the following steps.
- a substrate is provided.
- the substrate is patterned to form trenches in the substrate and fins between the trenches.
- a plurality of insulators is formed in the trenches of the substrate.
- a liner structure is formed on the plurality of insulators and across the fin.
- the liner structure is formed by performing a deposition process and a plasma treatment process.
- the deposition process is performed by introducing a plurality of precursors over a surface of the plurality of insulators and on the fins to form a liner layer.
- the plasma treatment process is performed on the liner layer to form the liner structure, wherein after the plasma treatment process, the liner structure is formed to include sidewall portions, base portions and a cap portion, the sidewall portions are covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, the base portions are covering the plurality of insulators and joined with the sidewall portions, and a maximum thickness T 1 of the cap portion is greater than a thickness T 2 of the sidewall portions.
- a gate stack is formed on the liner structure and across the fins.
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Abstract
A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
Description
- This application is a continuation application of U.S. Application Serial No. 16/942,781, filed on Jul. 30, 2020, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- As the semiconductor devices keep scaling down in size, three-dimensional multigate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar CMOS devices. A characteristic of the FinFET device lies in that the structure has one or more silicon-based fins that are wrapped around by the gate to define the channel of the device. The gate wrapping structure further provides better electrical control over the channel.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is an exemplary flow chart showing the process steps of a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure. -
FIGS. 2 to 12B are the perspective views and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some embodiments of the disclosure. -
FIGS. 13 to 16B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. -
FIGS. 17 to 21B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. -
FIGS. 22 to 25 are the perspective views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. -
FIGS. 26 to 29 are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. -
FIG. 30 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure. -
FIG. 31 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- The embodiments of the present disclosure describe the exemplary manufacturing processes of a three-dimensional structure with height differences and the structure(s) fabricated there-from. Certain embodiments of the present disclosure describe the exemplary manufacturing processes of fin field-effect transistor (FinFET) devices and the FinFET devices fabricated there-from. The FinFET device may be formed on a monocrystalline semiconductor substrate, such as a bulk silicon substrate in certain embodiments of the present disclosure. In some embodiments, the FinFET device may be formed on a silicon-on-insulator (SOI) substrate or a GOI (germanium-on-insulator) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers, doped regions or other semiconductor elements, such as transistors, diodes or the like. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.
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FIG. 1 is an exemplary flow chart showing the process steps of a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure. The various process steps of the process flow illustrated inFIG. 1 may comprise multiple process steps as discussed below.FIG. 2 toFIG. 12B are the perspective views and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some embodiments of the disclosure. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a semiconductor device, such as a FinFET device. -
FIG. 2 is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step S10 inFIG. 1 and as shown inFIG. 2 , asemiconductor substrate 200 is provided. In one embodiment, thesemiconductor substrate 200 comprises a crystalline silicon substrate (e.g., wafer). Thesemiconductor substrate 200 may comprise various doped regions depending on design requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET. In some alternative embodiments, thesemiconductor substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. - In one embodiment, a
pad layer 202 a and amask layer 202 b are sequentially formed on thesemiconductor substrate 200. Thepad layer 202 a may be a silicon oxide thin film formed, for example, by thermal oxidation process. Thepad layer 202 a may act as an adhesion layer between thesemiconductor substrate 200 and themask layer 202 b. Thepad layer 202 a may also act as an etch stop layer for etching themask layer 202 b. In at least one embodiment, themask layer 202 b is a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Themask layer 202 b is used as a hard mask during subsequent photolithography processes. In certain embodiments, a patternedphotoresist layer 204 having a predetermined pattern is formed on themask layer 202 b. -
FIG. 3 is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step S10 inFIG. 1 and as shown inFIG. 3 , thesubstrate 200 is patterned to formtrenches 206 in thesubstrate 200 andfins 208 are formed between thetrenches 206. For example, themask layer 202 b and thepad layer 202 a which are not covered by the patternedphotoresist layer 204 are sequentially etched to form a patternedmask layer 202 b′ and a patternedpad layer 202 a′ so as to expose theunderlying semiconductor substrate 200. By using the patternedmask layer 202 b′, thepatterned pad layer 202 a′ and the patternedphotoresist layer 204 as a mask, portions of thesemiconductor substrate 200 are exposed and etched to form thetrenches 206 and thesemiconductor fins 208. In some embodiments, thesemiconductor fins 208 are covered by the patternedmask layer 202 b′, the patternedpad layer 202 a′ and the patternedphotoresist layer 204. Twoadjacent trenches 206 are spaced apart by a spacing. For example, the spacing betweentrenches 206 may be smaller than about 30 nm. In other words, twoadjacent trenches 206 are spaced apart by acorresponding semiconductor fin 208. The number of thefins 208 shown inFIG. 3 is merely for illustration, in some alternative embodiments, two or more parallel semiconductor fins may be formed in accordance with actual design requirements. - In some embodiments, a height of the
semiconductor fins 208 and the depth of thetrench 206 range from about 5 nm to about 500 nm. After thetrenches 206 and thesemiconductor fins 208 are formed, the patternedphotoresist layer 204 is then removed. In one embodiment, a cleaning process may be performed to remove a native oxide of thesemiconductor substrate 200 a and thesemiconductor fins 208. The cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions. -
FIG. 4 andFIG. 5 are perspective views of the semiconductor device at one of various stages of the manufacturing method. In step S12 inFIG. 1 and as shown inFIG. 4 toFIG. 5 , a plurality ofinsulators 210 a are formed in thetrenches 206 of thesemiconductor substrate 200 a. As illustrated inFIG. 4 , in some embodiments, an insulatingmaterial 210 is first formed over thesemiconductor substrate 200 a to cover thesemiconductor fins 208 and to fill up thetrenches 206. Besides covering thesemiconductor fins 208, the insulatingmaterial 210 is also covering the patternedpad layer 202 a′ and the patternedmask layer 202 b′. In some embodiments, the insulatingmaterial 210 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material. It should be noted that the low-K dielectric materials are generally dielectric materials having a dielectric constant lower than 3.9. The insulatingmaterial 210 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD) or by spin-on processes. - Referring to
FIG. 5 , after forming the insulatingmaterial 210, etching processes are performed to remove a portion of the insulatingmaterial 210, the patternedmask layer 202 b′ and the patternedpad layer 202 a′ until thesemiconductor fins 208 are exposed. In some embodiments, the insulatingmaterial 210 filled in thetrenches 206 is partially removed by the etching process such that theinsulators 210 a are formed on thesemiconductor substrate 200 a. For example, eachinsulator 210 a is located between twoadjacent semiconductor fins 208. In one embodiment, the etching process may be a wet etching process with hydrofluoric acid (HF) or a dry etching process. In some embodiments, thetop surfaces 201T of theinsulators 210 a are lower than thetop surfaces 208T of thesemiconductor fins 208. Thesemiconductor fins 208 protrude from thetop surfaces 201T of theinsulators 210 a. The height difference between thetop surfaces 208T of thesemiconductor fins 208 and thetop surfaces 201T of theinsulators 210 a ranges from about 15 nm to about 50 nm. In some embodiments, the protruded portions of thesemiconductor fins 208 include achannel region 208A and source/drain regions 208B located aside thechannel region 208A. In certain embodiments, the source/drain regions 208B of thesemiconductor fins 208 are of substantially the same height as that of thechannel region 208A of thefins 208. -
FIG. 6A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 6B is a sectional view illustrating the semiconductor device ofFIG. 6A taken along the line A-A′. In step S14 inFIG. 1 and as shown inFIG. 6A andFIG. 6B , aliner structure 212 is formed on the plurality ofinsulators 210 a and across thesemiconductor fins 208. In the exemplary embodiment, theliner structure 212 includes acap portion 212A,sidewall portions 212B andbase portions 212C. Thecap portion 212A is covering thetop surfaces 208T of thesemiconductor fins 208 and joined with thesidewall portions 212B. Thesidewall portions 212B are covering sidewalls 208SD of thesemiconductor fins 208. In some embodiments, thesidewall portions 212B may include afirst sidewall portion 212B-1 and asecond sidewall portion 212B-2 covering opposite sidewalls 208SD of asemiconductor fin 208. Thecap portion 212A may be joining thefirst sidewall portion 212B-1 to thesecond sidewall portion 212B-2. Furthermore, thebase portions 212C are covering theinsulators 210 a and joined with thesidewall portions 212B. For example, thebase portions 212C may be joined with thefirst sidewall portion 212B-1 and/or thesecond sidewall portion 212B-2. - As illustrated in
FIG. 6A andFIG. 6B , a maximum thickness of thecap portion 212A is T1, a thickness of thesidewall portions 212B is T2, and a thickness of thebase portions 212C is T3. In some embodiments, the maximum thickness T1 of thecap portion 212A is greater than the thickness T2 of thesidewall portions 212B. In some embodiments, the maximum thickness T1 and the thickness T2 satisfies the relationship: 0.08 ≤ [(T1-T2)/T2] ≤ 0.26. Furthermore, the thickness T3 of thebase portions 212C is substantially equal to the thickness T2 of thesidewall portions 212B. In the exemplary embodiment, by controlling the thicknesses of thecap portion 212A, thesidewall portions 212B and thebase portions 212C T1, T2 and T3 in such a range, an issue of over-etching on thesemiconductor fins 208 or the formation of pits on thesemiconductor fins 208 may be prevented. In some embodiments, if [(T1-T2)/T2] is smaller than 0.08, then the impact on the formation of pits on thesemiconductor fins 208 becomes worse. In some other embodiments, if [(T1-T2)/T2] is greater than 0.26, then it increases the manufacturing time during subsequent etching process, and increases the manufacturing cost. - In the exemplary embodiment, the
liner structure 212 is formed by performing a deposition process and a plasma treatment process, for example. In some embodiments, the deposition process includes introducing a plurality of precursors over a surface of the plurality ofinsulators 210 a and on thesemiconductor fins 208 to form a liner layer (not shown). In certain embodiments, the deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, and the plurality of precursors is silicon-containing precursors. In one embodiment, the silicon-containing precursors is SAM-24 (H2Si[N(C2H5)2]2). Furthermore, in some embodiments, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 15 W to 800 W. In certain embodiments, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 500 W to 650 W to form the liner layer. The plasma-enhanced atomic layer deposition process is performed at a plasma power of 500 W to 650 W so that the liner layer having the desired thickness is ensured. In one embodiment, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 600 W. - Moreover, in some embodiments, the plasma treatment process includes treating the liner layer with a plasma selected from the group consisting of helium, argon, oxygen and hydrogen for 20 to 40 seconds under a source power of 500 W to 1500 W to form the
liner structure 212. In some embodiments, the plasma treatment process includes a decoupled plasma oxidation process to form an oxide layer (e.g. such as silicon oxide) constituting theliner structure 212. In some embodiments, the plasma treatment process is performed to increase the thickness of thecap portion 212A of theliner structure 212. In other words, after the plasma treatment process, theliner structure 212 including thecap portion 212A, thesidewall portions 212B, and thebase portions 212C may be formed. -
FIG. 7A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 7B is a sectional view illustrating the semiconductor device ofFIG. 7A taken along the line B-B′. In step S16 inFIG. 1 and as shown inFIG. 7A andFIG. 7B , adielectric layer 214 is conformally formed over theliner structure 212 and across thesemiconductor fins 208. In some embodiments, a thickness of thedielectric layer 214 is maintained to be the same along thebase portions 212C, thesidewall portions 212B and thecap portion 212A of theliner structure 212. In other words, a thickness of thedielectric layer 214 on thesidewall portions 212B is the same as a thickness of thedielectric layer 214 on thecap portion 212A. In certain embodiments, thedielectric layer 214 is formed to cover thechannel region 208A and the source/drain regions 208B of thesemiconductor fins 208. In some embodiments, theliner structure 212 is sandwiched in between theinsulators 210 a and thedielectric layer 214, or sandwiched in between thesemiconductor fins 208 and thedielectric layer 214. In some embodiments, the material of thedielectric layer 214 may be silicon oxide, silicon nitride, silicon carbonitride or the like. In some embodiments, the method of forming thedielectric layer 214 may be an atomic layer deposition method. In some alternative embodiments, the formation of adielectric layer 214 on theinsulators 210 a may be omitted. -
FIG. 8 is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step S18 inFIG. 1 and as shown inFIG. 8 , adummy gate stack 216 is formed on thedielectric layer 214 and across thesemiconductor fins 208. Thedummy gate stack 216 may include apolysilicon strip 216A and ahard mask strip 216B. In some embodiments, thedummy gate stack 216 is formed by forming a dummy layer (including a polysilicon layer and a hard mask layer) over thedielectric layer 214 and across thesemiconducfigtor fins 208, and patterning the dummy layer to form thepolysilicon strip 216A and thehard mask strip 216B. In the exemplary embodiment, although onedummy gate stack 216 is illustrated herein, it should be noted that the number ofdummy gate stack 216 is not limited to one and may be more than one. In some embodiments, the extension direction of the dummy gate stack 216 (thepolysilicon strip 216A and thehard mask strip 216B) is arranged to be perpendicular to the extension direction of thesemiconductor fins 208, and thedummy gate stack 216 is arranged across thesemiconductor fins 208 and covers thechannel region 208A of thesemiconductor fins 208. In one embodiment, the material of thehard mask strip 216B includes silicon nitride, silicon oxide or the combination thereof. - Referring still to
FIG. 8 , after forming thedummy gate stack 216,spacer structures 218 are formed on two opposite sides of thedummy gate stack 216. In some embodiments, thespacer structures 218 are located on thedielectric layer 214 and are covering sidewalls of thepolysilicon strip 216A and thehard mask strip 216B. In some embodiments, thespacer structures 218 may be formed by conformally forming a spacer material layer over thedielectric layer 214 and over thedummy gate stack 216, then performing an etching process on the spacer material layer to form thespacer structures 218. In some embodiments, the spacer material layer is formed of one or more dielectric materials, such as silicon nitride, silicon carbon oxynitride (SiCON), silicon carbonitride (SiCN) or combinations thereof. The spacer material layer may be a single layer or a multilayered structure. In some embodiments, the spacer material layer is formed by depositing a blanket layer of one or more dielectric materials. In one embodiment, the spacer material layer has a thickness ranging from 3 nm to 10 nm. -
FIG. 9A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 9B is a sectional view illustrating the semiconductor device ofFIG. 9A taken along the line C-C′. Referring toFIG. 9A andFIG. 9B , after forming thedummy gate stack 216 and thespacer structures 218, thedielectric layer 214 is patterned so that side surfaces 214SD of thedielectric layer 214 are aligned with side surfaces of thespacer structure 218. In some embodiments, portions of thedielectric layer 214 not covered by thedummy gate stack 216 and thespacer structures 218 are removed. In certain embodiments, thedielectric layer 214 may be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes. - Referring to
FIG. 9A andFIG. 9B , on thechannel region 208A (seeFIG. 5 ) of thesemiconductor fins 208, theliner structure 212 still includes thecap portion 212A,sidewall portions 212B and thebase portions 212C, wherein thecap portion 212A has the greatest thickness T1. In some embodiments, portions of theliner structure 212 located on the source/drain regions 208B (seeFIG. 5 ) of thesemiconductor fins 208 may be patterned and removed along with thedielectric layer 214. For example, after the patterning process, thecap portion 212A, the sidewall portions and thebase portions 212C of theliner structure 212 located on the source/drain regions 208B are removed. In other words, theliner structure 212 on the source/drain regions 208B may be removed by selective etching processes to reveal thesemiconductor fins 208. In certain embodiments, side surfaces 212SD of theliner structure 212 may be aligned with the side surfaces 214SD of thedielectric layer 214 after the patterning process. -
FIG. 10 is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step S20 inFIG. 1 and as shown inFIG. 10 ,strained material portions 220 may be formed on the source/drain regions 208B (seeFIG. 5 ) of thesemiconductor fins 208. In some embodiments, thestrained material portions 220 are formed over portions of thesemiconductor fins 208 that are revealed by thedummy gate stack 216. In some embodiments, thestrained material portions 220 covers and contacts thesemiconductor fins 208. In some embodiments, thestrained material portions 220 are located on two opposite sides of thedummy gate stack 216. - In the exemplary embodiment, the strained material portions 220 (or a high doped low resistance material) is grown on the source/
drain regions 208B of thesemiconductor fins 208 to strain or stress thesemiconductor fins 208. Thus, thestrained material portions 220 comprises a source disposed at a side of thedummy stack gate 216 and a drain disposed at the other side of thedummy gate stack 216. The source covers an end of thesemiconductor fins 208 and the drain covers the other end of thesemiconductor fins 208. In some embodiments, thestrained material portions 220 may be doped with a conductive dopant. In one embodiment, thestrained material portions 220 include materials such as SiGe, and is epitaxial-grown with a p-type dopant for straining a p-type FinFET. That is, thestrained material portions 220 is doped with the p-type dopant to be the source and the drain of the p-type FinFET. The p-type dopant comprises boron or BF2, and thestrained material portions 220 may be epitaxial-grown by LPCVD process with in-situ doping. In another embodiment, thestrained material portions 220 include materials such as SiC, SiP, a combination of SiC/SiP, or SiCP, and is epitaxial-grown with an n-type dopant for straining an n-type FinFET. That is, thestrained material portions 220 is doped with the n-type dopant to be the source and the drain of the n-type FinFET. The n-type dopant comprises arsenic and/or phosphorus, and thestrained material portions 220 may be epitaxial-grown by LPCVD process with in-situ doping. Thestrained material portions 220 may be a single layer or a multi-layer. -
FIG. 11 is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step S22 inFIG. 1 and as shown inFIG. 11 , aninterlayer dielectric layer 222 is formed on theinsulators 210 a and covering thestrained material portions 220. In some embodiments, theinterlayer dielectric layer 222 is formed adjacent to thespacer structures 218. In some embodiments, theinterlayer dielectric layer 222 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), polyimide, and/or a combination thereof. In some other embodiments, theinterlayer dielectric layer 222 includes low-K dielectric materials. Examples of low-K dielectric materials include BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SILK® (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF), and/or a combination thereof. It is understood that theinterlayer dielectric layer 222 may include one or more dielectric materials and/or one or more dielectric layers. - In some embodiments, the
interlayer dielectric layer 222 is formed to a suitable thickness by flowable CVD (FCVD), CVD, high density plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods. Specifically, an interlayer dielectric material layer (not illustrated) is formed to cover theinsulators 210 a and thedummy gate stack 216 first. Subsequently, the thickness of the interlayer dielectric material layer is reduced until a top surface of thedummy gate stack 216 is exposed, so as to form theinterlayer dielectric layer 222. The process of reducing the thickness of the interlayer dielectric material layer is achieved by a chemical mechanical polishing (CMP) process, an etching process, or other suitable process. The disclosure is not limited thereto. -
FIG. 12A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 12B is a sectional view illustrating the semiconductor device ofFIG. 12A taken along the line D-D′. In step S24 inFIG. 1 and as shown inFIG. 12A andFIG. 12B , agate stack 224 is formed by replacing thedummy gate stack 216 with thegate stack 224. In some embodiments, thepolysilicon strip 216A and thehard mask strip 216B located on thechannel region 208A of thesemiconductor fins 208 are removed. In one embodiment, the polysilicon strips 216A and the hard mask strips 216B are removed by anisotropic etching, whereas thespacer structures 218, theliner structure 212 and thedielectric layer 214 are retained. After removing thedummy gate stack 216, agate stack 224 is formed over thechannel region 208A of thesemiconductor fins 208, and over theliner structure 212 and on thedielectric layer 214. - As illustrated in
FIG. 12A andFIG. 12B , thegate stack 224 includes agate dielectric layer 224A and agate electrode layer 224B, and thegate stack 224 is located in between thespacer structures 218. In an embodiment, thegate dielectric layer 224A is formed within the recesses between thespacer structures 218 and on thedielectric layer 214, and over thechannel regions 208A of thesemiconductor fins 208. In some embodiments, thegate dielectric layer 224A is conformally formed on thedielectric layer 214 and over theliner structure 212. In some embodiments, a thickness of thegate dielectric layer 224A is maintained to be the same along thebase portions 212C, thesidewall portions 212B and thecap portion 212A of theliner structure 212. - In some embodiments, the material of the
gate dielectric layer 224A includes silicon oxide, silicon nitride or the combination thereof. In some embodiments, thegate dielectric layer 224A includes a high-k dielectric material, and the high-k dielectric material has a k value greater than about 3.9 and includes a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof. In some embodiments, thegate dielectric layer 224A is formed by atomic layered deposition, molecular beam deposition (MBD), physical vapor deposition (PVD) or thermal oxidation. After forming thegate dielectric layer 224A, thegate electrode layer 224B is formed on thegate dielectric layer 224A, over thechannel region 208A of thesemiconductor fins 208 and fills the remaining recesses between thespacer structures 218. In certain embodiments, thegate dielectric layer 224A is formed in between thegate electrode layer 224B and thedielectric layer 214. - In some embodiments, the
gate electrode layer 224B includes a metal-containing material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof. Depending on whether the semiconductor device is a p-type FinFET or an n-type FinFET, the materials of thegate dielectric layer 224A and/or thegate electrode layer 224B are appropriately chosen. Optionally, a chemical mechanical polishing (CMP) process is performed to remove the excess portions of gatedielectric layer 224A and thegate electrode layer 224B. Thespacer structures 218 are located on sidewalls of thegate dielectric layer 224A and thegate electrode layer 224B. In other words, thedummy gate stack 216 is replaced, and thegate stack 224 is formed. In some embodiments described herein, thegate stack 216 is a replacement metal gate, but the structure(s) of the gate stack(s) or the fabrication processes thereof are not limited by these embodiments. Up to here, a semiconductor device SM1 according to some embodiments of the present disclosure is accomplished. -
FIG. 13 toFIG. 16B are perspective and sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown inFIG. 13 toFIG. 16B is similar to the embodiment shown inFIG. 2 toFIG. 12B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is that thedielectric layer 214 is omitted. - In the exemplary embodiment, the same steps described in
FIG. 2 toFIG. 6B may be performed to form theliner structure 212 over theinsulators 210 a and across thesemiconductor fins 208. Referring toFIG. 13 , after forming theliner structure 212, adummy gate stack 216 is formed on theliner structure 212 and across thesemiconductor fins 208. For example, thedummy gate stack 216 covers thechannel region 208A of thesemiconductor fins 208. Furthermore,spacer structures 218 are formed over theliner structure 212 on two opposite sides of thedummy gate stack 216. - Referring to
FIG. 14 , in a next step, theliner structure 212 is patterned so that side surfaces 212SD of theliner structure 212 are aligned with side surfaces of thespacer structure 218. In some embodiments, portions of theliner structure 212 not covered by thedummy gate stack 216 and thespacer structures 218 are removed. In certain embodiments, theliner structure 212 may be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes. - Referring to
FIG. 15 , the same steps may be performed to formstrained material portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby thestrained material portions 220 covers and contacts thesemiconductor fins 208. Similarly, aninterlayer dielectric layer 222 is formed on theinsulators 210 a and covering thestrained material portions 220. -
FIG. 16A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 16B is a sectional view illustrating the semiconductor device ofFIG. 16A taken along the line E-E′. Referring toFIG. 16A andFIG. 16B , after forming theinterlayer dielectric layer 222, thedummy gate stack 216 may be removed and replaced withgate stack 224. As such, a semiconductor device SM2 according to some other embodiments of the present disclosure is accomplished. Referring toFIG. 16A andFIG. 16B , on thechannel region 208A (seeFIG. 5 ) of thesemiconductor fins 208, theliner structure 212 still includes thecap portion 212A,sidewall portions 212B and thebase portions 212C. For example, theliner structure 212 is sandwiched in between thesemiconductor fins 208 and thegate dielectric layer 224A. -
FIG. 17 toFIG. 21B are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown inFIG. 13 toFIGS. 16 is similar to the embodiment shown inFIG. 2 toFIG. 12B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the material of thesemiconductor fins 208. - Referring to
FIG. 17 , the same steps described inFIG. 2 toFIG. 5 may be performed to form thesemiconductor fins 208, andinsulators 210 a in between thesemiconductor fins 208. In the previous embodiments, thesemiconductor fins 208 may be silicon fins, for example. However, the disclosure is not limited thereto, and inFIG. 17 toFIG. 21B , thesemiconductor fins 208 are silicon-germanium (SiGe) fins, for example. In the exemplary embodiment, when thesemiconductor fins 208 are silicon germanium fins, anadditional capping layer 211 may be formed to cover thesemiconductor fins 208. In some embodiments, thecapping layer 211 may be a silicon capping layer. In some embodiments, thecapping layer 211 is formed over thesemiconductor fins 208 by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, thecapping layer 211 covers thetop surfaces 208T and sidewalls 208SD of thesemiconductor fins 208. In some embodiments, the capping layer 211 (silicon capping layer) is used to prevent the oxidation on thesemiconductor fins 208 during the formation of theliner structure 212 performed in a subsequent step. In certain embodiments, thecapping layer 211 prevents the formation of silicon germanium oxide (SiGeOx), which may affect the mobility of the semiconductor device. - Referring to
FIG. 18 , after forming thecapping layer 211, the same steps described inFIG. 6A toFIG. 8 may be performed to form theliner structure 212 over thecapping layer 211, and to form thedielectric layer 214 over theliner structure 212. Thereafter, adummy gate stack 216 andspacer structures 218 are formed on thedielectric layer 214, whereby thedummy gate stack 216 is located in between thespacer structures 218. -
FIG. 19A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 19B is a sectional view illustrating the semiconductor device ofFIG. 19A taken along the line F-F′. Referring toFIG. 19A andFIG. 19B , after forming thedummy gate stack 216 and thespacer structures 218, thedielectric layer 214 is patterned so that side surfaces 214SD of thedielectric layer 214 are aligned with side surfaces of thespacer structure 218. Similarly, portions of theliner structure 212 located on the source/drain regions 208B (seeFIG. 5 ) of thesemiconductor fins 208 may be patterned and removed along with thedielectric layer 214. - Referring to
FIG. 19A andFIG. 19B , on thechannel region 208A (seeFIG. 5 ) of thesemiconductor fins 208, theliner structure 212 still includes thecap portion 212A,sidewall portions 212B and thebase portions 212C. Furthermore, in some embodiments, thecapping layer 211 may be retained on the source/drain regions 208B (seeFIG. 5 ) of thesemiconductor fins 208. However, the disclosure is not limited thereto. For example, in some alternative embodiments, thecapping layer 211 on the source/drain regions 208B may be removed to reveal thesemiconductor fins 208 before forming thestrained material portions 220. As illustrated inFIG. 19A andFIG. 19B , in some embodiments, thecapping layer 211 is sandwiched in between theliner structure 212 and thechannel region 208A of thesemiconductor fins 208. In certain embodiments, theliner structure 212 is sandwiched in between thecapping layer 211 and thedielectric layer 214. - Referring to
FIG. 20 , the same steps may be performed to formstrained material portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby thestrained material portions 220 covers and contacts the capping layer 211 (silicon capping layer). Similarly, aninterlayer dielectric layer 222 is formed on theinsulators 210 a and covering thestrained material portions 220. -
FIG. 21A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.FIG. 21B is a sectional view illustrating the semiconductor device ofFIG. 21A taken along the line G-G′. Referring toFIG. 21A andFIG. 21B , after forming theinterlayer dielectric layer 222, thedummy gate stack 216 may be removed and replaced withgate stack 224. As such, a semiconductor device SM3 according to some other embodiments of the present disclosure is accomplished. Referring toFIG. 21A andFIG. 21B , on thechannel region 208A (seeFIG. 5 ) of thesemiconductor fins 208, theliner structure 212 still includes thecap portion 212A,sidewall portions 212B and thebase portions 212C. For example, theliner structure 212 is located in between thecapping layer 211 and thegate stack 224. In certain embodiments, theliner structure 212 is sandwiched in between thecapping layer 211 and thedielectric layer 214. -
FIG. 22 toFIG. 25 are the perspective views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown inFIG. 22 toFIG. 25 is similar to the embodiment shown inFIG. 2 toFIG. 12B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the way of patterning theliner structure 212. -
FIG. 22 is a stage of manufacturing a semiconductor device similar to that described inFIG. 8 , whereby adummy gate stack 216 andspacer structures 218 are formed on thedielectric layer 214. Referring toFIG. 23 , after forming thedummy gate stack 216 and thespacer structures 218, thedielectric layer 214 is patterned so that side surfaces 214SD of thedielectric layer 214 are aligned with side surfaces of thespacer structure 218. In some embodiments, portions of theliner structure 212 located on the source/drain regions 208B (seeFIG. 5 ) of thesemiconductor fins 208 may be patterned and removed along with thedielectric layer 214. For example, after the patterning process, theliner structure 212 includes thecap portion 212A located on the source/drain regions 208B of thesemiconductor fins 208, whereas the sidewall portions and thebase portions 212C are removed. In certain embodiments, sidewalls of thefins 208 are also revealed after the patterning process. In some embodiments, through the patterning or etching processes, a thickness of thecap portion 212A on the source/drain regions 208B is also reduced. In the exemplary embodiment, since thecap portion 212A initially has a thickness greater than that of thesidewall portions 212B and thebase portions 212C, thecap portion 212A may be retained on thesemiconductor fins 208 after the patterning/etching processes. - Referring to
FIG. 23 , the same steps may be performed to formstrained material portions 220 on the source/drain regions 208B of thesemiconductor fins 208, whereby thecap portion 212A may be covered by thestrained material portions 220. In certain embodiments, thecap portion 212A of theliner structure 212 is disposed over the source/drain regions 208B of thesemiconductor fins 208 and sandwiched in between thestrained material portions 220 and thesemiconductor fin 208. Similarly, aninterlayer dielectric layer 222 is formed on theinsulators 210 a and covering thestrained material portions 220. Referring toFIG. 25 , after forming theinterlayer dielectric layer 222, thedummy gate stack 216 may be removed and replaced withgate stack 224. As such, a semiconductor device SM4 according to some other embodiments of the present disclosure is accomplished. -
FIG. 26 toFIG. 29 are the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown inFIG. 26 toFIG. 29 is similar to the embodiment shown inFIG. 2 toFIG. 12B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the design of thesemiconductor fins 208. -
FIG. 26 is a stage of manufacturing a semiconductor device similar to that described inFIG. 9A , whereby theliner structure 212 and thedielectric layer 214 are pattered so that their side surfaces (212SD / 214SD) may be aligned with side surfaces of thespacer structure 218. Referring toFIG. 27 , after patterning theliner structure 212 and thedielectric layer 214, thesemiconductor fins 208 exposed by thedummy gate stack 216 and thespacer structures 218 are removed/recessed to form a plurality of recessed portions Rc. For example, portions of thesemiconductor fins 208 may be removed by, anisotropic etching, isotropic etching, or a combination thereof. In some embodiments, portions of thesemiconductor fins 208 are recessed below the top surfaces of theinsulators 210 a. In some embodiments, a depth of the recessed portions Rc is less than a thickness of theinsulators 210 a. In other words, thesemiconductor fins 208 exposed by thedummy gate stack 216 and thespacer structures 218 are not entirely removed, and the remainingsemiconductor fins 208 located in the recessed portion Rc form the source/drain regions of thesemiconductor fins 208. - Referring to
FIG. 28 , in a next step,strained material portions 220 may be formed over the recessed portions Rc of thesemiconductor fins 208. In some embodiments, thestrained material portions 220 extends beyond the top surfaces of theinsulators 210 a. Thestrained material portions 220 is similar to that described inFIG. 10 , thus its detailed discussion will be omitted herein. Referring toFIG. 29 , the same steps may be performed to form aninterlayer dielectric layer 222 on theinsulators 210 a and covering thestrained material portions 220. Subsequently, thedummy gate stack 216 may be removed and replaced withgate stack 224. As such, a semiconductor device SM5 according to some other embodiments of the present disclosure is accomplished. -
FIG. 30 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure. The semiconductor device illustrated inFIG. 30 is similar to the semiconductor device SM1 illustrated inFIG. 12B , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the design of theliner structure 212. - In the previous embodiments, the
liner structure 212 is formed with acap portion 212A having a substantially planar top surface. However, the disclosure is not limited thereto. Referring toFIG. 30 , thecap portion 212A of theliner structure 212 has a curved top surface. In the exemplary embodiment, a tip of thecap portion 212A has the maximum thickness T1, while a side of thecap portion 212A joined with thefirst sidewall portion 212B-1 has thickness T13, and another side of thecap portion 212A joined with thesecond sidewall portion 212B-2 has thickness T12. The thicknesses T12 and T13 being smaller than the thickness T1. In other words, a thickness of theliner structure 212 increases from thefirst sidewall portion 212B-1 to thecap portion 212A and decreases from thecap portion 212A to thesecond sidewall portion 212B-2. -
FIG. 31 is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure. The semiconductor device illustrated inFIG. 31 is similar to the semiconductor device SM1 illustrated inFIG. 12B and similar to the semiconductor device illustrate inFIG. 30 , hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the design of theliner structure 212. - In the previous embodiments, the
liner structure 212 is formed withsidewall portions 212B having substantially the same thickness along the sidewalls of thesemiconductor fins 208. However, the disclosure is not limited thereto. Referring toFIG. 22 , besides having acap portion 212A with the curved top surface, a side of thefirst sidewall portion 212B-1 and thesecond sidewall portion 212B-2 joined with thebase portions 212C has a thickness T21, and another side of thefirst sidewall portion 212B-1 and thesecond sidewall portion 212B-2 joined with thecap portion 212A has a thickness T23. The thickness T21 being smaller than the thickness T2, while the thickness T23 is greater than the thickness T2. In other words, in the exemplary embodiment, a thickness of theliner structure 212 gradually increases from thebase portion 212C to thefirst sidewall portion 212B-1 and to thecap portion 212A, and gradually decreases from thecap portion 212A to thesecond sidewall portion 212B-2 and to thebase portion 212C. - In the above-mentioned embodiments, since the morphology of the liner structure is modified to include a cap portion with greater thickness, the liner structure may act to prevent over-etching on the semiconductor fins or the formation of pits on the semiconductor fins. Furthermore, in situations where the semiconductor fins need to be further recessed, over-etching of the semiconductor fins or uneven etching of the semiconductor fins may be prevented when forming the recess. In other words, the strained material portion may be formed over the semiconductor fins having more smooth and planar surfaces due to liner structure protection. Overall, a semiconductor device having less defects and improved performance may be achieved.
- In accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
- In accordance with some other embodiments of the present disclosure, a semiconductor device includes a substrate, insulators, a liner structure, a gate stack and strained material portions. The substrate includes at least one fin, wherein the fin comprises a channel region and source/drain regions. The insulators are disposed on the substrate and located on two sides of the fin. The liner structure is disposed on the insulators and over the channel region of the fin, wherein the liner structure comprises a first sidewall portion, a second sidewall portion and a cap portion, the first sidewall portion and the second sidewall portion are covering sidewalls of the fin, the cap portion is covering a top surface of the fin and joining the first sidewall portion to the second sidewall portion, and a thickness of the liner structure increases from the first sidewall portion to the cap portion and decreases from the cap portion to the second sidewall portion. The gate stack is disposed on the liner structure and across the channel region of the fin. The strained material portions are disposed on the source/drain regions of the fin.
- In accordance with yet another embodiment of the present disclosure, a method of fabricating a semiconductor device is described. The method includes the following steps. A substrate is provided. The substrate is patterned to form trenches in the substrate and fins between the trenches. A plurality of insulators is formed in the trenches of the substrate. A liner structure is formed on the plurality of insulators and across the fin. The liner structure is formed by performing a deposition process and a plasma treatment process. The deposition process is performed by introducing a plurality of precursors over a surface of the plurality of insulators and on the fins to form a liner layer. The plasma treatment process is performed on the liner layer to form the liner structure, wherein after the plasma treatment process, the liner structure is formed to include sidewall portions, base portions and a cap portion, the sidewall portions are covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, the base portions are covering the plurality of insulators and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. A gate stack is formed on the liner structure and across the fins.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A structure, comprising:
a plurality of semiconductor fins;
a liner structure disposed on the plurality of semiconductor fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the plurality of semiconductor fins, and the cap portion is covering a top surface of the plurality of semiconductor fins and joined with the sidewall portions;
a dielectric layer conformally covering the liner structure and across the plurality of semiconductor fins; and
a gate dielectric layer disposed on the dielectric layer and a gate electrode layer disposed on the gate dielectric layer.
2. The structure according to claim 1 , wherein a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions.
3. The structure according to claim 1 , further comprising spacer structures located on two sides of the gate dielectric layer, wherein side surfaces of the spacer structures are aligned with side surfaces of the dielectric layer.
4. The structure according to claim 3 , further comprising an interlayer dielectric layer covering the side surfaces of the spacer structures and the side surfaces of the dielectric layer.
5. The structure according to claim 4 , wherein a top surface of the interlayer dielectric layer is aligned with a top surface of the gate dielectric layer and a top surface of the gate electrode layer.
6. The structure according to claim 1 , further comprising a capping layer disposed in between the plurality of semiconductor fins and the liner structure, wherein the capping layer is in direct contact with the plurality of semiconductor fins.
7. The structure according to claim 1 , wherein a thickness of the dielectric layer is maintained to be the same along the sidewall portions and the cap portion of the liner structure.
8. A structure, comprising:
a substrate comprising at least one fin, wherein the fin comprises a first region and a second region;
a liner structure disposed on the first region of the fin;
a dielectric layer disposed on the first region of the fin over the liner structure;
a gate stack disposed on the first region of the fin over the dielectric layer;
strained material portions disposed on the second region of the fin; and
an interlayer dielectric layer disposed over the substrate and covering the strained material portions, wherein the interlayer dielectric layer is contacting side surfaces of the liner structure and side surfaces of the dielectric layer.
9. The structure according to claim 8 , further comprising a capping layer disposed on the first region and the second region of the fin, wherein the liner structure is located in between the capping layer and the gate stack in the first region, and the strained material portions are covering the capping layer in the second region.
10. The structure according to claim 9 , further comprising insulators disposed on the substrate and located below the liner structure, wherein the insulators are in direct contact with the capping layer and the liner structure.
11. The structure according to claim 8 , wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions are covering sidewalls of the fin, and the cap portion is covering a top surface of the fin and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions.
12. The structure according to claim 11 , wherein the liner structure further includes base portions disposed over the substrate and joined with the sidewall portions, wherein a thickness T3 of the base portions is substantially equal to the thickness T2 of the sidewall portions.
13. The structure according to claim 8 , further comprising spacer structure disposed on two sides of the gate stack, wherein the interlayer dielectric layer is covering side surfaces of the spacer structure.
14. The structure according to claim 13 , wherein the side surfaces of the spacer structure are aligned with the side surfaces of the liner structure and the side surfaces of the dielectric layer.
15. A structure, comprising:
a substrate comprising semiconductor fins, wherein the semiconductor fins include a top surface and side surfaces joined with the top surface;
a liner structure, a first dielectric layer, a second dielectric layer and a gate electrode sequentially disposed on the semiconductor fins covering the top surface and the side surfaces of the semiconductor fins, wherein a thickness of the liner structure on the top surface of the semiconductor fins is greater than a thickness of the first dielectric layer and a thickness of the second dielectric layer on the top surface of the semiconductor fins.
16. The structure according to claim 15 , wherein a thickness of the liner structure on the side surfaces of the semiconductor fins is smaller than the thickness of the liner structure on the top surface of the semiconductor fins.
17. The structure according to claim 15 , wherein a thickness of the first dielectric layer on the side surfaces of the semiconductor fins is equal to the thickness of the first dielectric layer on the top surface of the semiconductor fins.
18. The structure according to claim 15 , further comprising a capping layer covering the semiconductor fins and located underneath the liner structure.
19. The structure according to claim 18 , wherein a bottom surface of the capping layer is aligned with a bottom surface of the liner structure.
20. The structure according to claim 18 , further comprising insulators disposed on the substrate and located underneath the capping layer and the liner structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US18/083,576 US20230124471A1 (en) | 2020-07-30 | 2022-12-19 | Finfet having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US16/942,781 US11532718B2 (en) | 2020-07-30 | 2020-07-30 | FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins |
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US20210257462A1 (en) * | 2020-02-19 | 2021-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors |
US11437496B2 (en) * | 2020-10-16 | 2022-09-06 | Texas Instruments Incorporated | Uniform implant regions in a semiconductor ridge of a FinFET |
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US8729627B2 (en) * | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8815712B2 (en) | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US8860148B2 (en) | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8823065B2 (en) | 2012-11-08 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8772109B2 (en) | 2012-10-24 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for forming semiconductor contacts |
US9236300B2 (en) | 2012-11-30 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs in SRAM cells and the method of forming the same |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
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US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US10181426B1 (en) * | 2017-08-30 | 2019-01-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch profile control of polysilicon structures of semiconductor devices |
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