JP4768399B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4768399B2 JP4768399B2 JP2005317627A JP2005317627A JP4768399B2 JP 4768399 B2 JP4768399 B2 JP 4768399B2 JP 2005317627 A JP2005317627 A JP 2005317627A JP 2005317627 A JP2005317627 A JP 2005317627A JP 4768399 B2 JP4768399 B2 JP 4768399B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- source
- drain
- contact
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 56
- 239000000758 substrate Substances 0.000 claims description 23
- 239000010410 layer Substances 0.000 description 28
- 238000009792 diffusion process Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
12 素子分離領域
14 p型ウェル領域
16 ゲート絶縁膜
18 ゲート電極
20 サイドウォール
22 n型ソース/ドレイン低濃度拡散層
24 n型ソース/ドレイン高濃度拡散層
25 シリサイド
26 tensile膜
28 TEOS膜
30 コンタクト
32 ソースコンタクト
34 ドレインコンタクト
36 n型ウェル領域
38 p型ソース/ドレイン低濃度拡散層
40 p型ソース/ドレイン高濃度拡散層
42 compressive膜
50 SRAMセル
52 トランスファトランジスタ(NMOSトランジスタ)
54 ドライバトランジスタ(NMOSトランジスタ)
56 ロードトランジスタ(PMOSトランジスタ)
Claims (2)
- 半導体基板上に第1のゲート電極が形成され、前記第1のゲート電極の両側方の前記半導体基板にn型の第1のソース/ドレイン層が形成される第1のトランジスタと、前記半導体基板上に第2のゲート電極が形成され、前記第2のゲート電極の両側方の前記半導体基板にp型の第2のソース/ドレイン層が形成される第2のトランジスタと、前記第1のトランジスタ及び前記第2のトランジスタ上に形成される、前記第1のゲート電極若しくは前記第2のゲート電極下部のチャネル領域に引張応力を与える絶縁膜と、前記第1のソース/ドレイン層上に前記絶縁膜を貫通して形成される第1のソースコンタクト及び第1のドレインコンタクトと、前記第2のソース/ドレイン層上に前記絶縁膜を貫通して形成される第2のソースコンタクト及び第2のドレインコンタクトと、を備え、前記第1のゲート電極と前記第1のソースコンタクトとの間の距離が、前記第1のゲート電極と前記第1のドレインコンタクトとの間の距離よりも広く、前記第2のゲート電極と前記第2のソースコンタクトとの間の距離が、前記第2のゲート電極と前記第2のドレインコンタクトとの間の距離よりも狭いことを特徴とする半導体装置。
- 半導体基板上に第1のゲート電極が形成され、前記第1のゲート電極の両側方の前記半導体基板にp型の第1のソース/ドレイン層が形成される第1のトランジスタと、前記半導体基板上に第2のゲート電極が形成され、前記第2のゲート電極の両側方の前記半導体基板にn型の第2のソース/ドレイン層が形成される第2のトランジスタと、前記第1のトランジスタ及び前記第2のトランジスタ上に形成される、前記第1のゲート電極若しくは前記第2のゲート電極下部のチャネル領域に圧縮応力を与える絶縁膜と、前記第1のソース/ドレイン層上に前記絶縁膜を貫通して形成される第1のソースコンタクト及び第1のドレインコンタクトと、前記第2のソース/ドレイン層上に前記絶縁膜を貫通して形成される第2のソースコンタクト及び第2のドレインコンタクトと、
を備え、前記第1のゲート電極と前記第1のソースコンタクトとの間の距離が、前記第1のゲート電極と前記第1のドレインコンタクトとの間の距離よりも広く、前記第2のゲート電極と前記第2のソースコンタクトとの間の距離が、前記第2のゲート電極と前記第2のドレインコンタクトとの間の距離よりも狭いことを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005317627A JP4768399B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体装置 |
US11/590,060 US20070102726A1 (en) | 2005-10-31 | 2006-10-31 | Semiconductor device for improving channel mobility |
US12/704,677 US20100164010A1 (en) | 2005-10-31 | 2010-02-12 | Semiconductor device for improving channel mobility |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005317627A JP4768399B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007123784A JP2007123784A (ja) | 2007-05-17 |
JP4768399B2 true JP4768399B2 (ja) | 2011-09-07 |
Family
ID=38002861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005317627A Expired - Fee Related JP4768399B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070102726A1 (ja) |
JP (1) | JP4768399B2 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080293194A1 (en) * | 2007-05-24 | 2008-11-27 | Neng-Kuo Chen | Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor |
JP5369406B2 (ja) * | 2007-08-29 | 2013-12-18 | 日本電気株式会社 | 半導体装置 |
JP2009111217A (ja) * | 2007-10-31 | 2009-05-21 | Toshiba Corp | 半導体装置 |
JP2010087420A (ja) * | 2008-10-02 | 2010-04-15 | Renesas Technology Corp | 半導体装置およびフォトマスク |
US8120116B2 (en) | 2007-12-28 | 2012-02-21 | Renesas Electronics Corporation | Semiconductor device and photomask |
JP5272203B2 (ja) * | 2007-12-28 | 2013-08-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびフォトマスク |
KR20100053311A (ko) * | 2008-11-12 | 2010-05-20 | 삼성전자주식회사 | 트랜지스터 어레이의 전기적 특성변화를 보상할 수 있는 반도체 장치 |
JP5159828B2 (ja) * | 2010-05-21 | 2013-03-13 | パナソニック株式会社 | 半導体装置 |
CN102487015A (zh) * | 2010-12-03 | 2012-06-06 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US9397217B2 (en) * | 2012-12-28 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of non-planar semiconductor device |
CN104183492A (zh) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | 应力结构的形成方法 |
US9536946B2 (en) * | 2014-08-25 | 2017-01-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
CN112310190A (zh) * | 2019-07-30 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN116546811B (zh) * | 2023-06-27 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | 一种半导体集成器件及其制作方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121663A (en) * | 1997-05-22 | 2000-09-19 | Advanced Micro Devices, Inc. | Local interconnects for improved alignment tolerance and size reduction |
JP4368014B2 (ja) * | 1999-10-06 | 2009-11-18 | 新日本無線株式会社 | シュミット回路 |
JP2005057301A (ja) * | 2000-12-08 | 2005-03-03 | Renesas Technology Corp | 半導体装置及びその製造方法 |
TW503586B (en) * | 2001-10-29 | 2002-09-21 | Macronix Int Co Ltd | MOSFET structure with low junction capacitance |
KR100500451B1 (ko) * | 2003-06-16 | 2005-07-12 | 삼성전자주식회사 | 인장된 채널을 갖는 모스 트랜지스터를 구비하는반도체소자의 제조 방법 |
JP4557508B2 (ja) * | 2003-06-16 | 2010-10-06 | パナソニック株式会社 | 半導体装置 |
JP2006156568A (ja) * | 2004-11-26 | 2006-06-15 | Renesas Technology Corp | 半導体装置 |
US7309637B2 (en) * | 2005-12-12 | 2007-12-18 | Chartered Semiconductor Manufacturing, Ltd | Method to enhance device performance with selective stress relief |
US7450413B2 (en) * | 2006-08-11 | 2008-11-11 | International Business Machines Corporation | Configurable SRAM system and method |
-
2005
- 2005-10-31 JP JP2005317627A patent/JP4768399B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-31 US US11/590,060 patent/US20070102726A1/en not_active Abandoned
-
2010
- 2010-02-12 US US12/704,677 patent/US20100164010A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20100164010A1 (en) | 2010-07-01 |
US20070102726A1 (en) | 2007-05-10 |
JP2007123784A (ja) | 2007-05-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4768399B2 (ja) | 半導体装置 | |
US8803234B1 (en) | High voltage semiconductor device and method for fabricating the same | |
JP4417601B2 (ja) | 半導体装置及びその形成方法 | |
US8486788B2 (en) | Semiconductor device and method for fabricating the same | |
US10418480B2 (en) | Semiconductor device capable of high-voltage operation | |
US9390983B1 (en) | Semiconductor device and method for fabricating the same | |
JP2006049628A (ja) | 半導体装置及びその製造方法 | |
US8664055B2 (en) | Fin field-effect transistor structure and manufacturing process thereof | |
US7915688B2 (en) | Semiconductor device with MISFET | |
JP2005064508A (ja) | 高電圧トランジスタおよびその製造方法 | |
US20070278613A1 (en) | Semiconductor device | |
JP2006100790A (ja) | 半導体装置及びその製造方法 | |
US9287261B2 (en) | Semiconductor device and manufacturing method thereof | |
US20070034973A1 (en) | Methods and Apparatus for Operating a Transistor Using a Reverse Body Bias | |
US9679983B2 (en) | Semiconductor devices including threshold voltage control regions | |
WO2009147772A1 (ja) | 半導体装置及びその製造方法 | |
JP4202388B2 (ja) | 半導体装置及びその製造方法 | |
JP5280121B2 (ja) | 半導体装置およびその製造方法 | |
KR20040054468A (ko) | 반도체 장치 | |
US7547606B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2008117801A (ja) | 半導体装置 | |
KR20070069726A (ko) | 트랜지스터 및 그의 형성 방법 | |
JP2005129635A (ja) | Soi半導体集積回路装置及びその製造方法 | |
JPH09186314A (ja) | Mos型電界効果トランジスタ | |
JP2006148151A (ja) | 半導体装置および半導体装置における配線方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080731 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110310 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110311 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110428 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110524 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110616 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140624 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |