JP5448082B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5448082B2 JP5448082B2 JP2010048755A JP2010048755A JP5448082B2 JP 5448082 B2 JP5448082 B2 JP 5448082B2 JP 2010048755 A JP2010048755 A JP 2010048755A JP 2010048755 A JP2010048755 A JP 2010048755A JP 5448082 B2 JP5448082 B2 JP 5448082B2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
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Description
(実施の形態1)
まず本発明の実施の形態1の半導体装置の構成について説明する。
図10および図11(A)〜(D)を参照して、まず半導体基板SBが準備される。半導体基板SBの主表面に酸化シリコン膜(SiO)IL1が形成される。酸化シリコン膜ではなく酸化窒化シリコン膜(SiON)が形成されてもよい。酸化シリコン膜IL1は、たとえば5〜50nm程度の厚さに形成される。酸化シリコン膜IL1上に窒化シリコン膜(SiN)IL2が形成される。窒化シリコン膜IL2は、たとえば50〜200nm程度の厚さに形成される。通常のフォトグラフィにより、その窒化シリコン膜IL2上にフォトレジストパターンPR1が形成される。このフォトレジストパターンPR1をマスクとして酸化シリコン膜IL1および窒化シリコン膜IL2がエッチングされてパターニングされる。この後、フォトレジストパターンPR1は、たとえばアッシングなどにより除去される。
まず、本実施の形態の半導体装置がドレイン電流を増大できる作用効果について説明する。本実施の形態の半導体装置におけるドレイン電流の増加の効果を調べるために、本実施の形態としての図1の半導体装置の構成と、比較例1としての図29(A)の半導体装置の構成および比較例2としての図29(B)の半導体装置の構成とについて検討を行った。それらの結果を図30に示す。
本発明の実施の形態2の半導体装置は、実施の形態1の半導体装置と比較して、溝の構成が主に異なっている。
図36および図37(A)〜(D)を参照して、酸化シリコン膜IL1が形成される。酸化シリコン膜IL1上に窒化シリコン膜IL2が形成される。通常のフォトグラフィにより、その窒化シリコン膜IL2上にフォトレジストパターンPR1が形成される。このフォトレジストパターンPR1をマスクとして酸化シリコン膜IL1および窒化シリコン膜IL2がエッチングされてパターニングされる。パターニングされた酸化シリコン膜IL1および窒化シリコン膜IL2をマスクとして異方性エッチングされることにより半導体基板SBの主表面に第1溝RE1および第2溝RE2となるトレンチが形成される。この後、図12〜図16で説明した実施の形態1と同様に方法により第1溝RE1および第2溝RE2が形成される。
MOSFETは、たとえば自動車の制御部品や光ディスクドライブなどにおいて、数十〜数百ボルトの高い電圧を制御する用途に用いられている。スイッチング素子であるMOSFETは、ゲート電極層GEに加えるバイアス電圧を変化させ、ソース領域SRおよびドレイン領域DR間に電流が流れるOn状態と、電流が流れないOff状態を切り替える。Off状態では、通常高い電圧が印加されるドレイン領域DRから、半導体基板SBやソース領域SRへパンチスルー電流が流れないようにしなければならない。そのため、ゲート電極層GEに加えるバイアス電圧がOffされた際、ドレイン領域DRに加える電圧が徐々に高くされてソース領域SRへパンチスルー電流が流れ始める臨界電圧(Off耐圧)を、デバイスの動作電圧領域より高く設定して、パンチスルー電流が流れないようにデバイスを設計する必要がある。
本発明の実施の形態3の半導体装置は、実施の形態2の半導体装置と比較して、溝の構成が主に異なっている。
本発明の実施の形態4の半導体装置は、実施の形態2の半導体装置と比較して、溝の構成が主に異なっている。
本発明の実施の形態5の半導体装置の製造方法では、実施の形態1と比較して、サイドウォール絶縁膜を形成する際の絶縁膜の残渣が溝に残らない点で主に異なっている。
本発明の実施の形態5の半導体装置の製造方法では、実施の形態1と比較して、サイドウォール絶縁膜を溝を形成する際の絶縁膜の残渣が溝に残らない点で主に異なっている。
また、溝REを有する高耐圧トランジスタHCのゲート電極層GEは、溝REを有さないcore−トランジスタCCのゲート電極層GEより高さが低くなる。たとえば溝REを有する高耐圧トランジスタHCのゲート電極層GEの高さは、溝REを有さないcore−トランジスタCCのゲート電極層GEの高さ3/4〜7/8程度の高さになる。また、溝REを有する高耐圧トランジスタHCの素子分離膜TIは、溝REを有さないcore−トランジスタCCの素子分離膜TIより高さが低くなる。たとえば溝REを有する高耐圧トランジスタHCの素子分離膜TIは、ゲート電極層GEと比較して1/4〜1/2程度の高さが減少する。
本発明の実施の形態7の半導体装置の製造方法では、実施の形態1と比較して、溝が形成された半導体装置のサイドウォール絶縁膜を形成しない点で主に異なっている。
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。
Claims (3)
- 主表面を有する半導体基板と、
前記主表面に互いに間隔をおいて形成されたソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域とに挟まれる前記主表面上に形成されたゲート電極層と、
前記ソース領域の表面に接するように形成された第1導電層と、
前記ドレイン領域の表面に接するように形成された第2導電層とを備え、
前記第1導電層と前記ソース領域との接触領域から前記ゲート電極層の下側を通って前記第2導電層と前記ドレイン領域との接触領域まで延びるように溝が前記主表面に形成されており、
前記ドレイン領域の周囲を覆うように形成され、かつ前記ドレイン領域よりも低い不純物濃度を有し、かつ前記ドレイン領域と同じ導電型のドレイン側低濃度領域と、
前記ソース領域の周囲を覆うように形成され、かつ前記ソース領域よりも低い不純物濃度を有し、かつ前記ソース領域と同じ導電型のソース側低濃度領域とをさらに備え、
前記溝は前記ドレイン側低濃度領域と前記ソース側低濃度領域を通るように形成されている、半導体装置。 - 前記第1導電層および前記第2導電層の各々が前記溝の側壁に接するように構成されている、請求項1に記載の半導体装置。
- 前記溝は複数の溝部を含んでおり、複数の前記溝部のそれぞれは互いに並走するように形成されている、請求項1または2に記載の半導体装置。
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US13/040,610 US8754471B2 (en) | 2010-03-05 | 2011-03-04 | Semiconductor device having gate in recess |
CN201110057407.4A CN102194881B (zh) | 2010-03-05 | 2011-03-04 | 半导体器件及其制造方法 |
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US9397217B2 (en) * | 2012-12-28 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of non-planar semiconductor device |
JP2015050336A (ja) * | 2013-09-02 | 2015-03-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2015082506A (ja) * | 2013-10-21 | 2015-04-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9379236B2 (en) * | 2014-06-04 | 2016-06-28 | Broadcom Corporation | LDMOS device and structure for bulk FinFET technology |
JP6362449B2 (ja) | 2014-07-01 | 2018-07-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
KR101707465B1 (ko) * | 2014-08-25 | 2017-02-20 | 삼성전자주식회사 | 반도체 소자 |
US9536946B2 (en) | 2014-08-25 | 2017-01-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2018125518A (ja) * | 2017-02-03 | 2018-08-09 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ、製造方法 |
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US4835584A (en) * | 1986-11-27 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench transistor |
JPH03129775A (ja) * | 1989-07-11 | 1991-06-03 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH05315613A (ja) * | 1992-05-13 | 1993-11-26 | Oki Electric Ind Co Ltd | 半導体装置およびシリサイド層の形成方法 |
US5539238A (en) * | 1992-09-02 | 1996-07-23 | Texas Instruments Incorporated | Area efficient high voltage Mosfets with vertical resurf drift regions |
JPH07131009A (ja) | 1993-11-04 | 1995-05-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH08264764A (ja) * | 1995-03-22 | 1996-10-11 | Toshiba Corp | 半導体装置 |
JPH0923011A (ja) * | 1995-07-05 | 1997-01-21 | Hitachi Ltd | 半導体装置及びその製造方法 |
US5717239A (en) * | 1995-11-15 | 1998-02-10 | Nec Corporation | MOS transistor with large gate width |
JP4733869B2 (ja) | 2001-07-25 | 2011-07-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006019518A (ja) * | 2004-07-01 | 2006-01-19 | Seiko Instruments Inc | 横型トレンチmosfet |
JP4541902B2 (ja) * | 2005-01-06 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7247887B2 (en) * | 2005-07-01 | 2007-07-24 | Synopsys, Inc. | Segmented channel MOS transistor |
JP5086558B2 (ja) * | 2006-04-04 | 2012-11-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR100908522B1 (ko) * | 2007-06-28 | 2009-07-20 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
JP2009054946A (ja) * | 2007-08-29 | 2009-03-12 | Seiko Instruments Inc | 半導体装置とその製造方法 |
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US8754471B2 (en) | 2014-06-17 |
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