TWI455316B - 高壓多閘極元件及其製造方法 - Google Patents

高壓多閘極元件及其製造方法 Download PDF

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TWI455316B
TWI455316B TW100103418A TW100103418A TWI455316B TW I455316 B TWI455316 B TW I455316B TW 100103418 A TW100103418 A TW 100103418A TW 100103418 A TW100103418 A TW 100103418A TW I455316 B TWI455316 B TW I455316B
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gate
semiconductor fin
high voltage
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TW201232778A (en
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Tsung Yi Huang
Chien Wei Chiu
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Richtek Technology Corp
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Description

高壓多閘極元件及其製造方法
本發明係有關一種高壓多閘極元件及其製造方法。
第1-3圖顯示三種高壓元件的剖面示意圖。請參照第1圖，顯示一種雙擴散金屬氧化半導體(double diffused metal oxide semiconductor,DMOS)元件的剖面示意圖，其結構如下。於P型矽基板11中形成絕緣結構12以定義第一元件區100，絕緣結構12例如為區域氧化(local oxidation of silicon,LOCOS)結構。於基板11上，形成N型井區17；於第一元件區100中，形成形成閘極13、源極14、汲極15、與本體區16。第2圖顯示一種橫向雙擴散金屬氧化半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件的剖面示意圖，其結構如下。於P型矽基板11中形成絕緣結構12以定義第一元件區100與第二元件區200，絕緣結構12例如為LOCOS結構。於基板11上，形成閘極13；於第一元件區100中，形成源極14；於第二元件區200中，形成汲極15；N型漂移區18形成於汲極15外圍，以隔開源極14與汲極15。第3圖顯示一種雙擴散汲極金屬氧化半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件的剖面示意圖，其結構如下。於P型矽基板11中形成絕緣結構12以定義第一元件區100，絕緣結構12例如為LOCOS結構。於第一元件區100中，形成形成閘極13、源極14、汲極15、與N型漂移區18。
以上三種高壓元件，在閘極的控制上，也就是在導通與不導通的元件特性上，需要更好的設計來降低導通阻值並減小漏電流。
有鑑於此，本發明即針對上述先前技術之不足，提出一種高壓多閘極元件及其製造方法，可改善元件的特性，增加元件的應用範圍。
本發明目的在提供一種高壓多閘極元件及其製造方法。
為達上述之目的，本發明提供了一種高壓多閘極元件，包含：一半導體鰭板，其具有第一導電型雜質摻雜；一介電層，覆蓋部分該半導體鰭板側壁；一閘極，覆蓋該介電層；一汲極，形成於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜；一源極，形成於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜，且該源極與汲極位於該閘極之不同側；以及一具有第二導電型雜質摻雜之漂移區或井區，形成於該半導體鰭板中，分隔並耦接於該汲極與閘極之間。
就另一觀點，本發明也提供了一種高壓多閘極元件製造方法，包含：形成一具有第一導電型雜質摻雜之半導體鰭板；形成一介電層，覆蓋部分該半導體鰭板側壁；形成一閘極，覆蓋該介電層；形成一汲極於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜；形成一源極於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜，且該源極與汲極位於該閘極之不同側；以及形成一具有第二導電型雜質摻雜之漂移區或井區於該半導體鰭板中，分隔並分別耦接該汲極與閘極。
上述高壓多閘極元件可為平面型或垂直型元件，亦即其源極與汲極可設置於同一平面或不同平面上。
上述高壓多閘極元件可為對稱或非對稱型元件；在對稱型元件的情況下，該高壓多閘極元件更包含一第二導電型漂移區，形成於該半導體鰭板中，分隔該源極與閘極。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第4A-4F圖，顯示本發明的第一個實施例，第4A圖顯示高壓多閘極DMOS元件之立體示意圖。第4B圖顯示在第4A圖中，AA’剖線的剖視示意圖。請同時參閱第4C-4F圖，顯示高壓多閘極DMOS元件之製造流程。如第4C圖所示，首先提供基板21，基板21例如為SOI(矽絕緣,Silicon On Insulator)基板或矽基板，並於基板21上形成半導體鰭板22，其具有第一導電型雜質摻雜，例如但不限於為P型雜質摻雜。第4D圖顯示於半導體鰭板22中，摻雜第二導電型雜質，例如但不限於為N型雜質，而形成第二導電型井區27。
接下來請參閱第4E圖。於基板21上，形成介電層231與閘極23，介電層231覆蓋部分半導體鰭板22側壁；而閘極23覆蓋介電層231。接下來請參閱第4F圖，藉由微影技術與閘極23的遮罩，並以離子植入技術，將第一導電型雜質，例如但不限於為P型雜質，以加速離子的形式，植入定義的區域內，以形成本體區26。再接下來藉由微影技術與閘極23的遮罩，並以離子植入技術，將第二導電型雜質，例如但不限於為N型雜質，以加速離子的形式，植入定義的區域內，以形成源極24與汲極25。其中，第二導電型井區27分隔並分別耦接汲極25與閘極13，以於元件導通時於其中形成通道；本體區26用以分隔源極24與閘極13，並包覆源極24。如此，就製成了高壓多閘極DMOS元件，其在元件特性上比第1圖所示的傳統元件更佳。
第5A與第5B圖顯示本發明的第二個實施例，第5A圖顯示高壓多閘極LDMOS元件之立體示意圖。第5B圖顯示在第5A圖中，BB’剖線的剖視示意圖。與第一個實施例不同的是，半導體鰭板22中沒有第二導電型井區27，也沒有本體區26；而是在半導體鰭板22中，形成第二導電型漂移區28，分隔源極24與閘極23；以及絕緣結構29，部分或全部於閘極23包覆範圍內。本實施例的高壓多閘極LDMOS元件，其元件特性比第2圖所示的傳統元件更佳。
第6A與第6B圖顯示本發明的第三個實施例，本實施例與第二個實施例相似，但應用本發明於高壓多閘極DDDMOS元件中。第6A圖顯示高壓多閘極DDDMOS元件之立體示意圖。第6B圖顯示在第6A圖中，CC’剖線的剖視示意圖。與第二個實施例不同的是，半導體鰭板22中沒有絕緣結構29，但與第二個實施例一樣，都具有第二導電型漂移區28。
第7A與第7B圖顯示本發明的第四個實施例，本實施例與第三個實施例相似，但應用本發明於對稱高壓多閘極DDDMOS元件中。第7A圖顯示對稱高壓多閘極DDDMOS元件之立體示意圖。第7B圖顯示在第7A圖中，DD’剖線的剖視示意圖。與第三個實施例不同的是，半導體鰭板22中多了一個第二導電型漂移區28，分隔並分別耦接源極24與閘極23。
第8A與第8B圖顯示本發明的第五個實施例，本實施例與第三個實施例相似，但應用本發明於平面高壓雙閘極DDDMOS元件中。第8A圖顯示平面高壓雙閘極DDDMOS元件之立體示意圖。第8B圖顯示在第8A圖中，EE’剖線的剖視示意圖。與第三個實施例不同的是，閘極23在半導體鰭板22的上下方形成兩閘極板232與233，而非如第三個實施例中，主要為半導體鰭板22前後的閘極板。另外，半導體鰭板22與基板21間，形成基板31以支撐半導體鰭板22。
第9A與第9B圖顯示本發明的第六個實施例，本實施例與第三個實施例相似，但應用本發明於垂直高壓雙閘極DDDMOS元件中。第9A圖顯示垂直高壓雙閘極DDDMOS元件之立體示意圖。第9B圖顯示在第9A圖中，FF’剖線的剖視示意圖。與第三個實施例不同，本實施例之源極24與汲極25如圖所示不在同一平面上，並且閘極23在半導體鰭板22的上下方形成兩閘極板232與233，而非如第三個實施例中，主要為半導體鰭板22前後的閘極板。
以上第三至六實施例之DDDMOS元件，其元件特性比第3圖所示的傳統元件更佳。
第10A與第10B圖顯示本發明的第七個實施例。第10A圖顯示高壓多閘極DMOS元件之立體示意圖。第10B圖顯示在第10A圖中，GG’剖線的剖視示意圖。本實施例與第一個實施例相似，不同的是，此DMOS元件之源極24與汲極25不在半導體鰭板22中，而是與半導體鰭板22連接。
第11圖顯示本發明的第八個實施例。與第七個實施例不同的是，此DMOS元件中之閘極23包含複數個分開的閘極板，例如但不限於如第11圖所示之兩個閘極板234與235。本實施例旨在說明在高壓多閘極元件結構中，閘極23包含複數個分開的閘極板，並可以分開控制。
以上第七至八實施例之DMOS元件，其元件特性比第1圖所示的傳統元件更佳。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，本發明亦可以應用於其他多閘極元件結構，例如具有圓筒狀結構之閘極等。本發明的範圍應涵蓋上述及其他所有等效變化。
11．．．基板
12．．．絕緣結構
13．．．閘極
14．．．源極
15．．．汲極
16．．．本體區
17．．．N型井區
18．．．漂移區
21．．．第一基板
22．．．半導體鰭板
23．．．閘極
231．．．介電層
232,233．．．閘極板
234,235．．．閘極板
24．．．源極
25．．．汲極
26．．．本體區
27．．．第二導電型井區
28．．．漂移區
100．．．第一元件區
200．．．第二元件區
第1-3圖顯示三種高壓元件的剖面示意圖。
第4A-4F圖，顯示本發明的第一個實施例。
第5A與第5B圖顯示本發明的第二個實施例。
第6A與第6B圖顯示本發明的第三個實施例。
第7A與第7B圖顯示本發明的第四個實施例。
第8A與第8B圖顯示本發明的第五個實施例。
第9A與第9B圖顯示本發明的第六個實施例。
第10A與第10B圖顯示本發明的第七個實施例。
第11圖顯示本發明的第八個實施例。
21．．．第一基板
22．．．半導體鰭板
23．．．閘極
231．．．介電層
24．．．源極
25．．．汲極
26．．．本體區
27．．．第二導電型井區

Claims (10)

  1. 一種高壓多閘極元件，包含：一半導體鰭板，其具有第一導電型雜質摻雜；一介電層，覆蓋部分該半導體鰭板側壁；一閘極，覆蓋該介電層；一汲極，形成於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜；一源極，形成於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜，且該源極與汲極位於該閘極之不同側；一本體區，具有第一導電型雜質摻雜，分隔該源極與該閘極，並包覆該源極；以及一具有第二導電型雜質摻雜之漂移區或井區，形成於該半導體鰭板中，分隔並耦接於該汲極與閘極之間。
  2. 如申請專利範圍第1項所述之高壓多閘極元件，其中該閘極包括複數個分開之閘極板。
  3. 如申請專利範圍第1項所述之高壓多閘極元件，更包含一絕緣結構，形成於該半導體鰭板中，部分或全部於該閘極包覆範圍內。
  4. 如申請專利範圍第1項所述之高壓多閘極元件，更包含一第二導電型漂移區，形成於該半導體鰭板中，分隔該源極與閘極。
  5. 如申請專利範圍第1項所述之高壓多閘極元件，其中該源極與汲極設置於同一平面或不同平面上。
  6. 一種高壓多閘極元件製造方法，包含：形成一具有第一導電型雜質摻雜之半導體鰭板； 形成一介電層，覆蓋部分該半導體鰭板側壁；形成一閘極，覆蓋該介電層；形成一汲極於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜；形成一源極於該半導體鰭板中或與該半導體鰭板耦接，其具有第二導電型雜質摻雜，且該源極與汲極位於該閘極之不同側；形成一本體區，具有第一導電型雜質摻雜，分隔該源極與該閘極，並包覆該源極；以及形成一具有第二導電型雜質摻雜之漂移區或井區於該半導體鰭板中，分隔並分別耦接該汲極與閘極。
  7. 如申請專利範圍第6項所述之高壓多閘極元件製造方法，其中該閘極包括複數個分開之閘極板。
  8. 如申請專利範圍第6項所述之高壓多閘極元件製造方法，更包含形成一絕緣結構於該半導體鰭板中，部分或全部於該閘極包覆範圍內。
  9. 如申請專利範圍第6項所述之高壓多閘極元件製造方法，更包含形成一第二導電型漂移區於該半導體鰭板中，分隔該源極與閘極。
  10. 如申請專利範圍第6項所述之高壓多閘極元件製造方法，其中該源極與汲極設置於同一平面或不同平面上。
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