KR102303060B1 - 웨이퍼 지지 디바이스 및 그 제조 방법 그리고 반도체 가공 장치 - Google Patents

웨이퍼 지지 디바이스 및 그 제조 방법 그리고 반도체 가공 장치 Download PDF

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KR102303060B1
KR102303060B1 KR1020190044213A KR20190044213A KR102303060B1 KR 102303060 B1 KR102303060 B1 KR 102303060B1 KR 1020190044213 A KR1020190044213 A KR 1020190044213A KR 20190044213 A KR20190044213 A KR 20190044213A KR 102303060 B1 KR102303060 B1 KR 102303060B1
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쇼지 푸미타카
쿠다 히데아키
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에이에스엠 저펜 가부시기가이샤
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Abstract

반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스는 베이스면; 및 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖는 돌출부을 포함한다. 라운드팁은 웨이퍼의 이면측이 점접촉을 통해 라운드팁에 의해 전체적으로 지지되도록 되어 있다. 돌출부는 웨이퍼가 놓이는 베이스면의 영역상에 실질적으로 균일하게 배치되고, 용도에 정해진 대로 돌출부의 수(N) 및 높이(H [㎛])는 300 mm 웨이퍼에 대한 면적마다 다음의 부등식들, (-0.5N + 40)≤H≤53; 5≤N≤100을 만족한다.

Description

웨이퍼 지지 디바이스 및 그 제조 방법 그리고 반도체 가공 장치{WAFER SUPPORTING DEVICE AND MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR-PROCESSING APPARATUS}
본 발명은 반도체 가공 챔버 내에 장착된 웨이퍼 지지 디바이스에 관한 것으로서, 특히 디바이스상에 웨이퍼를 지지하기 위한 돌출부을 갖는 웨이퍼 지지 디바이스 및 그 제조 방법과 반도체 가공 장치에 관한 것이다.
하나의 대표적인 종래 서셉터(susceptor)는 도 1a에 도시된 바와 같이 평평한 표면을 갖는다. 웨이퍼 지지 디바이스(1)는 통상적으로 히터를 포함하는 서셉터 베이스에 부착되도록 구성되어 있다. 웨이퍼는 통상적으로 플라즈마 강화 CVD 또는 ALD에 의하여 가공하기 위해 웨이퍼 지지 디바이스상에 배치된다. 도 1a(상단 도면은 평면도이고, 하단 도면은 선 1A-1A를 취한 단면도이다)에 도시된 바와 같이, 웨이퍼 지지 디바이스는 평평한 표면을 갖는다. 그러나, 웨이퍼가 평평한 표면에 놓여 가공될 때, 통상 막 형성 후에 웨이퍼의 이면측(reverse side)에서 입자들의 발생 및 축적이 관찰되고 있다. 또한, 가공 방식에 따라, 종종 웨이퍼의 상단면상에 웨이퍼의 이면측이 부착되는 일이 생긴다. 이러한 문제들을 해결하기 위해서, 종래에는 2가지 방식의 웨이퍼 지지 디바이스가 개발되어 있다. 도 1b(상단 도면은 평면도이고, 하단 도면은 선 1B-1B를 취한 단면도이다)는 연속적 베이스면에 의해 격리된 볼록부(3)들을 갖는 엠보스식(emboss type) 웨이퍼 지지 디바이스(2)를 도시한다. 도 1c(상단 도면은 평면도이고, 하단 도면은 선 1C-1C를 취한 단면도이다)는 연속적 베이스면에 의해 격리된 오목부(5)들을 갖는 딤플식(dimple type) 웨이퍼 지지 디바이스(4)를 도시한다. 도 1b에 도시된 볼록부가 위에서 볼 때 정사각형으로 되어 있지만, 이 볼록부는 원형이 될 수 있다. 유사하게, 도 1c에 도시된 오목부가 위에서 볼 때 원형으로 되어 있지만, 이 오목부는 정사각형이 될 수 있다.
막 형성 중에 웨이퍼의 이면측에 발생되어 부착되는 입자들의 수를 감소시키기 위해, 웨이퍼 이면측과 서셉터의 상단면 사이의 접촉면적을 줄이는 것이 일반적으로 효과적이다. 그러나, 엠보스식 또는 딤플식 웨이퍼 지지 디바이스가 사용될지라도, 웨이퍼 이면측상에서의 입자들의 발생 및 축적이 여전히 문제가 된다. 또한, 웨이퍼 지지 디바이스의 볼록부 또는 오목부는 막 두께 및 막 특성의 균일성에 악영향을 주기도 한다.
관련 기술에 포함된 문제들 및 해법들의 어떠한 논의도 본 발명을 위한 문맥을 제공하기 위해서 단독으로 본 개시내용에 포함되었고, 이러한 논의 모두 또는 어떤 것이 본 발명이 만들어졌을 때 알려져 있었다고 인정하는 것으로 여겨져서는 안 된다.
본 발명은 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스로서, 베이스면; 및 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖는 돌출부를 포함하고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉에 의해 상기 라운드팁에 의해 전체적으로 지지되고, 상기 돌출부는 웨이퍼가 놓여 지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되며, 사용 중에 정해진 대로 상기 돌출부의 수(N) 및 높이(H [㎛])가 300 mm 웨이퍼에 대한 면적마다 다음의 부등식을 만족시키는 웨이퍼 지지 디바이스를 제공한다.
(-0.5N + 40)≤H≤53, 5≤N≤100
이때, 본 발명의 상기 돌출부는 직경 라인상에 배치되고, 실질적으로 등간격으로 배열되어 있는 것에도 그 특징이 있다.
게다가, 본 발명의 상기 돌출부는 각각이 상기 돌출부에 의해 형성된 동일한 정사각형 또는 동일한 정삼각형 각각의 점을 구성하도록 상기 베이스면 상에 기하학적 배열로 배치되어 있는 것에도 그 특징이 있다.
뿐만 아니라, 본 발명의 상기 돌출부는 동심적으로 배치되어 있는 것에도 그 특징이 있다.
나아가, 본 발명의 상기 돌출부는 각각이 상기 돌출부에 의해 형성된 동일한 정육각형 각각의 점을 구성하도록 상기 베이스면 상에 기하학적 배열로 배치되어 있는 것에도 그 특징이 있다.
더불어, 본 발명의 상기 돌출부는 상기 베이스면 내에 매립된 세라믹 볼로 형성되어 있는 것에도 그 특징이 있다.
이와 함께, 본 발명의 상기 돌출부는 돔형 세라믹으로 형성되어 있는 것에도 그 특징이 있다.
그리고, 본 발명의 상기 돌출부는 상기 베이스면의 재료와 동일한 재료로 형성되어 있는 것에도 그 특징이 있다.
아울러, 본 발명의 상기 라운드팁은 1 mm 내지 2 mm의 반경을 갖는 것에도 그 특징이 있다.
여기서, 본 발명의 상기 세라믹볼은 사파이어로 제조되는 것에도 특징이 있다.
또한, 본 발명의 상기 세라믹 볼은 2 mm 내지 4 mm의 직경을 갖는 것에도 그 특징이 있다.
추가로, 본 발명의 N은 20 내지 40의 정수인 것에도 그 특징이 있다.
게다가, 본 발명의 H는 50㎛ 이하인 것에도 그 특징이 있다.
또한, 본 발명은 반도체 가공 장치로서, 진공화될 수 있는 반응실; 상기 반응실의 내부에 설치되는 청구항 제 1항의 웨이퍼 지지 디바이스 및 가열블록을 포함하는 서셉터; 및 상기 서셉터와 평행하게 상기 반응실 내부에 설치되는 샤워헤드;를 포함하는 반도체 가공 장치를 제공한다.
이때, 본 발명은 RF 전원을 추가로 포함하고, 상기 RF 전원에서 상기 서셉터 및 상기 샤워헤드는 플라즈마를 발생시키기 위한 상부 전극 및 하부 전극으로서 작용하는 것에도 그 특징이 있다.
그리고, 본 발명은 반도체 가공 장치에 설치되어 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스의 제조 방법으로서, 웨이퍼 지지 디바이스에 베이스면을 제공하는 단계; 사용 중에 정해진 대로 돌출부의 수가 N이고 높이가 H[㎛]일 때, 300 mm 웨이퍼에 대한 면적마다 부등식 (-0.5N + 40)≤H≤53, 5≤N≤100을 사용하여 상기 돌출부를 디자인하는 단계로서, 상기 돌출부는 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉에 의해 상기 라운드팁에 의해 전체적으로 지지되고, 상기 돌출부는 웨이퍼가 놓여 지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되는 단계; 및 디자인된 상기 돌출부과 함께 웨이퍼 지지 디바이스를 제조하는 단계;를 포함하는 웨이퍼 지지 디바이스의 제조 방법을 제공한다.
여기서, 본 발명의 H는 50㎛ 이하이고, N은 20 내지 40의 정수인 것에도 그 특징이 있다.
도 1a는 종래 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 하단 도면은 선 1A-1A를 취한 단면도.
도 1b는 종래 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 하단 도면은 선 1B-1B를 취한 단면도.
도 1c는 종래 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 하단 도면은 선 1C-1C를 취한 단면도.
도 2a는 본 발명의 실시예에 따른 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2A-2A를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2A-2A를 취한 단면도.
도 2b는 본 발명의 다른 실시예에 따른 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2B-2B를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2B-2B를 취한 단면도.
도 2c는 본 발명의 또 다른 실시예에 따른 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2C-2C를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2C-2C를 취한 단면도.
도 2d는 본 발명의 여전히 다른 실시예에 따른 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2D-2D를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2D-2D를 취한 단면도.
도 2e는 본 발명의 다른 실시예에 따른 웨이퍼 지지 디바이스의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2E-2E를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2E-2E를 취한 단면도.
도 3은 (비교예로서) 직경 1mm를 갖는 주상(columnar) 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측의 긁힌 부분에 대한 결함관찰 주사전자 현미경(Defect Review SEM)의 영상을 나타낸 도면.
도 4는 본 발명의 한 실시예에 따라, 2mm의 직경을 갖는 구체들이 매립되어 있는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측의 긁힌 부분에 대한 결함관찰 주사전자현미경의 영상을 나타낸 도면.
도 5는 본 발명의 한 실시예에 따라, 2mm의 직경을 갖는 구체들이 매립되어 있는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측의 원형 변형 부분에 대한 결함관찰 주사전자 현미경의 영상을 나타낸 도면.
도 6은 1mm의 직경과 30㎛의 높이를 갖는 주상 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킴(비교예로서).
도 7은 본 발명에 따라, 2mm의 직경을 갖는 구체들이 매립되어 있으며 50㎛의 높이를 갖는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킴
도 8은 본 발명의 실시예들에 따라 막 응력과 돌출부의 높이 사이의 관계를 예시하는 그래프.
도 9는 본 발명의 실시예들에 따라 웨이퍼 이면측의 입자들의 수와 돌출부의 높이 사이의 관계를 예시하는 그래프.
도 10은 본 발명의 실시예들에 따라 막 응력과 입자들의 수에 대하여 돌출부의 높이와 돌출부의 수 사이의 관계를 예시하는 그래프.
도 11은 막 두께의 균일성과 돌출부의 높이 사이의 관계를 예시하는 그래프(기준 예로서).
도 12는 막 응력과 돌출부의 높이 사이의 관계를 예시하는 그래프(기준 예로서).
도 13은 본 발명의 실시예에 따라 웨이퍼 지지 디바이스를 구비한 반도체 가공장치의 개략도.
도 14는 2mm의 직경을 갖는 구체들이 매립되어 있으며 10㎛의 높이를 갖는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킴(비교예로서).
도 15는 2mm의 직경을 갖는 구체들이 매립되어 있으며 30㎛의 높이를 갖는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킴(비교예로서).
도 16은 2mm의 직경을 갖는 구체들이 매립되어 있으며 32㎛의 높이를 갖는 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킴(비교예로서).
도 17은 돌출부의 높이 H[㎛]와 돌출부의 수(N) 사이의 관계를 예시하는 그래프이며, 여기서 회색(Gray) 영역은 본 발명의 실시예에 따라 막 특성들 및 입자 축적을 상당하게 개선하는 범위를 가리킴.
본 발명의 이러한 특징들 및 다른 특징들은 이제 본 발명을 예시하지만 제한하지 않는 의도로 되어있는 양호한 실시예들의 도면을 참고하여 설명될 것이다. 도면들은 예시의 목적을 위해 아주 간략화 되어 있고 크기대로 그려진 것이 아니다.
하나의 양상에서, 본 발명의 목적은 막 형성 중에 웨이퍼 이면측에 부착되는 입자들의 수를 감소시킬 수 있고 또한 막 두께 및 막 특성의 균일성을 개선할 수 있는 서셉터 상단면을 제공하는데 있다. 웨이퍼 이면측과 웨이퍼 지지 디바이스의 상단면이 막 형성 중에 서로 접촉되어 있는 경우 입자들이 웨이퍼 이면측상에서 관찰되기 때문에, 일부 실시예들에서는 웨이퍼 이면측과 웨이퍼 지지 디바이스의 상단면 사이의 접촉면적을 감소시키기 위해, 라운드팁(rounded tips)을 갖는 돌출부가 웨이퍼 지지 디바이스의 베이스면상에 제공되어 접촉면적을 감소시킨다. 위에서, 돌출부의 수를 감소시키는 것은 웨이퍼 이면측과 웨이퍼 지지 디바이스의 상단면 사이의 접촉점들의 수를 감소시키기 위해 효과를 발휘할 수 있다. 그러나, 돌출부의 수가 작을 때, 웨이퍼는 가공 방식에 따라 접촉점들 사이의 작은 처짐 또는 변형(비록 이것이 정도가 작을지라도)을 겪는 경향이 있고, 따라서 서셉터의 상단면에 접촉하여 웨이퍼 이면측상에서 입자들의 발생 및 축적을 증가시킨다. 위에서, 돌출부의 높이를 증가시킴에 의하여 웨이퍼의 작은 처짐 또는 변형이 발생할 때에는 웨이퍼 이면측과 웨이퍼 지지 디바이스의 상단면 사이의 접촉을 억제할 수는 있다. 그러나, 돌출부의 높이가 증가할 때, 막 응력이 심해지는 경향이 있다.
상기 관점에 따라, 일부 실시예들에서, 라운드팁을 갖는 돌출부을 사용하고 그리고 제어 파라미터들로서 돌출부의 수 및 높이를 사용함으로써, 웨이퍼 지지 디바이스가 디자인되고, 이는 놀랍게도 웨이퍼 이면측상에서 입자들의 축적을 감소시킬 수 있고 막 응력과 막 특성들과 막 두께의 균일성을 개선할 수 있다.
일부 실시예들은, 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스로서, (ⅰ) 베이스면; 및 (ⅱ) 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖는 돌출부을 포함하고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉을 통해 상기 라운드팁에 의해 전체적으로 지지되도록 되어 있고, 상기 돌출부는 웨이퍼가 놓여지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되고, 용도에 정해진 대로 상기 돌출부의 수(N) 및 높이(H [㎛])는 300 mm 웨이퍼에 대한 면적마다 다음의 부등식(inequity)들, (-0.5N + 40)≤H≤53, 5≤N≤100을 만족하는, 웨이퍼 지지 디바이스를 제공한다.
다른 양상에서, 일부 실시예들은, 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스 제조방법으로서, (Ⅰ) 웨이퍼 지지 디바이스에 베이스면을 제공하는 단계; (Ⅱ) 300 mm 웨이퍼에 대한 면적마다 아래의 부등식들 을 사용하여 돌출부을 디자인하는 단계; 및 (Ⅲ) 상기 디자인된 돌출부과 함께 웨이퍼 지지 디바이스를 제조하는 단계를 포함하고: (-0.5N + 40)≤H≤53, 5≤N≤100
여기서 N 및 H는 용도에 정해진 대로 돌출부의 수 및 높이([㎛])이고, 상기 돌출부는 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉을 통해 상기 라운드팁에 의해 전체적으로 지지되도록 되어 있고, 상기 돌출부는 웨이퍼가 놓여지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되는, 제조방법을 제공한다.
관련 기술에 비하여 우수한 본 발명의 양상들 및 장점들을 개략 설명하기 위해, 본발명의 어떠한 목적들 및 장점들이 여기에 설명되어 있다. 당연히, 반드시 필요한 것은 아니지만 그러한 목적들 또는 장점들은 본 발명의 어떠한 특별한 실시예에 따라 달성될 수 있다는 것을 이해할 것이다. 따라서 예를 들어 기술에 숙련된 자들(이하 당업자)은 본 발명이 여기에 가르치고 암시한 대로 반드시 다른 목적들 또는 장점들을 달성하지 않아도 여기에 가르친 대로 하나의 장엄 또는 장점들의 그룹을 달성하거나 최적화하는 방법으로 구체화 또는 수행될 수 있다는 것을 인식할 것이다.
또한, 본 발명의 양상들, 특징들 및 장점들은 이하의 상세한 설명으로부터 명백하게 나타날 것이다.
본 개시에서, "실질적으로 동일", "실질적으로 균일" 등은 당업자가 인식하는 차이에 대한 것으로서, 예를 들어 10%미만, 5%미만, 1% 미만 또는 그 범위의 어떤 것을 의미한다. 본 개시에서, "점접촉"은 표면들 중 적어도 하나가 구부러지는 한 지점에서 이론적으로 또는 실질적으로 초기에 서로 접촉하는 2개의 구별된 물체들의 경질 표면들을 지칭하며, 또는 직경이 약 50㎛이하 또는 약 20㎛가 될 수 있는 접촉면적을 지칭할 수 있다. 본 개시에서 상태들 및/또는 구조들이 특정되어 있지 않는 경우, 당업자는 본 개시내용의 관점에서 통상적인 실험 사항으로서 그러한 상태들 및/또는 구조들을 용이하게 제공할 수 있다. 또한 본 개시에서, 특정한 실시예들에 포함된 수는 다른 실시예들에서 적어도 ±50% 범위로 변경될 수 있고, 실시예들에 포함된 범위들은 종료점들을 포함하거나 배제할 수 있다.
상술한 바와 같이, 일부 실시예들에서, 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스는, (ⅰ) 베이스면; 및 (ⅱ) 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖는 돌출부을 포함하고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉을 통해 상기 라운드팁에 의해 전체적으로 지지되도록 되어 있고, 상기 돌출부는 웨이퍼가 놓여지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되고, 용도에 정해진 대로 상기 돌출부의 수(N) 및 높이(H [㎛])는 300 mm 웨이퍼에 대한 면적마다 다음의 부등식들, (-0.5N + 40)≤H≤53; 5≤N≤100을 만족한다. 도 17은 상기 관계를 예시하는 그래프이며, 여기서 회색 영역은 막 특성들 및 입자 축적을 상당하게 개선하는 범위를 가리킨다. 일부 실시예들에서, H는 약 50㎛ 이하이다.
높이(H)는 통상적으로 웨이퍼 지지 디바이스가 사용될 때, 즉 웨이퍼 지지 디바이스상에 놓인 웨이퍼를 챔버 내에서 가공하는 동안, 베이스면의 상단면(기준면)으로부터 돌출부(돌출부 주위에 리세스가 있는가 여부에 관계없이)의 가장 높은 지점까지 이르는 거리로서 규정되어 있다. 일부 실시예들에서, 세라믹 또는 합금 볼들이 돌출부을 구성하는데 사용될 때, 세라믹 볼들과 베이스면을 포함한 재료와의 열팽창으로 인하여 돌출부의 높이가 웨이퍼 지지 디바이스가 약 400℃의 온도에서 웨이퍼를 가공하기 위한 용도에 사용될 때 프로세스 이전의 돌출부의 높이에 비하여 예를 들어 약 10㎛만큼 감소된다. 일부 실시예들에서, 웨이퍼 지지 디바이스가 사용되지 않을 때의 돌출부의 높이를 H'로 정의할 때, 부등식들 (-0.5N + 50)≤H'≤65; 5≤N≤100을 만족한다. 일부 실시예들에서, 세라믹 또는 합금 볼들이 돌출부을 구성하는데 사용될 때, H=(H'-10㎛). 일부 실시예들에서, H'는 적어도 (0.5N + 52.3), 60㎛이하이다. 돌출부가 웨이퍼 지지 디바이스의 재료 표면을 기계적으로 연마함으로써 형성될 때, 열팽창의 차이가 발생하지 않기 때문에, 사용시의 돌출부의 높이는 사용하지 않을 때(이하 '비사용시'라고 함)의 높이와 동일하며, 즉 H=H'.
세라믹 또는 합금 볼들이 돌출부을 구성하는데 사용될 때, H(가공 온도에서 사용시의 높이)는 다음과 같이 H'(실온에서 비사용시의 높이)로부터 결정될 수 있다: 웨이퍼 지지 디바이스가 실온 T0에서 T1으로 가열될 때, 베이스면에서 내부에 볼을 수용하는 보이드 또는 리세스의 깊이는 A만큼 증가한다:
A = CTE(M)×D(M)×(T1-T0)
여기서 CTE(M)은 웨이퍼 지지 디바이스의 베이스 재료의 선팽창계수이고, D(M)은 보이드 또는 리세스의 직경이다.
유사하게, 볼이 실온 T0에서 T1으로 가열될 때, 볼의 직경은 B만큼 증가한다:
B = CTE(B)×D(B)×(T1-T0)
여기서 CTE(B)은 볼의 선팽창계수이고, D(B)는 볼의 직경이다. 따라서,
H = H' - (A - B)
예를 들어, 볼이 사파이어(CTE(B)=7E-6)로 제조되고, 베이스 재료는 알루미늄 합금 6061(CTE(M)=23E-6)이고, 볼 및 보이드 또는 리세스의 직경은 0.002m(D(B)=D(M)=0.002), T1은 400(T1=400℃, T0=25℃)일 때, (A - B)의 값은 12.0E-6[m]로 계산될 수 있다. 상술한 바와 같은 동일한 조건하에서 볼 및 보이드 또는 리세스의 직경이 0.004m(D(B)=D(M)=0.004)일 때, (A - B)의 값은 24.0E-6[m]로 계산될 수 있다.
일부 실시예들에서, N은 약 20 내지 약 40의 정수이다. 일부 실시예들에서, N이 21이상이고, 60미만이다. 이러한 구성에 따라, 웨이퍼 지지 디바이스를 사용하여 TEOS로부터 형성된 산화규소막과 같은 막은 안정적인 응력(웨이퍼들 사이의 막 응력의 편차들이 약 20MPa 또는 약 10MPa 이내에서 억제될 수 있다)을 가질 수 있고, 웨이퍼 이면측에 부착된 입자들의 수가 300 mm 웨이퍼에 대한 면적마다 약 400이하 또는 약 200이하로 감소될 수 있다. 일부 실시예들에서, 웨이퍼 지지 디바이스는 가열요소 또는 독립된 전극을 포함하지 않고, 또는 전기 척으로서 작용하거나 이에 필요한 어떠한 구조를 가지지 않는다. 일부 실시예들에서, 웨이퍼 지지 디바이스는 전기 척으로서 작용하거나 이에 필요한 어떠한 구조를 가지지 않고 가열요소 및/또는 독립된 전극을 포함한다.
일부 실시예들에서, 웨이퍼 이면측과 돌출부의 라운드팁이 점접촉에 의해 서로 접촉하기 때문에, 그들 사이의 초기 접촉면적(막 형성 전에)은 극도로 작아서, 예를 들어 웨이퍼 이면측의 면적에 대하여 10-6% 내지 10-3%(일부 실시예들에서 10-5% 내지 10-4%)의 범위에 있다.
일부 실시예들에서, 베이스면의 직경 라인상에 배치된 돌출부는 실질적으로 등간격으로 배열되어 있다. 일부 실시예들에서, 돌출부는 상기 돌출부 각각이 상기 돌출부에 의해 형성된 동일한 정사각형들 또는 동일한 정삼각형들 각각의 점을 구성하도록 상기 베이스면상에 기하학적 배열로 배치되어 있다. 대안으로서, 일부 실시예들에서, 돌출부는 동심적으로 배치된다. 대안으로서, 일부 실시예들에서, 돌출부는 상기 돌출부 각각이 상기 돌출부에 의해 형성된 동일한 정육각형들 각각의 점을 구성하도록 상기 베이스면상에 기하학적 배열로 배치된다. 일부 실시예들에서, 상기 구성들 중 어느 것이라도 단일 베이스면상에서 어떠한 조합이 사용될 수 있다.
일부 실시예들에서, 돌출부는 베이스면에 매립된 세라믹 볼들로 형성된다. 일부 실시예들에서, 세라믹 볼들은 사파이어로 제조된다. 일부 실시예들에서, 세라믹 볼들은 알루미나, 기타 산화알루미늄, 질화알루미늄, 질화마그네슘, 탄화규소 등으로 제조된다. 일부 실시예들에서, 돌출부을 돔형 세라믹스로 형성된다. 일부 실시예들에서, 스테인레스강, 알루미늄 합금, 티타늄 합금 등이 사용될 수 있다. 일부 실시예들에서, 라운드팁은 약 1mm 내지 약 2mm의 반경을 갖는다. 일부 실시예들에서, 세라믹 볼들은 약 2mm 내지 약 4mm의 직경을 갖는다.
일부 실시예들에서, 돌출부는 베이스면의 재료와 동일한 재료로 형성된다. 베이스면은 알루미늄, 양극성 산화알루미늄, 알루미늄 합금 등으로 제조될 수 있다.
일부 실시예들에서, 웨이퍼를 지지하기 위한 돌출부 이외의 돌출부가 베이스면상에 제공되어 있다. 일부 실시예들에서, 베이스면은 돌출부 이외에 단차들, 스페이서들, 테두리들을 갖지 않으며, 클램핑기구를 갖지 않는다. 일부 실시예들에서, 웨이퍼는 중력에 의하여 주도적으로 또는 실질적으로 돌출부상에 놓인다.
본 발명의 다른 양상은 반도체 가공 장치로서, (Ⅰ) 진공화될 수 있는 반응실; (Ⅱ) 상술한 웨이퍼 지지 디바이스들 중 어떤 것 및 가열블록을 포함하고, 상기 반응실 내부에 장착되는 서셉터; 및 (Ⅲ) 상기 서셉터와 평행하게 상기 반응실 내부에 장착된 샤워헤드(showerhead)를 포함하는, 반도체 가공 장치를 제공한다. 일부 실시예들에서, 웨이퍼 지지 디바이스는 플라즈마 또는 열 CVD 장치를 포함하는 CVD장치, 플라즈마 또는 열 CVD 장치를 포함하는 ALD장치, 또는 에칭장치 내에서 서셉터로서 사용된다. 일부 실시예들에서, 반도체 가공 장치는 RF 전원을 추가로 포함하고, 상기 RF 전원에서 서셉터 및 샤워헤드는 플라즈마를 발생하기 위해 상부 전극 및 하부 전극으로서 작용한다.
여전히 다른 양상에서 본 발명은 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스 제조방법으로서, (a) 웨이퍼 지지 디바이스에 베이스면을 제공하는 단계; (b) 300 mm 웨이퍼에 대한 면적마다 아래의 부등식들 을 사용하여 돌출부을 디자인하는 단계; 및 (c) 상기 디자인된 돌출부을 갖는 웨이퍼 지지 디바이스를 제조하는 단계를 포함하고: (-0.5N + 40)≤H≤53; 5≤N≤100, 여기서 N 및 H는 용도에 정해진 대로 돌출부의 수 및 높이([㎛])이고, 상기 돌출부는 상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉을 통해 상기 라운드팁에 의해 전체적으로 지지되도록 되어 있고, 상기 돌출부는 웨이퍼가 놓여지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되는, 제조방법을 제공한다.
일부 실시예들에서, 부등식들은 (-0.5N + X)≤H≤Y; 5≤N≤100, 여기서 X = 40.5, 41, 42, 43, 44, 또는 45, Y = 47, 48, 49, 50, 51, 또는 52가 어떠한 조합을 이룬다. 일부 실시예들에서, N은 약 20 내지 약 40의 정수이다. 일부 실시예들에서, N은 21이상, 60미만이다.
본 발명은 본 발명을 제한할 의도가 없는 실시예들 및 도면을 참고하여 상세히 설명될 것이다.
도 2a는 본 발명의 실시예에 따른 웨이퍼 지지 디바이스(10)의 개략도로서, 상단 도면은 평면도이고, 중간 도면은 한 실시예에 따라 선 2A-2A를 취한 단면도이고, 반면 하단 도면은 다른 실시예에 따라 선 2A-2A를 취한 단면도이다. 이 실시예에서, 돌출부(11, 11')은 돌출부 각각이 돌출부에 의해 형성된 동일한 정사각형들 각각의 점을 구성하도록 베이스면 전체에 걸쳐 기하학적 배열로 배치된다. 베이스면의 직경 라인(2A-2A)상에 배치된 돌출부(11, 11')은 실질적으로 등간격으로 배열되어 있다. 돌출부(11)은 베이스면에 매립된 세라믹 볼들이고, 한편 돌출부(11')은 베이스면의 재료와 동일한 재료로 형성된다. 세라믹 볼들(11)은 코킹(caulking)에 의해 베이스면에 매립될 수 있다. 예를 들어, JP 2007-180246에 개시된 코킹 방법이 사용될 수 있고, 그 내용은 본원에 전체적으로 합체되어 있다. 돌출부(11')은 기계적으로 예를 들어 연마에 의해 형성될 수 있다. 도 2b에 도시된 웨이퍼 지지 디바이스(12) 및 돌출부(13, 13')은 도 2a에 도시된 것들과 유사하고, 다만 도 2a에서 돌출부(11, 11')의 수는 21이고, 반면 도 2b에서 돌출부(13, 13')의 수는 37인 것이 다르다.
도 2d에 도시된 웨이퍼 지지 디바이스(16) 및 돌출부(17, 17')은 도 2a에 도시된 것들과 유사하고, 다만 도 2a에서 돌출부(11, 11')의 수는 21이고, 반면 도 2d에서 돌출부(17, 17')의 수는 22이고 그리고 돌출부(17, 17')이 돌출부 각각이 돌출부에 의해 형성된 동일한 정삼각형들 각각의 점을 구성하도록 베이스면 전체에 걸쳐 기하학적 배열로 배치되는 것이 다르다. 도 2d에 도시된 구성에서, 모든 인접한 2개의 돌출부 사이 및 어떠한 인접한 2개의 돌출부 사이의 거리는 동일하므로, 돌출부가 웨이퍼의 처짐을 일으키지 않고 더욱 균등하게 지지할 수 있다.
도 2e에 도시된 웨이퍼 지지 디바이스(18) 및 돌출부(19, 19')은 도 2a에 도시된 것들과 유사하고, 다만 돌출부(19, 19')이 동심적으로 배치되어 있는 것이 다르다(도 2e의 돌출부(19. 19')의 수는 도 2a와 동일하게 21이다).
도 2c에 도시된 웨이퍼 지지 디바이스(14) 및 돌출부(15, 15')은 도 2a에 도시된 것들과 유사하고, 다만 도 2a에서 돌출부(11, 11')의 수는 21이고, 반면 도 2c에서 돌출부(15, 15')의 수는 54이고 그리고 돌출부(15, 15')이 돌출부의 각각이 돌출부에 의해 형성된 동일한 정육각형들 각각의 점을 구성하도록 베이스면 전체에 걸쳐 기하학적 배열로 배치되는 것이 다르다. 베이스면의 직경 라인상에 배치된 돌출부(15, 15')은 등간격으로 배치되지 않고, 2가지 다른 간격으로 배치된다(대안으로 긴 간격과 짧은 간격으로).
도 13은 본 발명의 실시예에 따른 웨이퍼 지지 디바이스를 구비한 반도체 가공 장치의 개략도이다. 반응실(111)에서, 서셉터 상단판(101)은 상하로 이동할 수 있는 가열요소를 포함한다. 샤워헤드(102)는 웨이퍼 지지 디바이스(101) 위에서 평행하게 배치된다. 샤워헤드(102) 및 웨이퍼 지지 디바이스(101)는 용량적으로 커플링되고, 상부 전극 및 하부 전극으로서 작용한다. RF 전원(105)이 RF 전력을 샤워헤드(102)에 공급하고, 웨이퍼 지지 디바이스는 접지되어 있다. 샤워헤드(102)를 향하여, 전구체가 밸브(103)를 구비한 라인(108)을 경유하여 공급되고, 반면 반응물질 또는 기타 가스들은 밸브(104)를 구비한 라인(109)을 경유하여 공급된다. 반응실은 배기시스템(도시 안 됨)을 갖는다.
실례들
[비교예 1]
약 350nm의 두께를 갖는 산화규소막이 도 13에 도시된 반도체 가공 장치를 사용하여 300 mm 웨이퍼상에 TEOS를 이용하여 증착되었으며, 반도체 가공 장치에는 1.0mm의 직경을 갖는 17개의 주상 돌출부가 동심적으로 분포된 웨이퍼 지지 디바이스가 장착되었고, 50㎛의 높이(H')를 가지고 있었다(돌출부가 기계적으로 형성되었기 때문에, 사용시의 높이(H)는 비사용시의 높이(H')와 동일한 것으로 결정되었다). 막 형성 후에, 웨이퍼 이면측을 관찰하였다. 도 3은 막 형성 후에 웨이퍼 이면측의 긁힌 부분(스크래치)에 대한 결함관찰 주사전자 현미경(Defect Review SEM)의 영상이다. 도 3에 도시된 바와 같이, 일부 스크래치들이 길이가 1mm 이상이고 폭이 50-100㎛인 큰 스크래치들의 많은 영역들이 일반적으로 돌출부의 팁들이 위치해 있었던 영역들에서 관찰되었다. 또한, 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리키고 있는 도 6에 도시된 바와 같이, 입자들의 축적이 관찰되고, 여기서 직경 0.2㎛ 이상을 갖는 247개의 입자들이 관찰되었다.
[실례 1]
막 형성은 비교예 1과 동일한 방법으로 웨이퍼상에 실시되었고, 다만 2mm의 직경과 50㎛의 높이(H')를 갖는 사파이어 볼들을 사용하여 도 2b(37개의 돌출부)에 도시된 웨이퍼 지지 디바이스가 사용되었다는 것이 다르다. 알루미늄 합금 본체와 사파이어 볼들 사이의 열팽창계수의 차이로 인하여, 사용시의 높이(H)는 아래에 계산된 바와 같이 비사용시의 높이(H')보다 약 12㎛ 더 작은 것으로 결정되었다:
A = CTE(M)(23E-6: 알루미늄 합금 6061)×D(M)(0.002m)×(T1-T0)(T1=390℃, T0=25℃) = 17.0E-6 m
B = CTE(B)(23E-6: 알루미늄 합금 6061)×D(B)(0.002m)×(T1-T0)(T1=390℃, T0=25℃) = 5.18E-6 m
A-B = 11.8E-6 m
H = H' - 11.8[㎛](
Figure 112019038872013-pat00001
12㎛).
도 4는 막 형성후 웨이퍼 이면측의 긁힌 부분에 대한 결함관찰 주사전자 현미경의 영상이다. 도 5는 막 형성후 웨이퍼 이면측의 원형 변형 부분에 대한 결함관찰 주사전자 현미경의 영상이다. 도 4 및 도 5에 도시된 바와 같이, 스크래칭들 및 원형 변형 부분들이 관찰되었지만, 이들은 매우 작아서 직경이 약 20㎛ 내지 약 30㎛의 범위에 있는 작은 영역들로 제한되었다. 또한, 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리키는 도 7에 도시된 바와 같이, 비교예 1에 비하여 입자들의 축적이 상당히 줄어 든 것이 관찰되었고, 0.2㎛ 이상의 직경을 갖는 112개의 입자들이 관찰되었다.
[실례 2]
막 형성은 실례 1과 동일한 방법으로 웨이퍼상에 실시되었고, 다만 2mm의 직경을 갖는 사파이어 볼들을 사용하여 도 2a(21개의 돌출부)에 도시된 웨이퍼 지지 디바이스와, 2mm의 직경을 갖는 사파이어 볼들을 사용하여 도 2b(37개의 돌출부)에 도시된 웨이퍼 지지 디바이스가 사용되었고, 이러한 웨이퍼 지지 디바이스들의 높이(H')가 도 8에 도시된 바와 같이 변화되었고, 막들의 막 응력(stress)이 측정되었다는 것이 다르다(알루미늄 합금 본체와 사파이어 볼들 사이의 열팽창계수의 차이로 인하여, 사용시의 높이(H)가 비사용시의 높이(H')보다 약 12㎛ 더 작은 것으로 결정되었다). 도 8은 이 실시예에 따라 막 응력(stress)과 돌출부의 높이(Height of Protrusions, H') 사이의 관계를 예시하는 그래프이다. 응력은 7개의 막의 평균이고, 높이(H')가 40㎛이하일 때의 데이터는 도 2a에 도시된 웨이퍼 지지 디바이스를 사용하여 얻어지고, 높이(H')가 40㎛보다 높을 때의 데이터는 도 2b에 도시된 웨이퍼 지지 디바이스를 사용하여 얻어진 것이다. 도 8에 도시된 바와 같이, 돌출부의 높이(H')가 약 60㎛ 또는 약 65㎛보다 작을 때(H < 약 48 또는 53㎛), 막 응력의 편차들은 약 10MPa 내로 감소될 수 있다.
[실례 3]
막 형성은 실례 1과 동일한 방법으로 웨이퍼상에 실시되었고, 다만 2mm의 직경을 갖는 사파이어 볼들을 사용하여 도 2a(21개의 돌출부)에 도시된 웨이퍼 지지 디바이스와, 2mm의 직경을 갖는 사파이어 볼들을 사용하여 도 2b(37개의 돌출부)에 도시된 웨이퍼 지지 디바이스가 사용되었고, 이러한 웨이퍼 지지 디바이스들의 높이(H')가 도 9에 도시된 바와 같이 변화되었고, 웨이퍼 이면측상의 입자들의 수가 측정되었다는 것이 다르다. 도 9는 이 실시예에 따라 웨이퍼 이면측의 입자들의 수(Number of Particles on Reverse Side)와 돌출부의 높이(Height of Protrusions, H') 사이의 관계를 예시하는 그래프이다. 입자들의 수는 3개의 웨이퍼들의 평균이었다. 도 9에 도시된 바와 같이, 도 2a(21개의 돌출부)에 도시된 돌출부의 높이(H')가 약 40㎛이상일 때(H < 약 28㎛), 0.2㎛이상의 직경을 갖는 입자들의 수가 약 500개 이하로 제어될 수 있었고, 돌출부(21개의 돌출부)의 높이(H')가 약 40㎛이상일 때(H > 약 28㎛), 0.2㎛이상의 직경을 갖는 입자들의 수가 약 300개 이하로 제어될 수 있었고, 반면에 도 2b(37개의 돌출부)에 도시된 돌출부의 높이(H')가 30㎛ 보다 많을 때(H > 약 18㎛), 0.2㎛이상의 직경을 갖는 입자들의 수가 약 300개 이하로 제어될 수 있었다. 도 2a(21개의 돌출부)에 도시된 돌출부과 도 2b(37개의 돌출부)에 도시된 돌출부 모두에 대해서, 돌출부의 높이(H')가 약 50㎛이상일 때(H > 약 38㎛), 입자들의 수는 약 200보다 작게 감소될 수 있는 것으로 예상된다.
도 14는 10㎛의 높이(H')(H
Figure 112019038872013-pat00002
0㎛)를 갖는 21개의 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킨다(비교예로서). 사파이어 볼들이 사용되었을 때, 사용시의 높이(H)는 비사용시의 높이(H')보다 약 12㎛ 더 작은 것으로 결정되었고, 따라서 12㎛의 높이(H')가 거의 충분한 접촉이 되는 것으로 결정되었다. 도 15는 30㎛의 높이(H')(H=18㎛)를 갖는 21개의 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킨다(비교예로서). 도 16은 32㎛의 높이(H')(H=20㎛)를 갖는 21개의 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스를 사용하여 막 형성후 웨이퍼 이면측에 대한 입자 맵(웨이퍼면 검사장치에 의한)이며, 여기서 밝은 점들은 입자들의 부착을 가리킨다(비교예로서). 21개의 돌출부(사파이어 볼들)을 갖는 웨이퍼 지지 디바이스들에 대해서, 높이(H')가 32㎛이하(H ≤20㎛)일 때, 웨이퍼 이면측은 처짐에 의해 막 형성 중에 돌출부(돌출부 주위에 소수의 입자들이 있었다) 사이의 영역들에서 웨이퍼 지지 디바이스의 베이스면과 접촉하고, 따라서 웨이퍼 이면측에서의 입자들의 축적을 증가시켰다.
[기준 예 1]
막 형성은 비교예 1과 동일한 방법으로 웨이퍼상에서 실시되었고, 다만 돌출부의 높이가 변화된 것이 다르다. 도 11은 막 두께의 균일성(Uniformity)과 돌출부의 높이(Height of Protrusions) 사이의 관계를 예시하는 그래프이다. 도 12는 막 응력(stress)과 돌출부의 높이(Height of Protrusions) 사이의 관계를 예시하는 그래프이다. 돌출부가 기계적으로 형성되었기 때문에, 사용시의 높이(H)는 비사용시의 높이(H')와 동일한 것으로 결정되었다. 도 11 및 도 12에 도시된 바와 같이, 돌출부의 높이가 약 60㎛보다 높을 때, 막 응력뿐 아니라 막 두께의 균일성이 저해되었다. 도 12는 도 8에 대응하며, 따라서 구체-상단 돌출부을 갖는 웨이퍼 지지 디바이스가 사용될 때에도 막 두께의 균일성은 돌출부의 높이가 약 60㎛보다 높을 때 저해될 것으로 예상된다.
[돌출부의 수와 높이 사이의 관계]
실험들을 통해, 평균적으로, 0.2㎛이상의 직경을 갖는 2개의 입자들이 돌출부마다 웨이퍼 이면측에 발생되고 부착되는 것으로 결정할 수 있다. 따라서, 돌출부의 수가 약 100개보다 작을 때, 입자들의 수는 약 200개보다 작은 것으로 예상된다. 또한, 돌출부의 수가 증가될 때, 웨이퍼 지지 디바이스의 제조 원가도 증가된다. 상술한 것과 상기 실례들의 관점에서, 도 10은 막 응력과 입자들의 수를 상당하게 개선하기 위해 돌출부의 높이(Height of Protrusion, H')와 돌출부의 수(Number of Protrusions) 사이의 관계를 예시하는 그래프이다. 도10에서, "N/G"는 양 또는 불량을 나타내고, "OK"는 허용되거나 만족스러운 것을 지칭하고, "Gray"는 불량과 허용 사이의 범위를 지칭하고, "OK B/L"은 허용가능한 경계선을 지칭한다.
또한, 도 10의 그래프에서 상측 화살표는 "응력은 ㎛이상의 높이에서 N/G"의 의미이고, 우측 화살표는 "입자(>200)는 100개 이상의 돌출부에서 N/G"의 의미이며, "Reverse Side Particle OK range[>200]"은 "이면측 입자 OK 범위"이고, "Rerverse Side Particle N/G range[>200]"은 "이면측 입자 N/G 범위"이다.
그리고, 도 13에서 "Precursor"는 전구체를 의미하고, "Reactant"는 반응물질을 의미한다.
더불어, 도 17에서 "Height of Protrusions"는 돌출부의 높이를 의미하고, "Number of Protrusion"는 돌출부의 수를 의미한다.
당업자는 본 발명의 정신을 벗어나지 않고 여러 가지 변경이 만들어질 수 있음을 이해할 것이다. 따라서 본 발명의 형태들은 단지 예시에 불과하고 본 발명의 범위를 제한할 의도가 아니라는 것을 명백히 이해해야 한다.

Claims (8)

  1. 정전기 척으로서 작용하거나 정전기 척에 필요한 어떠한 구조 없이, 반도체 가공 장치에 설치되도록 구성된 웨이퍼 지지용 웨이퍼 지지 디바이스로서,
    상기 반도체 가공 장치 내에 베이스면을 가열하는 매립된 가열요소를 포함하는, 상기 베이스면; 및
    상기 베이스면에서 돌출하고 웨이퍼를 지지하기 위한 라운드팁을 갖는 돌출부를 포함하고, 상기 라운드팁은 웨이퍼의 이면측이 점접촉에 의해 상기 라운드팁에 의해 전체적으로 지지되고,
    상기 웨이퍼의 이면측과 접촉하는 상기 돌출부의 상기 라운드팁의 전체 영역이 상기 웨이퍼의 이면측의 영역의 10-6% 내지 10-3% 의 범위에 있고,
    상기 돌출부와 상기 베이스면 사이에서 열팽창에 차이가 존재하지 않도록 상기 돌출부와 상기 베이스면이 동일한 재료로 이루어지고, 상기 재료는 알루미늄, 양극성 산화 알루미늄, 또는 알루미늄 합금이고,
    상기 돌출부는 상기 베이스면을 기계 가공에 의해 형성된 것이고,
    상기 돌출부는 웨이퍼가 놓여 지는 상기 베이스면의 영역상에 실질적으로 균일하게 배치되며, 사용 중에 정해진 상기 돌출부의 수(N) 및 높이(H [㎛])가 300 mm 웨이퍼에 대한 면적마다 부등식 (-0.5N + 40)≤H≤47, 21≤N≤60을 만족시키되, 상기 웨이퍼의 이면측에 부착되는 입자들의 수는 300 mm 웨이퍼에 대한 면적마다 200 이하이고,
    상기 웨이퍼 지지 디바이스는 클램프 기구를 갖지 않고, 사용 중 상기 웨이퍼는 중력에 의해 단독으로 상기 돌출부 상에 유지되고,
    상기 베이스면의 직경 라인상에 배치된 상기 돌출부는 등간격으로 배열되어 있고,
    상기 베이스면과 상기 가열요소는 상하로 이동하도록 구성되고, 그리고,
    상기 웨이퍼 지지 디바이스는 접지되어 있는, 웨이퍼 지지 디바이스.
  2. 제 1 항에 있어서,
    상기 돌출부는 각각이 상기 돌출부에 의해 형성된 동일한 정사각형 또는 동일한 정삼각형 각각의 점을 구성하도록 상기 베이스면 상에 기하학적 배열로 배치되어 있는 웨이퍼 지지 디바이스.
  3. 제 1 항에 있어서,
    상기 돌출부는 돔형 세라믹으로 형성되어 있는 웨이퍼 지지 디바이스.
  4. 제 1 항에 있어서,
    상기 라운드팁은 1 mm 내지 2 mm의 반경을 갖는 웨이퍼 지지 디바이스.
  5. 제 1 항에 있어서,
    N은 21 내지 40의 정수인 웨이퍼 지지 디바이스.
  6. 제 1 항에 있어서,
    H는 47㎛ 이하인 웨이퍼 지지 디바이스.
  7. 반도체 가공 장치로서,
    진공화될 수 있는 반응실;
    상기 반응실의 내부에 설치되는 청구항 제 1항의 웨이퍼 지지 디바이스 및 가열블록을 포함하는 서셉터; 및
    상기 서셉터와 평행하게 상기 반응실 내부에 설치되는 샤워헤드를 포함하는 반도체 가공 장치.
  8. 제 7 항에 있어서,
    RF 전원을 추가로 포함하고, 상기 RF 전원에서 상기 서셉터 및 상기 샤워헤드는 플라즈마를 발생시키기 위한 상부 전극 및 하부 전극으로서 작용하는 반도체 가공 장치.
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