TWI733859B - 填充間隙的方法及儀器 - Google Patents

填充間隙的方法及儀器 Download PDF

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TWI733859B
TWI733859B TW106124130A TW106124130A TWI733859B TW I733859 B TWI733859 B TW I733859B TW 106124130 A TW106124130 A TW 106124130A TW 106124130 A TW106124130 A TW 106124130A TW I733859 B TWI733859 B TW I733859B
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plasma
reactant
gas
inert
gaps
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TW201816172A (zh
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財津優
深澤篤毅
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荷蘭商Ａｓｍ智慧財產控股公司
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Abstract

本發明提供一種用於藉由將基板提供於反應腔室中且提供沉積方法填充在該基板上製造特徵期間所產生之一或多個間隙的方法。該沉積方法包含：提供各向異性電漿以藉由離子轟擊該一或多個間隙之表面之底部區域，從而在該底部區域產生吸附位點；將第一反應物引入至該基板；及，允許該第一反應物與該表面之該底部區域處的該等吸附位點反應以自該底部區域向上填充該一或多個間隙。

Description

填充間隙的方法及儀器
本發明大體而言係關於用於製造電子元件之方法及儀器。
更特定言之，本發明係關於一種藉由以下填充在基板上製造特徵期間所產生之一或多個間隙的方法及儀器：在反應腔室中提供基板且提供沉積方法，其包含：將第一反應物引入至基板；及允許第一反應物在表面之底部區域反應以填充一或多個間隙。
在基板上製造積體電路期間，可在該基板上產生間隙(例如，溝槽)。根據特定應用，可採取多種形式再填充溝槽。
基礎溝槽填充方法可具有缺陷，包括在再填充期間在溝槽中形成空隙。在溝槽經完全填充之前，當再填充材料在溝槽頂部附近形成縮窄時，可能形成空隙。此類空隙可能損害積體電路(integrated circuit；IC)上之元件之元件隔離及IC之整體結構完整性。不幸地，在溝槽填充期間防止空隙形成可通常造成對該等溝槽自身的最小尺寸限制，此可能限制元件之元件裝填密度。
若溝槽經填充用於元件隔離，則在量測元件隔離之有效度中之關鍵參數可為場臨限電壓，亦即，產生連接相鄰隔離元件之寄生電流所 必需的電壓。場臨限電壓可受多個物理特性及材料特性影響，諸如溝槽寬度、溝槽填充材料之介電常數、基板摻雜、場植入劑量及基板偏壓。
可藉由減小溝槽深度及/或使溝槽側壁逐漸變窄來降低空隙形成以使得開口可在頂部比在底部更寬。減小溝槽深度之權衡可能為降低元件隔離之有效度，而具有逐漸變窄側壁之溝槽之較大頂部開口耗用額外的積體電路實際面積。
舉例而言，目的為提供一種改良之或至少替代性間隙填充方法。
因此，提供一種用於藉由提供沉積方法來填充在該基板上製造特徵期間所產生之一或多個間隙的方法，該沉積方法包含：提供各向異性電漿以藉由離子轟擊一或多個間隙之表面之底部，從而在底部產生吸附位點；將第一反應物引入至基板；及允許第一反應物與表面之底部區域處的該等產生之吸附位點反應以自底部區域向上填充一或多個間隙。
各向異性電漿將藉由離子轟擊一或多個間隙之表面之底部且從而在底部產生吸附位點。第一反應物將被引入至反應腔室中之基板且允許其與表面之底部處的吸附位點反應以自底部向上填充一或多個間隙。
根據另一個具體實例，提供一種半導體處理儀器以提供改良的或至少替代性的間隙填充方法。該儀器包含：一或多個反應腔室，其用於容納基板，該基板具有在基板上製造特徵 期間所產生的間隙；電漿氣體之電漿氣體源，其經由電漿氣體閥與該等反應腔室中之一者氣體連通；射頻電源，其經建構且經佈置以產生電漿氣體之各向異性電漿以藉由離子轟擊一或多個間隙之表面之底部，從而在底部產生吸附位點；第一反應物之第一源，其經由第一閥與該等反應腔室中之一者氣體連通；及，控制器，其可操作地連接至電漿及第一氣體閥及射頻電源且經組態並程式化以控制：經由電漿氣體閥的電漿氣體及射頻源之時序(timing)及量，以使用該電漿氣體源及該射頻電源以產生各向異性電漿以藉由離子轟一或多個間隙之表面之底部，從而在該底部產生吸附位點；及，第一反應物之時序及量，以將該第一反應物沉積於間隙之表面之底部中以與在該底部處的該等所產生之吸附位點反應。
出於概述本發明及所達成的優於先前技術之優點的目的，已在上文中對本發明之某些目標及優點加以描述。當然，應理解，未必所有的此類目的或優點均可根據本發明之任何特定具體實例來達成。
因此，舉例而言，熟習此項技術者將認識到，可以如本文中所教示或建議來達成或最佳化一個優點或一組優點而不一定達成如本文中可能教示或建議的其他目標或優點的方式來實施或進行本發明。
所有此等具體實例意欲在本文所揭示之本發明範圍內。此等及其他具體實例將自參考附圖之以下某些具體實例之詳細描述而對熟習此 項技術者變得顯而易見，本發明並不受限於所揭示之任何特定具體實例。
1:基板
2:電極/下段
3:反應腔室
4:電極/噴淋板
5:轉移腔室
6:排氣管線
7:排氣管線
11:內部
12:另一側
13:循環導管
14:隔離板
16:內部
20:HRF功率
21:氣體管線
22:管線
24:密封氣體管線
100:沉積方法
110:第一步驟
120:第二步驟
參考某些具體實例之圖式在下文中描述本文中所揭示的本發明之此等及其他特徵、態樣及優點，該等圖式意欲說明而非限制本發明。
圖1A為可用於本發明之具體實例中的用於填充間隙之PEALD(電漿增強型原子層沉積；plasma-enhanced atomic layer deposition)儀器之示意性表示。
圖1B說明可用於本發明之具體實例中的使用流通系統(flow-pass system；FPS)之前驅物供應系統之示意性表示。
圖2為用於根據第一具體實例填充間隙之方法之流程圖。
儘管在下文中揭示某些具體實例及實施例，但熟習此項技術者應理解，本發明延伸超出本發明所具體揭示之具體實例及/或用途及其明顯修改及均等物。因此，意欲所揭示之本發明之範圍不應受下文所描述之特定所揭示具體實例限制。
圖2為根據本發明之至少一個具體實例的方法之流程圖，其中在基板上製造特徵期間所產生之一或多個間隙可利用沉積方法100填充。間隙可小於40nm或甚至20nm寬。間隙可超過40nm、100nm、200nm或甚至400nm深。
沉積方法可包含在第一步驟110中，提供各向異性電漿以藉由離子轟擊一或多個間隙之表面之底部，從而在該底部產生吸附位點。一或多個間隙之表面之底部可經界定為下部，包括底部本身之間隙之總高度 的10%。沉積方法可包含，在第一步驟110中提供各向異性電漿以藉由離子轟擊相對於表面之側壁的一或多個間隙之表面之底部，從而在該底部比在側壁上產生更多的吸附位點，或甚至在側壁上無實質性吸附面。
各向異性電漿可包含惰性氣體電漿(諸如氦電漿或氬電漿)以轟擊一或多個間隙之表面之底部以在暴露表面上產生懸鍵。
可使用例如圖1A中所說明之儀器產生各向異性電漿。圖1A為可用於本發明之一些具體實例中的適宜結合程式化控制以實施本文中所描述之程序的PEALD儀器之示意圖。藉由將一對平行且彼此面對的導電性平板電極4、2提供在反應腔室3之內部11(反應區)中，將HRF功率(13.56MHz或27MHz)20施加於一側，且將另一側12電接地，在該等電極之間激發各向異性電漿。
溫度調節器提供於下段2(下部電極)中，且位於其上之基板1之溫度在既定溫度下保持恆定。上部電極4亦用作噴淋板，且將電漿氣體(例如惰性氣體，諸如氬氣或氦氣)經由氣體管線21且經由噴淋板4引入至反應腔室3以產生電漿。
在反應腔室3中，可提供具有排氣管線7之循環導管13，經由該排氣管線可排放來自反應腔室3之內部11中之氣體。安置於反應腔室3下方之轉移腔室5可具有密封氣體管線24以將密封氣體經由轉移腔室5之內部16(轉移區)引入至反應腔室3之內部11中，其中提供有用於隔離反應區與轉移區之隔離板14(晶圓轉移至轉移腔室5或自該轉移腔室轉移所經由之閘閥在此圖示中被省去)。轉移腔室亦具有排氣管線6。
在一些具體實例中，膜之各向異性蝕刻、沉積及表面處理可 在相同的反應空間中執行，使得全部步驟可在不暴露基板於空氣或其他含氧氣氛圍的情況下連續地實施。在一些具體實例中，遠端電漿單元可用於激發氣體。
在一些具體實例中，基板可相對於多個反應腔室移動使得該等處理步驟中之一些可在單獨反應腔室中進行。
熟習此項技術者將瞭解，儀器包括經程式化或以其他方式經組態以使得本文中其他處所描述之沉積及反應器淨化程序得以實施之一或多個控制器(圖中未示)。如熟習此項技術者將瞭解，該等控制器與多個電源、加熱系統、泵、機器人，及反應器之氣流控制器或閥連通。
參考圖2，在第二步驟120中，可將第一反應物提供至表面。第一反應物可包含有機矽化合物，例如，四有機矽烷。有機矽化合物可具有甲基端基。有機矽化合物可包含較少沉積於側壁上之四甲基矽烷。有機矽化合物可包含碳封端之矽前驅物。有機矽化合物可包含氮。第一有機矽可為矽烷醇、矽氧烷或矽烷烷氧化物。第一反應物可為用於SiN沉積之矽氮烷。第一反應物可經由管線22、經由噴淋板4提供至反應腔室3(參見圖1)中。
在圖2中之步驟120期間，可視情況產生濺鍍電漿以在表面之頂部區域中產生濺鍍，由此可將來自頂部區域之材料再定位於間隙之底部中。濺鍍電漿可包含氧電漿、氫電漿、氮電漿、氦電漿或氬電漿或其任何混合物。沉積薄膜之組成及質量可受電漿條件控制，例如，SiO沉積可藉由使用氧電漿來控制或SiN沉積可藉由使用氮/氫混合物來控制。
為改良濺鍍作用，第一反應物可具有較大的大小且可為弱化學吸附的。可藉由例如經由管線21、經由噴淋板4將氧電漿、氫電漿、氮電漿、氦電漿或氬電漿或其任何混合物提供至圖1之反應腔室3中來產生濺鍍電漿。
可在第一步驟110及第二步驟120之後移除過量反應物及副產物以防止在儀器中之其他處發生反應。沉積方法可經多個循環重複以自底部至頂部填充間隙使得再填充材料將不在間隙經完全填充之前在間隙之頂部附近形成收縮。
應理解，本文中所描述之組態及/或方法本質上為例示性的，且此等特定具體實例或實例不應視為具有限制意義，原因在於可能存在諸多變化。本文所描述之特定常式或方法可表示任何數目之處理策略中之一或多者。因此，所說明之各種操作可以所說明之順序、以其他順序進行，或在一些情況下被省去。
本發明之主題包括本文中所揭示之各種程序、系統及組態，及其他特徵、功能、作用及/或特性，及其任何及所有等效物的所有新穎但非顯而易見之組合及子組合。
100‧‧‧沉積方法
110‧‧‧第一步驟
120‧‧‧第二步驟

Claims (20)

  1. 一種用於藉由提供沉積方法填充在基板上製造特徵期間所產生之一或多個間隙的方法，該方法包含：提供惰性氣體各向異性電漿以藉由離子轟擊該一或多個間隙之表面之底部區域，從而在該底部區域處產生包含用於第一反應物之懸鍵之吸附位點；將第一反應物引入至該基板；及允許該第一反應物與相對於該表面之側壁之該表面之該底部區域處的該等產生之吸附位點反應，以在相對於該等側壁之該底部區域上沉積材料，以自該底部區域向上填充該一或多個間隙。
  2. 如申請專利範圍第1項之方法，其中該方法包含在提供該惰性氣體各向異性電漿及/或引入該第一反應物之後自該反應腔室移除過量反應物及副產物。
  3. 如申請專利範圍第1項之方法，其中該惰性氣體電漿包含氦電漿。
  4. 如申請專利範圍第1項之方法，其中該惰性氣體電漿包含氬電漿。
  5. 如申請專利範圍第1項之方法，其中在引入該第一反應物期間，產生濺鍍電漿以在該表面之頂部區域中產生濺鍍。
  6. 如申請專利範圍第5項之方法，其中該濺鍍電漿包含氫電漿。
  7. 如申請專利範圍第5項之方法，其中該濺鍍電漿包含氮電漿。
  8. 如申請專利範圍第5項之方法，其中該濺鍍電漿包含氧電漿。
  9. 如申請專利範圍第5項之方法，其中該濺鍍電漿包含氬電漿。
  10. 如申請專利範圍第1項之方法，其中該第一反應物包含有機矽化合物。
  11. 如申請專利範圍第10項之方法，其中該有機矽化合物包含四有機矽烷(tetraorganosilane)。
  12. 如申請專利範圍第10項之方法，其中該有機矽化合物包含甲基端基。
  13. 如申請專利範圍第10項之方法，其中該有機矽化合物包含四甲基矽烷。
  14. 如申請專利範圍第10項之方法，其中該有機矽化合物包含碳封端之矽前驅物。
  15. 如申請專利範圍第10項之方法，其中該有機矽化合物包含氮。
  16. 如申請專利範圍第10項之方法，其中該第一反應物包含矽烷醇。
  17. 如申請專利範圍第10項之方法，其中該第一反應物包含矽氧烷。
  18. 如申請專利範圍第10項之方法，其中該第一反應物包含矽烷烷氧化物。
  19. 如申請專利範圍第1項之方法，其中該第一反應物包含矽氮烷(silazane)。
  20. 一種半導體處理儀器，其包含：一或多個反應腔室，其用於容納基板，該基板具有在該基板上製造特徵期間所產生的間隙；惰性電漿氣體之惰性電漿氣體源，其經由惰性電漿氣體閥與該等反應腔室中之一者氣體連通；射頻電源，其經建構且經佈置以產生該惰性電漿氣體之各向異性惰性氣體電漿以藉由離子轟擊該一或多個間隙之表面之底部，從而在該底部處產生吸附位點；第一反應物之第一源，其經由第一閥與該等反應腔室中之一者氣體連通；及控制器，其可操作地連接至該電漿及第一氣體閥及該射頻電源且經組態 並程式化以控制：經由該惰性電漿氣體閥的該惰性電漿氣體及該射頻源之時序及量，以使用該惰性電漿氣體源及該射頻電源以產生各向異性惰性氣體電漿以藉由離子轟擊該一或多個間隙之該表面之該底部，從而在該底部處產生吸附位點；及該第一反應物之時序及量，以將該第一反應物沉積於該間隙之該表面之該底部中以與在該底部處的該等所產生之吸附位點反應。
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