CN101589459A - 用于层间介电气隙的pevcd沉积牺牲聚合物薄膜的紫外光固化 - Google Patents

用于层间介电气隙的pevcd沉积牺牲聚合物薄膜的紫外光固化 Download PDF

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CN101589459A
CN101589459A CNA2008800032700A CN200880003270A CN101589459A CN 101589459 A CN101589459 A CN 101589459A CN A2008800032700 A CNA2008800032700 A CN A2008800032700A CN 200880003270 A CN200880003270 A CN 200880003270A CN 101589459 A CN101589459 A CN 101589459A
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A·诺利
F·施米特
A·莱克斯曼
B·H·金
R·阿尔加瓦尼
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Abstract

本发明的实施例一般提供一种在半导体器件的导电元件之间形成气隙的方法，其中气隙的介电常数约为1。气隙的形成一般通过在相应导电元件间沉积牺牲材料、在导电元件与牺牲材料上沉积多孔层、然后通过多孔层从相应导电元件之间的间隙剥除牺牲材料，从而在相应导电元件之间留下气隙。牺牲材料可以是例如聚合α－萜品烯层，多孔层可以是例如多孔碳掺杂氧化层，且剥除工艺可利用例如基于紫外线(UV)的固化工艺。

Description

用于层间介电气隙的PEVCD沉积牺牲聚合物薄膜的紫外光固化
背景
技术领域
本发明权利要求所陈述的实施例一般涉及一种在半导体器件的导电元件之间形成气隙的方法，其中气隙的介电常数(k)约为1。
相关技术的描述
在半导体衬底上可靠地生产亚0.25(sub-quarter)微米和更小特征结构是制造下一代超大规模集成(VLSI)与极大规模集成(ULSI)器件的关键技术之一。然而随着电路技术推向极限，日益缩小的互连特征结构尺寸对处理技术与用于制造器件的材料的物理特性的要求日益提高。例如，为了提高集成电路上半导体器件的密度，特征结构的尺寸已缩减成亚0.25微米范围。此外，由于铜的电阻率比铝小，因此铜实质上已取代铝做为主要导体。另外，尺寸缩小使得介电材料(即置于导电特征结构间的材料)的介电常数必需小于先前使用的介电材料，即低k材料，在此通常是指介电常数小于约4.0，因为导电元件相距较近导致的各层间的电容耦合增加会不利地影响半导体器件起作用。
用来形成当前所需的多层半导体器件的常用方法是镶嵌或双嵌工艺。以镶嵌方法为例，一个或多个低k介电材料经沉积及图案化蚀刻成垂直与水平互连。导电材料(诸如含铜材料)和其它导电材料(诸如用来防止含铜材料扩散到周围的低k介电材料的阻挡层材料)接着镶入蚀刻图案或特征结构。导电材料一般被过量沉积，以确保充分填满介电层中的特征结构。但蚀刻图案外部(诸如衬底上)过多的含铜材料和阻挡层材料通常经由化学机械研磨工艺移除。一旦移除了过多的沉积物，器件大致上就具有基本平坦的上表面，此上表面会露出导电元件与绝缘元件，因此一般会再将绝缘层沉积于其上，以使特征结构的第一层与后续沉积至第一层上的第二层绝缘。
然而，关联于镶嵌工艺的挑战之一是，个别特征结构尺寸不断缩小以满足持断增加的电路密度。因此分隔开相应导电元件的材料的介电常数也必须降低，以便于保持相应导电元件的电气隔离。虽然目前低k介电材料可提供的介电常数可达约2.0至约3.5，但是需要介电常数更小的材料来支持持续变小的特征结构尺寸和更高的电路密度。
因此，需要用于半导体器件的导电元件之间的间隙壁，其中间隙壁的介电常数约小于2。
发明内容
本发明权利要求所陈述的实施例一般提供一种在半导体器件的导电元件之间形成气隙的方法，其中气隙的介电常数约为1。气隙的形成一般可通过在各导电元件之间沉积牺牲层、在导电元件与牺牲层上沉积多孔层、然后通过多孔层从相应导电元件之间的间隙剥除牺牲层，从而在相应导电元件之间留下气隙。牺牲层可以是例如诸如α-萜品烯的聚合物，多孔层可以是例如多孔氧化物层，且剥除工艺可例如利用紫外线(UV)固化工艺。
在一些实施例中，提供一种在导电互连之间形成低介电常数(k)间隙壁的方法。该方法一般包括：在沉积在衬底上的牺牲层中形成互连特征结构，其中牺牲层包含聚合α-萜品烯；以及用导电材料填充互连特征结构。该方法还包括：在经填充的互连特征结构与牺牲层上沉积多孔层，该多孔层具有整齐的孔隙结构；以及通过多孔层从在经填充的导电互连之间的一区域剥除牺牲层，以在导电互连之间形成气隙，其中剥除工艺包含基于紫外线(UV)的固化工艺。最后，该方法可包括在多孔层上沉积覆盖层，以密封整齐的孔隙结构。
在一些实施例中，提出一种在半导体器件的导电元件之间形成间隙壁的方法。该方法一般可包括在衬底上沉积牺牲层、在牺牲层中形成特征结构、以及用导电材料填充特征结构。该方法还包括：在经填充的互连特征结构与牺牲层上沉积多孔层，该多孔层具有整齐的孔隙结构；通过多孔层从在经填充的导电互连之间的一区域剥除牺牲层，以在导电互连之间形成气隙；以及在多孔层上沉积覆盖层，以密封整齐的孔隙结构。
在一些实施例中，提出一种在半导体器件的导电特征结构之间形成介电常数约为1的间隙壁的方法。该方法包括利用化学气相沉积工艺在衬底上沉积聚合α-萜品烯层，在聚合α-萜品烯层中蚀刻出特征结构，以及利用电化学电镀工艺、无电电镀工艺、物理气相沉积工艺、和化学气相沉积工艺的至少之一用导电材料填充在聚合α-萜品烯层中所蚀刻出的特征结构。此外，该方法可包括：利用化学机械研磨工艺平坦化半导体器件的上表面；在经填充的特征结构与聚合α-萜品烯层上沉积多孔氧化物层；以及利用紫外线剥除工艺从导电元件之间的区域剥除聚合α-萜品烯层，以在导电元件之间形成气隙，其中该紫外线剥除工艺被配置成通过多孔氧化物层中的孔隙移除聚合α-萜品烯层；以及在多孔的氧化物层上沉积覆盖层，以密封孔隙。
在一些实施例中，提供一种在导电互连特征结构之间形成低介电常数(k)间隙壁的方法，其中这些特征结构形成在半导体衬底上的牺牲层内。该方法可包括：在互连特征结构与牺牲层上沉积多孔层；通过多孔层从在导电互连特征结构之间的一区域移除至少一部分的牺牲层，以在导电互连特征结构之间形成气隙；以及在多孔层上沉积覆盖层，以密封多孔层。如此得到的互连特征结构之间的间隙充满空气，从而产生约为1的介电常数。
附图简述
例示以上概述的本发明的更具体描述可参考特定实施例进行，这些特定实施例的一部分在附图中示出。然而，要注意的是，虽然附图仅例示了特定实施例，但其并非用来限定本发明的范围。
图1例示使用多孔层在半导体器件的导电元件之间形成低介电常数(k)气隙的方法；
图2例示使用具穿孔的掩模层在半导体器件的导电元件之间形成低介电常数(k)气隙的方法；
图3例示使用牺牲层在半导体器件的导电元件之间形成低介电常数(k)气隙的方法；以及
图4例示使用牺牲层和碳掺杂氧化层在半导体器件的导电元件之间形成低介电常数(k)气隙的方法。
为便于了解，各图中同样的元件符号代表类似的元件。当可理解，其它实施例也可有益地结合一个实施例的元件和/或工艺步骤。
优选实施方式的详细描述
在一些实施例中，一般提供一种在半导体器件的导电元件之间形成气隙的方法。气隙的形成一般通过在导电元件间沉积可移除材料、在可移除材料与导电元件上沉积多孔层、然后通过多孔层从导电元件之间的间隙剥除沉积材料，从而在导电元件之间留下气隙。尽管可移除材料参照α-萜品烯进行讨论，但应可理解所述示例性方法可采用其它可移除材料，例如聚甲基丙烯酸甲酯(poly(methyl methacrylate))或聚对二甲苯(parylene)。
特定实施例可基于任何等离子体增强CVD室或包括诸如CENTURAULTIMA HDP-CVDTM系统、PRODUCER APF PECVDTM系统、PRODUCERBLACK DIAMONDTM系统、PRODUCER BLOK PECVDTM系统、PRODUCER DARC PECVDTM系统、PRODUCER HARPTM系统、PRODUCER PECVDTM系统、PRODUCER STRESS NITRIDE(氮化物)PECVDTM系统、和PRODUCER TEOS(四乙氧基硅烷)FSG(氟硅玻璃)PECVDTM系统的系统，其可从美国加州圣克拉拉的应用材料公司(AppliedMaterials，Inc.)购得。示例性
Figure A20088000327000091
系统在1999年1月5日授权的共同受让的美国专利NO.5,855,681中进一步描述，其一并引用于此以供参考。
图1例示在半导体器件的导电元件之间形成间隙或间隙壁的示例性方法，其中间隙或间隙壁的介电常数约小于2。该方法始于步骤100，第一层可以是低介电常数材料层101(如碳掺杂氧化层)，其沉积在半导体衬底(未示出)上。低介电常数材料层101可例如使用化学气相沉积工艺或等离子体增强化学气相沉积工艺沉积。第二层102可以是诸如聚合α-萜品烯的牺牲层，其沉积在低介电常数材料层101上，且可例如经由等离子体增强化学气相沉积工艺沉积。形成牺牲层102的沉积工艺方法可包括供应流速为约100mgm至约5,000mgm的α-萜品烯、流速为约100sccm至约5,000sccm的氦气(He)、流速为约100sccm至约2,000sccm的氧气(O2)，且压力为约2托(torr)至约8托、功率为约10瓦(W)至约1,000瓦、温度为约100℃至约300℃、间距为约200密尔(mil)至约1600密尔。
如此，低介电常数材料层101一般可构成第一层，即可用作为通孔、插塞与多层互连特征结构的层；而第二层102则可用作较大的单层特征结构，例如沟槽。如步骤110所示，一旦第一与第二层在衬底上形成，就可利用蚀刻、光刻、或其它在半导体器件层中形成特征结构的已知方法，在相应层中形成各种特征结构。例如，沟槽103A可蚀刻到第二层102中，通孔103B可蚀刻到第一层101中。如步骤120所示，一旦预期特征结构形成和/或蚀刻到相应层，就可用导电材料104(如铜)填充特征结构。虽未例示，但在沉积导电材料前，可将阻挡层沉积至相应特征结构中，以免导电材料扩散到邻接层。可过度沉积导电材料104，以便于充分填充特征结构103A和103B)，且因此如步骤120所示，导电材料104与第二层102的上表面可经平坦化而构成基本平坦的表面。
一旦平坦化了导电材料104与第二层102的上表面，如步骤130所示，就可将多孔层105沉积于其上。多孔层105一般可具有足够的厚度，以对后续沉积层提供结构刚性和支撑，其通常包括相当密集的孔隙。孔隙可以有序的互连方式排列，即相应层中的孔隙大致上垂直对齐，从而分子可经由整齐的互连孔隙轻易地从多孔层一侧直线行进到另一侧。整齐的互连孔隙一般呈对齐孔隙(即类似圆柱)，由此直径小于孔隙直径的分子可通过多孔层105。或者，孔隙可以无序方式排列，即孔隙大致上不垂直对齐，因此孔隙不会构成穿过多孔层的直线路径。在此配置下，孔隙通常互相偏移，因此穿过多孔层的分子在垂直通过一定厚度的层前，将先通过一孔隙行进一段垂直距离，再水平行进到另一孔隙。多孔层105可以是任意数量的多孔层，其不限于例如多孔氧化物层、多孔氮化物层、多孔BLOk层、以上各层的组合、或半导体领域熟知的其它多孔层。多孔层105的厚度可例如为约100埃至约1,000埃，其中形成的孔隙的直径为约10埃至约200埃。更具体地，多孔层105的厚度可例如在约200埃至约600埃之间，其中形成的孔隙的直径为约20埃至约60埃。
多孔层105可藉由溶胶-凝胶凝聚工艺的分子自组装(self-assembly)，形成高度受控及具再现性的整齐孔隙大小和形状。以此工艺为例，硅醇盐(如四乙基正硅酸盐(tetraethylorthosilicate))在含有合适的水溶性溶剂(如丙二醇单丙基醚(propylene glycol monopropyl ether))且添加水和适当酸的溶液中，水解形成液态溶液。硅醇盐的酸催化水解反应会产生部分聚合的硅烷醇悬浮在溶液中的复杂混合物。添加表面活性剂至溶液可提供分子自组装的模板结构。表面活性剂浓度的关键范围需在后续干燥时，使表面活性剂能适当分离成胶束(micelle)。低浓度的四甲基铵盐也可加到化学前体溶液中，以提供最后锻烧步骤所需的化学环境。表面活性剂分子通常是两亲的，可包括疏水部分和亲水部分端。在干燥初期，两性分子会进行自组装，让分子中较短的亲水部分朝向结构外表面而接触水溶性环境，而较长的疏水部分则簇集在一起以构成胶束内部主体。溶剂化硅烷醇涂覆在自组装胶束外边的水溶性部分，形成最初的多孔膜架构。溶剂挥发期间，此结构通常会构成超分子装配体(supramolecular assembly)。
在沉积多孔层105期间，可将含有全部所需成分的液态化学前体涂到旋转的衬底表面，以使化学前体覆盖整个衬底表面。接着迅速将衬底转速加速到预定最终转速，该转速将决定膜厚(膜厚也受特定的其它包括溶液黏度等因素影响)。溶剂(和大部分的过量水分)在旋转时会挥发而形成”尚未干透”的膜层。此膜层进一步在加热板上干燥，例如在140℃干燥1分钟。然后例如在约350℃至约400℃进行高温锻烧从而形成最终膜结构。在锻烧期间，表面活性剂模板通过烧蚀自膜层脱落而形成具有整齐互连孔隙的预期膜层。互连孔隙通道有助于取出表面活性剂。由于溶剂挥发引发的自组装胶束形成，以及采用大小均一的表面活性剂分子决定了胶束大小，因此整齐孔隙的特征是孔径大小分布很窄。审慎选择表面活性剂分子尺寸可调节胶束大小；凭借化学前体溶液中所采用的表面活性剂浓度可调节总体多孔性。在一些实施例中，多孔层105和牺牲层102可被原位(in-situ)沉积。在其它实施例中，多孔层105和牺牲层102可被非原位(ex-situ)沉积。
多孔层105也可通过已知的半导体层沉积技术沉积，例如化学气相沉积和等离子体增强化学气相沉积。一旦沉积了多孔层105，如步骤140所示，就可利用剥除工艺移除位于相应特征结构之间的部分第二层102(即分隔开第二层中相应导电特征结构的聚合α-萜品烯层)。如果第二层102为诸如聚合α-萜品烯的牺牲层，则可以是基于紫外线的固化工艺的剥除工艺用来离解构成相应导电元件之间的牺牲层的分子，从而经由多孔层105流出导电元件之间的区域。因此，导电元件之间的区域无牺牲材料留下，因而在导电元件之间形成气隙106。鉴于空气的介电常数一般为1，从相应导电元件之间的区域移除牺牲层从而在其间形成气隙106用来在相应导电元件之间形成约为1的介电常数。通过孔隙剥除有机层的示例性工艺采用基于UV的固化工艺。该UV固化工艺只利用热进行固化一段时间。此工艺可利用美国加州圣克拉拉的应用材料公司制造的UV系统，例如NanoCure系统执行。也可使用其它UV系统，例如2005年5月9日提交的、题为“用于固化介电材料的复式紫外线腔室(TANDEM UV CHAMBER FOR CURINGDIELECTRIC MATERIALS)”、公开号为2006/0251827的美国专利申请S/N.11/124,908所描述的系统，其一并引用于此且不与本说明书相悖。此工艺可使用静态或双频源实现。腔室压力可为约2托至约12托，腔室温度可为约50℃至约600℃。UV源波长可为约200纳米(nm)至约300nm。氦气的供应流速可为约100sccm至约20,000sccm。在一些实施例中，可附加采用诸如氩气、氮气、以及氧气、或其混合气体。UV功率可为约25％至约100％，处理时间可为约0-200分钟。一旦完成剥除工艺，也可以是低k材料的覆盖层或密封层(未示出)可被沉积至多孔层105上，以密封其中形成的孔隙，并防止材料回流到气隙区域内。
在一些实施例中，当通过上层中形成的穿孔从导电元件间的区域中移除牺牲层时，可不利用剥除工艺来形成空气间隙壁。在图2所示的实施例中，如步骤200所示，诸如含碳氧化硅层的低介电常数材料层201被沉积在半导体衬底上，并且可以是聚合α-萜品烯层的牺牲层202被沉积在低介电常数材料层201上。以类似图1所示实施例的方式，层201和202可以多种已知沉积工艺形成，例如化学气相沉积。一旦形成了层201和202，如步骤210所示，各种特征结构203(即接线、插塞、通孔、沟槽等)可按需形成在层201和层202中，以支撑要制造的元件。在层201和202中形成特征结构203的方法可通过半导体领域熟知的多种工艺，例如蚀刻工艺进行。一旦形成特征结构203，如步骤220所示，例如铜的导电材料204就沉积到特征结构203内。更具体地，诸如物理气相沉积、化学气相沉积、和/或电镀等铜沉积工艺可用来形成覆盖整个衬底表面的铜填充层，该整个衬底表面包括特征结构和含聚合α-萜品烯的牺牲层202的上表面。另外，如果需要可在形成导电材料204前沉积阻挡层，以防止导电材料204扩散到周围的层。导电材料204一般使用过度沉积工艺形成，即铜的沉积量足以填充各个特征结构203，这通常表示铜被过度沉积至牺牲层202的上表面。诸如化学机械研磨和回蚀等各种平坦化技术可用来平坦化牺牲层202的上表面以及其中沉积有导电材料204的特征结构203的导电上表面。无论采取何种平坦化技术，最终结果是将上表面平坦化，如步骤220所示。在一些实施例中，可在平坦化金属之前或之后，固化导电材料204。
一旦平坦化了上表面，如步骤230所示，就将掩模层205沉积到牺牲层202与其中所形成的导电特征结构204上。掩模层205可由阻挡层材料和/或其它低k材料构成，其通常为碳化硅层。此低k层以及上述任一低k层的沉积工艺方法可包括供应约300sccm至约2,500sccm的三甲硅烷(TMS)、最高约达5,000sccm的氦气(He)、最高约达1,000sccm的氨气(NH3)、压力为约1托至约14托、功率为约50瓦至约1,500瓦、且温度为约300℃至约400℃。掩模层205的厚度通常为约100埃至约1,000埃，但也可实现更厚或更薄的掩模层。一旦形成了掩模层205，如步骤240所示，就可在其中形成多个掩模孔206。掩模孔206一般可位于分隔开相应导电元件204的区域之上，即掩模孔206一般位于牺牲层202上且偏离导电元件204。一旦形成了掩模孔206，方法就继续至步骤250，以从相应导电元件204之间的区域移除分隔开导电元件204的牺牲材料。掩模孔206可以是策略地置于牺牲层上的圆孔或管口；或者，掩模孔206可以是沿着要剥除的一部分牺牲层铺置的细长孔或通道。移除工艺一般包括利用剥除工艺剥除分隔开相应导电元件204的牺牲材料，以便于在导电元件204间形成气隙207或间隙壁。假设分隔开导电元件204的牺牲材料为聚合α-萜品烯层，基于UV的固化工艺可用来从导电元件204之间的区域移除聚合α-萜品烯。这样，剥除工艺一般包括经由掩模孔206向聚合α-萜品烯层施加UV光，从而通过行进通过掩模孔206从导电元件204之间的区域移除聚合α-萜品烯。一旦从导电元件204之间的区域移除了聚合α-萜品烯，剥除工艺的结果就将是在相应导电元件204之间形成气隙207。尽管气隙区域内可能残留聚合α-萜品烯，但导电元件204之间的间隙大致上仍为气隙，因此介电常数约为1。此外，为了密封掩模孔206，覆盖层(未示出)可被沉积到掩模层205上。覆盖层可以是多孔氧化物层、多孔氮化物层、多孔碳化硅层、或适合覆盖半导体器件的其它层。
在本发明的另一实施例中，如图3所示，可使用双嵌工艺来在半导体器件的导电元件之间形成低k间隙壁。如步骤300所示，双嵌工艺一般包括将聚合α-萜品烯层301沉积到衬底(未示出)上。聚合α-萜品烯层301的厚度通常足以使半导体器件特征结构在其中形成，且可通过已知半导体沉积技术沉积，例如等离子体增强化学气相沉积。一旦形成了聚合α-萜品烯层，方法就继续至步骤310，以在聚合α-萜品烯层301中形成互连特征结构302。可以是例如沟槽及/或通孔的互连特征结构302可通过蚀刻工艺在聚合α-萜品烯层301内形成。一旦在聚合α-萜品烯层301中形成了特征结构302，就可用例如是铜的导电材料303填充特征结构。如步骤320所示，导电材料303可通过已知的半导体沉积技术沉积到聚合α-萜品烯层301上和特征结构302上，例如物理气相沉积工艺、化学气相沉积工艺、无电电镀工艺、及/或电化学电镀工艺。如同半导体领域所知悉地，将导电材料303沉积到特征结构302内的工艺一般包括过度沉积导电材料303，然后利用平坦化或研磨工艺移除过度沉积物。无论采用何种填充和/或平坦化工艺，最终结果是用导电材料303填充特征结构302、以及在特征结构302上产生基本平坦的上表面，该上表面大致与聚合α-萜品烯层301的上表面共面。
一旦用导电材料303填充并平坦化特征结构302，就可完全移除相应导电特征结构302之间的聚合α-萜品烯层。如步骤330所示，移除工艺一般包括基于UV的固化工艺，其被配置成完全移除聚合α-萜品烯层301。一旦移除了中间的聚合α-萜品烯，先前被聚合α-萜品烯占据的间隙可用极低k材料304填充。尽管各类极低k材料皆落入本发明的范围，但沉积在导电元件303之间的材料的介电常数通常为约1.7至约2.2，较佳为约2。以类似步骤320的金属沉积工艺的方式，沉积极低k材料304一般还包括过度沉积极低k材料以完全填满先前被聚合α-萜品烯占据的间隙。因此，步骤340一般还包括诸如化学机械研磨工艺的平坦化步骤，其被配置成平坦化导电材料303和沉积在导电元件303之间的极低k材料304的上表面。一旦完成平坦化工艺，方法就继续至步骤350，其中将阻挡层305沉积在导电特征结构303与极低k层301上。阻挡层305通常用来使其下所形成层中呈现的导电元件与后续沉积在阻挡层305上所形成层中的导电元件电气隔离。
在一些实施例中，提供镶嵌方法以在半导体器件的导电元件之间形成低k间隙壁。如图4所示，该方法一般始于步骤400，先将低k材料层401沉积在衬底(未示出)上；接着将聚合α-萜品烯层402沉积在层401上。低k材料层401通常可以是含碳氧化硅层。示例性含碳氧化硅材料在2005年3月9日提交、题为“使用电子束形成极低介电常数膜的方法(METHOD FORFORMING ULTRA LOW K FILMS USING ELECTRON BEAM)”、公开号为2005/0153073的美国专利申请S/N.11/076,181中描述，其一并引用于此且不与本说明书相悖。一旦形成了层401和402，方法就继续至步骤410，以在层401和402中形成各种器件特征结构403。可以是沟槽、通孔、或其它已知用来构成半导体器件的特征结构的器件特征结构403例如可通过蚀刻工艺形成。一旦形成了特征结构403，方法就继续至步骤420，其中用导电材料404填充特征结构403。可以是例如铜的导电材料可使用已知的半导体层形成技术填充特征结构403，例如物理气相沉积、化学气相沉积、和/或电化学电镀。无论采取何种沉积技术，金属层一般都被过度沉积至特征结构403内，然后加以平坦化。
一旦形成了特征结构并用导电材料填充了这些特征结构，方法就继续至步骤430，以从导电特征结构404之间的区域移除聚合α-萜品烯层402。移除聚合α-萜品烯层一般可经由UV固化工艺或其它已知能有效移除聚合α-萜品烯层的工艺完成。一旦移除聚合α-萜品烯，本质上会在相应导电元件404之间形成气隙405；继续至步骤440，其中通过移除聚合α-萜品烯材料并用极低k材料406填充而形成气隙。以类似金属沉积工艺的方式，沉积极低k材料一般用过度沉积工艺完成，且因此过度沉积材料例如以化学机械研磨工艺从器件表面移除。因此在完成步骤440时，器件大致上包括导电元件404，其间设置有极低介电常数材料。此外，经化学机械平坦化工艺处理后，器件具有基本平坦的上表面，即导电元件404的上表面与极低介电常数材料的上表面齐平。接着继续至步骤450，其中将阻挡层407沉积到导电元件404和极低k材料406上。
尽管前面的内容涉及本发明的各个实施例，但可设计本发明的其它和进一步的实施例而不背离其基本范围，且其范围根据所附权利要求确定。

Claims (20)

1.一种用于在导电互连间形成低介电常数(k)间隙壁的方法，所述方法包括：
在沉积在衬底上的牺牲层中形成多个互连特征结构，其中所述牺牲层是聚合α-萜品烯层；
用导电材料填充所述互连特征结构；
将多孔层沉积到所述经填充的互连特征结构与所述牺牲层上，所述多孔层具有整齐的孔隙结构；以及
通过所述多孔层从在所述经填充的导电互连间的区域移除至少一部分的所述牺牲层，以在所述导电互连之间形成气隙。
2.如权利要求1所述的方法，其特征在于，所述移除步骤包括基于紫外线的固化工艺。
3.如权利要求1所述的方法，其特征在于，进一步包括将覆盖层沉积到所述多孔层上，以密封所述整齐的孔隙结构。
4.如权利要求1所述的方法，其特征在于，所述气隙的介电常数约为1。
5.如权利要求1所述的方法，其特征在于，所述填充工艺包括物理气相沉积工艺、化学气相沉积工艺、电化学电镀工艺、和无电电镀工艺的至少之一。
6.如权利要求1所述的方法，其特征在于，所述多孔层包含多孔含碳氧化物层。
7.如权利要求1所述的方法，其特征在于，进一步包括在所述填充步骤与所述沉积多孔层的步骤之间平坦化所述衬底的上表面，其中所述平坦化步骤包含使用化学机械研磨。
8.如权利要求1所述的方法，其特征在于，沉积所述多孔层包括：
将液态溶液沉积到所述衬底上，所述液态溶液进行反应以形成悬浮在所述溶液中的部分聚合的硅烷醇；以及
固化所述衬底上的所述溶液以形成所述多孔层。
9.如权利要求1所述的方法，其特征在于，所述沉积多孔层和沉积覆盖层在原位进行。
10.一种在半导体器件的导电元件之间形成间隙壁的方法，所述方法包括：
将牺牲层沉积到衬底上；
在所述牺牲层中形成多个特征结构；
用导电材料填充所述特征结构；
将多孔层沉积到所述经填充的互连特征结构与所述牺牲层上，所述多孔层具有整齐的孔隙结构；
通过所述多孔层从所述经填充的导电互连之间的区域剥除所述牺牲层，以在所述导电互连之间形成气隙，其中所述剥除工艺包括基于紫外线的固化工艺；以及
将覆盖层沉积到所述多孔层上，以密封所述整齐的孔隙结构。
11.如权利要求10所述的方法，其特征在于，所述牺牲层是聚合α-萜品烯层。
12.如权利要求11所述的方法，其特征在于，将牺牲层沉积到所述衬底上的步骤包括：
供应流速为约100mgm至约5,000mgm的α-萜品烯；
供应流速为约100sccm至约5,000sccm的氦气；以及
供应流速为约100sccm至约2,000sccm的氧气。
13.如权利要求10所述的方法，其特征在于，所述牺牲层是成孔剂。
14.如权利要求10所述的方法，其特征在于，所述多孔层为多孔的碳掺杂氧化层。
15.如权利要求10所述的方法，其特征在于，所述剥除工艺包括通过在所述多孔层中形成的穿孔，从所述特征结构之间的区域剥除所述牺牲层。
16.如权利要求10所述的方法，其特征在于，还包括在用导电材料填充所述特征结构之前，将阻挡层沉积于在所述牺牲层中形成的特征结构上。
17.如权利要求10所述的方法，其特征在于，所述气隙的介电常数约为1。
18.如权利要求10所述的方法，其特征在于，所述多孔层选自由多孔氧化物层、多孔氮化物层、和多孔碳化硅层所构成的群组。
19.如权利要求10所述的方法，其特征在于，还包括在所述填充步骤与所述沉积多孔层的步骤之间，平坦化所述半导体器件的上表面。
20.一种在半导体器件的导电特征结构之间形成介电常数约为1所谓间隙壁的方法，所述方法包括：
利用等离子体增强化学气相沉积工艺，将聚合α-萜品烯层沉积到衬底上；
在所述聚合α-萜品烯层中蚀刻出多个特征结构；
利用电化学电镀工艺、无电电镀工艺、物理气相沉积工艺、和化学气相沉积工艺的至少之一，用导电材料填充所述聚合α-萜品烯层中所蚀刻出的特征结构；
利用化学机械研磨工艺平坦化所述半导体器件的上表面；
将多孔氧化物层沉积在所述经填充的特征结构与所述聚合α-萜品烯层上；以及
通过基于紫外线的固化工艺从多个导电元件之间的区域剥除所述聚合α-萜品烯层，以在所述导电元件之间形成气隙，其中所述紫外线固化工艺被配置成通过所述多孔氧化物层中的多个孔隙移除所述聚合α-萜品烯层；以及
将覆盖层沉积到所述多孔氧化物层上，以密封所述孔隙。
CNA2008800032700A 2007-01-26 2008-01-22 用于层间介电气隙的pevcd沉积牺牲聚合物薄膜的紫外光固化 Pending CN101589459A (zh)

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