CN100483647C - 沉积多孔膜的方法 - Google Patents
沉积多孔膜的方法 Download PDFInfo
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- CN100483647C CN100483647C CNB2005800282454A CN200580028245A CN100483647C CN 100483647 C CN100483647 C CN 100483647C CN B2005800282454 A CNB2005800282454 A CN B2005800282454A CN 200580028245 A CN200580028245 A CN 200580028245A CN 100483647 C CN100483647 C CN 100483647C
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- silicon
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
本发明涉及一种将主体基质材料的多孔膜沉积在一基材上的方法,其包括数个加工循环,其中每个循环包括:共沉积该主体基质材料与硅;在共沉积之后,将该共沉积物置于包括至少一种选择性硅去除试剂的反应环境,从而使该共沉积物中的硅通过该选择性硅去除试剂优先化学去除,在该共沉积物中形成孔;重复进行该共沉积与该选择性硅去除步骤,构成该多孔膜的厚度。用本发明的方法可制得具有高度均匀小孔及所需孔率轮廓之多孔膜。该方法有利于形成广泛范围之供半导体集成电路制造用的低k电介质。该方法亦有利于形成用于其它应用之其它多孔膜。
Description
发明的背景
1.技术领域
本发明总体上涉及一种用于在基材上沉积多孔膜之加工方法。更明确地说,本发明涉及一种用于沉积供制造半导体集成电路用之多孔氧化硅或掺杂氧化硅膜的加工方法。该方法亦有利地用于需要多孔结构之其它应用。
2.相关领域的描述
以往,采用介电常数(k)约4之二氧化硅作为供制造半导体集成电路用之绝缘材料。随着装置尺寸缩小,互连RC(电阻—电容)延迟问题需要该绝缘体具有更低介电常数以给出优良的电路性能。半导体工业已经以各种技术交点确认此等目标,并将之发表于International Technology Roadmap for Semiconductors。介电常数低于4通常称为低k值,而低于2.2通常称为超低k值。预计在90nm装置这一代以后需要k值低于2.6之低k电介质以制造装置。
介电常数是外电场在一种材料中感应电偶极倾向的尺度。这种所谓的电极化度系由该材料中的电子、离子与失真极化所支配的。极化现象的综述与各种类型的低介电常数材料的更详细论述可参见K.Maex等人的作品[K.Maex,M.R.Baklanov,D.Shamiryan,F.Iacopi,S.H.Brongersma,and Z.S.Yanovitskaya,J.App.Phys.,Vol.93,No.11,p.8793-8841]或S.Wolf之作品[“SiliconProcessing for The VLSI Era,Volume 4:Deep-Submicron Process Technology”by S.Wolf,Lattice Press,Sunset Beach,California,2002,p.639-670]。
基本上,为了弱化二氧化硅中之极化,可以改变硅与氧的结构晶格,以极化较少之键取代部分或全部硅-氧键,及/或导入自由空间以降低该膜中之材料密度。己在研究的方法包括1)开发基于二氧化硅的掺杂氧化物、2)开发基于倍半硅氧烷的无机—有机杂化聚合物、3)开发有机聚合物,及4)开发无定形无定形碳膜。
基于二氧化硅的氧化物通常是通过采用或不采用等离子体强化的化学气相沉积(CVD)法沉积的。掺杂氟可提供k值约3.6之氟硅酸盐玻璃(FSG)。碳或其它烷基取代基可以进一步降低该介电常数;有时可使k值达到低至2.6至2.8。己有报告指出完全无定形碳膜或氟碳化合物膜可产生更低k值。不过,无定形碳膜技术仍然尚未成熟,目前还无法列入制造考虑。
由于基于CVD二氧化硅的氧化物具有类似硅氧化物的结构,因此呼吁以此作为半导体电介质。该等膜几乎不需要对电路设计作修正。半导体制造商亦可应用现有工具组及基本设施继续其装置制造。此等膜中一部分已采用在180nm、150nm、130nm甚至90nm的节点(node)。不过,含氧碳化物膜在后续加工中倾向于发生碳损耗,导致低于所需之最终介电常数。此外,在二氧化硅中结合碳会引入许多处理复杂度,特别是在蚀刻、化学机械抛光与清洁方面。因此,实施方式令人畏惧且成本高昂。
相反地,由于基于倍半硅氧烷的无机-有机杂化聚合物和有机聚合物具有比二氧化硅更为开放的分子晶格,且分子组份中之极化键更少,因此其本身就是低k值电介质。这些材料可提供宽范围的低k值。此等膜通常通过旋涂法施加,尽管某些膜亦可通过CVD法沉积。该旋涂膜必须经过固化以驱除过量溶剂,完全该化学反应,并发生致密化作用。与二氧化硅相较,此等膜通常在机械上更软且热稳定性较低。其亦可能吸收湿气,因此经常需要额外覆盖层以保护所述膜。由于所述不同性质,在常规加工中有许多限制,且通常在综合加工中需要改良以容纳所述膜。因此,尚未注意到其受普遍采用。
近年来,工业上己断定世界上不存在一种完全致密的旋涂或CVD材料,其具有足够低之介电常数并同时符合对90nm这一代及以后各代的综合加工之所有不同需求。由于介电常数值与主体基质密度成比例,因此注意力已转移到探索通过在绝缘体中导入孔率来降低介电常数的可能性。
已知溶胶-凝胶技术可提供一种用于在二氧化硅网络中导入掺杂物及形成多孔模板的灵活手段。不过,溶胶-凝胶技术需要小心地胶凝并干燥。其不同加工模式、加工控制与综合路径与半导体装置制造不兼容。此等膜中有许多亦显示出其机械性质随着k值降低而变差。
在该电介质中导入孔隙容积的更适合途径系使用牺牲成孔剂(详见美国专利6,271,273号与美国专利6,451,712号)。将一种热不稳定性材料(称为成孔剂)与有机硅酸盐聚合物加以掺合,并施涂以形成膜,如同常规的旋涂电介质那样。固化该膜,然后对其进行退火步骤以挥发该成孔剂,同时形成该固化膜之骨架多孔框架。此热解技术的关键系:首先,该成孔剂必须与热固性基质分离,且在退火步骤期间必须分解并且完全去除,不留下任何残留物。其次,该成孔剂分解必须在低于主体材料的玻璃化温度下进行,不引起该多孔结构崩解。第三,在相分离和成孔剂热驱除期间必须小心处理膜应力的变化,不造成任何膜龟裂或层离。以此方法形成的多孔膜通常具有大的孔大小分布,且最小孔在20nm范围。
已经使用CVD技术探索该成孔剂概念(详见例如美国专利6,054,206号与美国专利6,171,945号)。将容易热不稳定的有机基团会沉积在有机硅酸盐玻璃中。然后对该膜加以退火以挥发该不稳定的有机组份,形成多孔结构。还报道用电子束处理(详见例如美国专利6,737,365号)或紫外光辐照(详见美国专利申请案20040096672)来有效去除此等物质并额外加强该主体材料的交联。一般来说用这种方法可获得具有与离去的有机基团大小相当的孔的纳米多孔膜。据说该纳米多孔基质能在后续处理中可提供良好的机械与热稳定性。然而,如同其它成孔剂技术,此种CVD技术是以挥发有机物质为基础的,如果预期要去除的有机物质未完全去除,则存在除气残留物残存的问题。此外,仍然存在着如前述讨论与加工含碳氧化物膜有关的综合加工复杂性的问题。
迄今为止仍需要开发低k膜。本发明目的系创造一种用以产生多孔低k介电膜的CVD方法,该方法可以延伸至制造超低k膜。希望该膜与二氧化硅一样具有化学、机械与热稳定性。另外希望与现有技术相比较,该方法综合要求不会过于极端且昂贵。
发明的概述
本发明涉及一种将主体基质材料的多孔膜沉积在一基材上的方法,其包括数个加工循环,其中每个循环包括:
—共沉积该主体基质材料与硅;
—在共沉积之后,将该共沉积物置于包括至少一种选择性硅去除试剂的反应环境,从而使该共沉积物中的硅通过该选择性硅去除试剂优先化学去除,在该共沉积物中形成孔;
重复进行该共沉积与该选择性硅去除步骤,构成该多孔膜的厚度。
本发明还涉及一种在真空环境下在一基材上沉积主体基质材料的多孔膜的方法,其包括数个加工循环,其中每个循环包括:
—以化学气相沉积技术,在有或无等离子体强化协助之下,共沉积该主体基质材料与硅;
—在共沉积之后,将该共沉积物置于包括至少一种选择性硅去除试剂的反应环境中,从而用选择性硅去除试剂优先化学去除该共沉积物中的硅,在该共沉积物中形成孔;
重复进行该共沉积与该选择性硅去除步骤,构成该多孔膜的厚度。
本发明还涉及一种在真空环境下基于等离子体增强的化学气相沉积技术在一基材上沉积主体基质材料之多孔膜的方法,其包括:
—向一真空环境提供一基材;
—向该真空环境中导入本领域普通技术人员已知的用于促进所述主体基质材料之PECVD与硅之PECVD的化学试剂的前体;
—还向该真空环境中导入至少一种选择性硅去除试剂;
—在该真空环境中对所述前体和所述选择性硅去除试剂的混合物施加RF功率调制,以控制多个加工循环之操作,在每个调制循环过程中,先进行该主体基质材料与硅之PECVD共沉积,然后优先化学去除该共沉积物中之硅,以在该共沉积物中形成孔。
本发明总体上涉及形成多孔膜。更明确地说,本发明涉及在基材上形成多孔二氧化硅或掺杂二氧化硅膜用于形成半导体集成电路。所揭示方法使用循环方式沉积该膜。在每个循环中,首先共沉积二氧化硅与硅或掺杂二氧化硅与硅之薄层。(该共沉积膜一般被视为富含硅之氧化物或富含硅之掺杂氧化物)。然后,使该膜置于化学试剂(该化学试剂可优先从该共沉积物的二氧化硅中去除硅)中,留下多孔结构。交替重复该处理步骤以构成该膜厚度。
各层中孔大小与孔分布是由所结合的牺牲硅之数量以及该硅在该层中的分布情况决定的。每个后续沉积步骤在先前产生的多孔层上沉积一层共沉积物,随后的选择性硅去除步骤原位形成多孔结构。因此,利用本发明揭示的循环方法,通过在每个循环中改变加工条件,可在该二氧化硅膜中有利地获得所需之孔率分布。
本发明有三个显著特性:1)共沉积二氧化硅(或概括地说主体基质材料)与硅、2)在去除硅步骤过程中,将该共沉积膜置于选择性硅去除试剂中,及3)在方法上促进并优化对该共沉积与选择性硅去除步骤的控制。
作为本发明之具体实施例,该选择性硅去除试剂较佳选自分子卤化物或卤化物质,包括氟、氯、溴及其衍生物。该选择性硅去除试剂亦可为衍生自含有氢氧化钾或氢氧化四甲铵(TMAH)或乙二胺焦儿茶酚(EDP)(pyrocatecol)或其衍生物之溶液的蒸气,视需要还可混以与该蒸气不发生反应的高蒸气压的载体气体(醇)。
在本发明另一具体实施例中,促进该选择性去除硅反应的较佳试剂选自分子氟、二氟化氙及其组合物。
在本发明的较佳实施方式中,该沉积步骤采用等离子体强化的化学气相沉积(PECVD)技术。该试剂流包括一种共沉积混合物,所述混合物含有至少一种含硅前体和其它本领域已知的用于促进二氧化硅与硅或掺杂二氧化硅与硅之PECVD的其它化学试剂,及至少一种选择性硅去除试剂。
在所述较佳方法中,使用RF功率调制以促进所述共沉积与选择性去除硅之循环方法。当该RF功率位于沉积氧化硅与硅的最适水准时,进行该材料之沉积。当RF功率关闭或降至低数值时,不再发生解离(不论是发生共沉积的解离还是共沉积该硅去除试剂之解离)。此时,利用该硅去除试剂的化学作用,自该共沉积物优先去除硅,留下多孔二氧化硅结构。
以此种方法获得的多孔二氧化硅膜具有均匀分散之小尺寸孔,其与该共沉积物中分散的硅之均匀度与分布相同。该膜中的孔大小与孔率分布是由反应器室设计、该试剂混合物中组份的流量和沉积条件(诸如温度、压力、RF功率、电极间距及与进行该循环方法有关的参数(诸如加工循环频率与工作循环))所决定的。
本发明其它具体实例揭示于权利要求书。本发明总体上亦适于形成多孔掺杂的二氧化硅膜,只要该掺杂物成份不会与该选择性硅去除试剂发生明显反应即可,或者万一发生反应,剩余的反应产物有利于加强该膜性质或者是加强该膜性质所需的。同样地,在共沉积过程中将该掺杂物结合至该二氧化硅中。本发明总体上还适于形成可与硅共沉积且与该选择性硅去除试剂呈相对化学惰性的任何主体基质材料之多孔膜。
本文所述之加工方法提供获得用于制造半导体集成电路之多孔低k值介电膜的方法。该方法亦有利于制造供其它领域中之应用的其它多孔结构,所述领域包括但不局限于半导体、高级封装、能量储存与高级微系统。
附图简述
通过本发明的描述并参考附图可容易地了解本发明的教示,其中:
图1系流程图,说明共沉积二氧化硅-硅,然后选择性去除该共沉积层中之硅以形成多孔二氧化硅膜的依次交替步骤。每个循环之后,加工条件可做改变以改变该膜中孔率分布。
图2A至2I概要说明本发明循环共沉积与选择性去除硅方法形成的范例多孔膜。
图3A至3I概要说明用本发明之循环方法可制得具有不同孔率分布的范例多孔膜。
图4系概要说明加工循环频率、循环周期、工作循环,并说明范例RF功率释放波形的RF功率水准。
图5是通用循环加工流程图,用于根据硅与该膜材料共沉积然后选择性去除硅之交替重复步骤形成其它多孔膜。该通用方法主张本发明更广的范围。
发明的详细描述
本发明提出一种在基材上形成多孔二氧化硅或掺杂多孔二氧化硅膜的加工方法用于半导体集成电路制造。使用本揭示所述之特性,该方法亦总体上适于形成其它主体基质材料之多孔膜。为了简明讨论起见,本发明人将说明焦点主要放在多孔二氧化硅膜上。
根据本发明,该方法需要循环加工流程以形成该膜。在每个循环中,先共沉积二氧化硅与硅或掺杂二氧化硅与硅之薄层。(该共沉积膜一般被视为富含硅之氧化物或富含硅之掺杂氧化物)。然后,自该共沉积物选择性去除硅,以产生多孔氧化硅结构。交替重复该加工步骤以构成该膜厚度。本说明中,将更详细描述本发明条件与实施方式。
为了明暸起见,本文中膜中的“硅”是指在共沉积过程中混入所述膜中与二氧化硅松散键合的硅,诸如填隙的硅或与氢或羟基键合的硅,或共价键合于硅的硅,或元素硅共沉积。本文中膜中的“二氧化硅”是指含有完全或部分与氧键合之硅的任何经氧化之硅。此外,除非另有说明,否则术语“二氧化硅”可以互换使用,用以指经氧化之硅,它可以是未掺杂的或掺杂有其它成份。富含硅之氧化物被视为氧化硅与硅之共沉积物。术语“主体基质”是指多孔结构的固体物质,且术语“主体基质材料”是指由该多孔结构所制成的材料。
图1显示该循环方法的简化流程图,图2A至2I是该经加工膜在膜形成不同阶段的剖面图。此等横剖面图系经简化仅用于说明的目的,不应视为该共沉积膜组份的实际排列。
本发明方法是从步骤102由位于反应室中的基材开始的。图2A中,该起始基材图标为硅晶圆202,并且已对其进行预处理。预处理所得之结果系由在硅晶圆上之组合结构204概要图标。204的表面是半导体装置制造过程中经处理的晶圆进入低k值电介质沉积段的典型的起始表面。表面204还具有其它用途,包括硅晶圆的裸表面。
在步骤204中,设定起始加工参数以共沉积二氧化硅与硅之薄层。在步骤106中,进行沉积且产生共沉积膜220,其包括分散在二氧化硅208中的硅206。此系概要图示于图2B。
在下一个步骤108中,自共沉积物220选择性去除硅206。图2C显示该仅剩下二氧化硅208之开口氧化硅基质230的横剖面。
通常需要一个以上的循环以形成所需膜厚度,因此在下一循环中交替重复步骤106与108。通过下一循环中之步骤106,在先前产生之开口氧化硅基质层230上面形成相同之共沉积层220,封闭该开口部分以形成孔215,如图2D所示。图2E显示在后续选择性去除步骤108之后,共沉积物220中的硅206被去除。该重复沉积与选择性去除步骤形成较厚之多孔二氧化硅膜。图1中之步骤110判定是否已达到所需之膜厚度。若未达到所需膜厚度,则重复相同之依次共沉积与选择性去除硅步骤,以构成该多孔膜的厚度。图2A至2I显示完成四个循环的结果。视需要可重复更多次循环。该加工在步骤120结束。
每层中的孔大小与孔分布是由硅在共沉积物中的分布与所结合之牺牲硅数量决定的。就此特征来看,该循环方法亦可机动地用于制得具有不同孔率分布的多孔膜。图3A至3I概要说明可在相同之起始表面204上制得的不同孔率膜。层238示意性地显示包含比层220更少的硅,在去除硅步骤108之后,层238会形成孔少于层230的多孔层240。须注意的是,图3a至3I表示的孔率分布仅出于说明的目的,并不限制本发明可制得之各种孔率分布。
如图1中之流程图所示,每个循环之后,可在步骤114时重新选择加工条件,以沉积不同的氧化硅与硅共沉积膜。不同的硅加入量会改变沉积层之孔率。图3B与3I显示若有需要,沿该多孔膜的厚度方向可以形成致密氧化硅膜。在此情况下,在共沉积步骤中不需要掺入硅。
由于该多孔膜完全是在原位形成的,因此作为本发明另一具体实施例,视需要可在该循环加工之前或之后插入任何其它制造加工步骤。如图3I所示之层250,相似的致密衬层、覆盖层、蚀刻中止层或任何其它加工理层可与该多孔膜共同沉积,而毋须打破真空。这对于例如形成双重波纹结构方法的处理整体性而言特别有利。
就本发明而言,沉积后无成孔剂待挥发。多孔二氧化硅基质在化学上与致密的二氧化硅相似。该精密分布的孔提供良好结构完整性与热稳定性。以此方法可以获得广范围的低k值电介质。
本发明本质系1)共沉积二氧化硅(即主体基质材料)与硅、2)在选择性去除硅步骤过程中将该共沉积膜置于选择性硅去除试剂中,及3)促进循环加工以调整该共沉积与该选择性去除硅步骤。
使用硅作为牺牲材料形成该多孔膜是本发明的关键。与硅共沉积提供了二氧化硅模板,使多孔结构可由该模板形成。该选择性硅去除试剂使得该结构得以形成。在硅产业中已详知有某些化学试剂可容易地与硅发生化学反应,但不会与其它材料反应。因此,我们可以利用这些不同的化学活性性质以促进选择性去除硅步骤。
就本发明而言,该选择性硅去除试剂较好选自分子卤化或卤化的物质,包括氟、氯、溴及其衍生物。该选择性硅去除试剂亦可选自由包含氢氧化钾、氢氧化四甲铵(TMAH)、乙二胺焦儿茶酚(EDP),或其类似物或其衍生物溶液所衍生之蒸气,视需要所述蒸气还可混以不会与该蒸气起反应的高蒸气压载体气体(例如醇)。
就本发明而言,较佳之选择性硅去除试剂系选自分子氟(F2)、二氟化氙(XeF2)与其组合物。
本发明另一重要方面系促进该循环加工以调整该共沉积与选择性去除硅步骤。视该膜所需性质,有许多方法可实施本发明。本领域的普通技术人员可知在不违背本发明精神的情况下有其它沉积方法及数种进行该循环的加工形式。
本发明较佳具体实施例中,该共沉积是使用等离子体强化的化学气相沉积技术实现的。使用具备13.56MHz之对称平行板构造的射频(RF)源之PECVD反应器以在加工室中产生沉积用之等离子体。该试剂流包括共沉积试剂混合物与一或多种选择性硅去除试剂。使用间歇RF功率以调制该共沉积与该选择性去除硅步骤。在这两个步骤过程中向加工室供应相同试剂流。
图4说明RF功率调制控制中之重要特性。为了简化说明,该图中以矩形脉冲列表示该RF功率波形。实际上,亦可使用其它波形。该波形可由循环频率、循环周期及工作循环(duty cycle)表征。所述循环周期是完成一个处理循环中所有处理步骤所需的持续时间。所述循环频率是循环周期的倒数,而工作循环是循环周期内发生共沉积之时间的比例。
图4中,本发明人显示该处理循环系由共沉积与选择性去除硅步骤所组成。在共沉积过程中,该RF功率系以Pd运行。在此功率水准下,该RF功率高得足以解离用于共沉积二氧化硅与硅二者的前体。该循环其余时间,关闭RF功率或设定在低水准从而中止沉积。不仅使该功率水准低到使二氧化硅与硅沉积用的前体不会解离,还必须使功率低于会解离所述选择性硅去除试剂的功率水准Pf。图4任意说明该选择性硅去除步骤期间功率水准设为零的波形。
为了促进同时PECVD形成二氧化硅与硅,该共沉积试剂混合物必须包括至少一种含硅前体与一种含氧前体。由于熟悉PECVD技术之人士了解有许多合适的化学物质组合,因此在此不再详细描述前体的选择。不过,本发明人给出用于本发明较佳方法中之下列共沉积混合物。该较佳共沉积混合物包括硅烷(SiH4)、一氧化二氮(N2O),具有或不具原硅酸四乙酯(TEOS)、具有或不具氢(H2)及氩(Ar)或其它惰性气体。
如常规的富含硅之PECVD氧化硅那样,该二氧化硅—硅共沉积物将包含二氧化硅与某些间隙硅原子,硅共价彼此键合,并且硅与氢或羟基等弱键合。当将该共沉积物置于选择性硅去除试剂中时,该试剂会化学性蚀刻该硅,同时氧化硅实质上保持完整。该化学反应的进行速率由加工温度与该处理室中所述选择性硅去除试剂浓度而定。
在本发明人较佳实施方式中,在共沉积和选择性硅去除步骤过程中向该处理室连续进料相同试剂混合物。因此,该共沉积反应是在该选择性硅去除试剂的存在下发生的。通过开启RF功率,在该等离子体反应中该选择性硅去除试剂会解离并沉淀。其甚至会掺入该膜中。例如,若使用氟作为选择性硅去除试剂,在共沉积过程中亦会形成某些氟化的氧化物。(该氟化的氧化物有利于进一步降低该二氧化硅的介电常数)。此外,视该共沉积加工条件,这些基团会蚀刻掉某些已沉积之硅与氧化物。由所有此等反应来看,虽然在进料流中必须存在合理浓度之选择性硅去除试剂以促进用合理速率选择性去除硅,但重要的是使该浓度保持在低于共沉积条件下的浓度从而净结果是在共沉积步骤过程中发生沉积。
除了该沉积与选择性去除硅加工条件之外,该循环频率与该工作循环亦在形成该多孔膜中扮演重要角色。该选择性硅去除步骤的持续期间通常设定在长得足以去除在同一循环中所沉积之部分或所有硅。若在一个循环中沉积太厚的共沉积层,则选择性硅去除试剂必须通过厚的共沉积物以去除硅。此方法无效率,有时其甚至无法使小分子(例如氟)远程扩散进入所述材料进行反应。另一方面,沉积薄层也不一定是适当的,尤其是需要结合大量硅以构成高孔率膜时。太薄的层在去除硅之后会形成稀少的氧化硅基质。下一循环中之共沉积物会填满该等间隙。因此,该加工循环频率与该工作循环必须根据所述共沉积和选择性去除硅的速率设定,使得可获得该膜所需之孔大小与孔率分布。
作为另一具体实施例,本发明循环方法可用以制造具有纳米孔径的多孔二氧化硅或掺杂二氧化硅膜。其容量说明于下列实施例中。若以/min之表观速率共沉积硅并以/min之表观速率共沉积二氧化硅,且若该加工循环频率系3Hz、工作循环为50%(即,共沉积过程为0.167秒),则每个循环内仅形成数埃的共沉积物。所述表观沉积速率可由既定时间间隔内沉积在该膜中之二氧化硅与硅相对数量计算求得。例如,可由SIMS(次级离子质谱)分析与FTIR(傅利叶转换红外线)吸收光谱测得该沉积物中之硅与氧的相对量估算该共沉积层的氧化硅与硅相对量。在此种条件下,该分散硅的大小与该共沉积物层的厚度具有相同的数量级。当该硅原子被选择性去除时,将会发生相同大小的分散开口。在下一循环中形成的共沉积物会覆盖此等开口,并封闭下方空间。该方法可制造具有有利纳米大小孔的膜。因此,以该方法可制得孔大小自0.3nm至50nm且孔率自0.5%至90%的多孔膜。
总结上述进行该PECVD加工的条件,本发明人给出下列具体实施例。该较佳试剂流包括硅烷、一氧化二氮,具有或不具原硅酸四乙酯(TEOS),及具有或不具氢或氩或其它惰性气体。该硅烷对一氧化二氮流量比介于0.005与100间。该进料流亦包含0.1至50%分子氟或二氟化氙或其组合物。在沉积过程中,该PECVD室压力保持在介于0.01乇与15乇之间,电极间距介于0.1英时与3英时间,该基材温度介于25℃与500℃间,且该RF功率密度介于0.01W/cm2与5W/cm2。该选择性去除硅步骤是在与共沉积步骤相同之压力与温度下进行的。施加13.56MHz RF功率,加工循环频率为0.0005Hz至500Hz,共沉积工作循环为1%至99%。为求清楚起见,本文将对称平行板反应器的RF功率密度界定为RF功率除以二倍的阴极或阳极面积。
更佳情况系,该PECVD方法采用硅烷对一氧化二氮流量比自0.01至30之进料流。该进料流亦包含1%至30%分子氟、二氟化氙或其组合物。在沉积过程中,该加工室的压力保持在0.1乇与10乇之间,电极间距介于0.3英时与1.5英时之间,基材温度保持在300℃与400℃之间,而RF功率密度介于0.2W/cm2与1.0W/cm2。施加13.56MHz RF功率,加工循环频率为0.1Hz至10Hz,共沉积工作循环自5%至70%。
不待言,本发明此较佳实施方式可容易地在装有RF功率调制控制的PECVD系统上进行。若该PECVD系统上没有所述RF功率调制控制,可在循环加工过程中使用一组加工步骤以仿真循环RF功率切换。或者,可以修改该RF功率输送硬件使之具有计时电路,或修改该系统以提供一机构,从而释放供沉积用之RF功率可以间歇地关闭或降至前述之低水准。另一选择是,可将硅去除试剂与共沉积试剂混合物作为单一的试剂加料流一同导入用于共沉积与硅去除步骤。
另一种在常规PECVD反应器上实施本发明的方式是以两个独立处理程序分别进行该共沉积与选择性硅去除步骤。此二加工步骤可在同一加工室中交替进行,以仿真循环处理。虽然如同常规PECVD方法进行该共沉积,但是在选择性硅去除步骤过程中不施加RF功率。该共沉积试剂与该选择性硅去除试剂可于其各自加工期间分别加入。
或者,在设计具有多个依次加工段的加工室中(详见例如美国专利6,007,675号),实施本发明的另一种方式系在该共沉积步骤之后将该基材移到同一反应器的一个单独的加工段。仅对于进行共沉积的加工段施加RF功率。此情节中,在同一反应器中,以相同进料流但在不同加工段上同时一并处理至少两片晶圆(一片进行共沉积,一片进行选择性去除硅)。
另一实施本发明的方法是在一组设备(a cluster tool)的分立反应室中进行该共沉积与选择性硅去除步骤。将基材在两个反应室之间移送使之依次进行共沉积与选择性去除硅加工。
对于分立的反应室加工,可使用任何能形成共沉积物的沉积方法进行本发明的循环处理。某些方法可能是物理气相沉积、热化学气相沉积、旋涂与其它方法。事实上,只要能形成二氧化硅-硅共沉积物并且能将该共沉积物置于含有选择性硅去除试剂环境下以去除该硅,所述实施方式可扩展到任何实施方式。视需要可以重复相同处理顺序以形成该多孔膜的厚度。
在所有前述实施方式中,重要的是必须注意在加工循环频率与工作循环方面它们不完全是相同的。因此,各种实施方式的适用性取决于具体的加工化学与需要选择之加工条件。本发明人相信在PECVD构造中使用RF振幅调制可以提供最灵活的手段,稳定地控制该共沉积与选择性去除硅的环境,以有效率进行本发明。
最后,本文的说明并未区分用于形成多孔二氧化硅膜或形成多孔掺杂的二氧化硅膜的方法,实施多孔掺杂二氧化硅膜有例如多孔掺杂氟之二氧化硅(FSG)、多孔掺杂碳之二氧化硅、多孔掺杂磷之二氧化硅(PSG)、多孔氢硅倍半氧烷(HSQ)、多孔甲基硅倍半氧烷(MSQ)、多孔掺杂硼之二氧化硅(BSQ)、多孔掺杂硼—磷之二氧化硅(BPSQ)等等。事实上,本文并未区分用于形成其它多孔膜之方法,该等其它多孔膜有例如多孔氮化硅、多孔氧氮化硅、多孔碳化硅、多孔氮化硼、多孔氧氮化硼、多孔氧化铝、多孔氮化铝、多孔氧氮化铝等等。重复地说,本发明显著之处系与硅共沉积及选择性去除牺牲硅。因此,本发明范围不仅涵括形成多孔二氧化硅膜,亦涵括对于该选择性硅去除试剂呈相对惰性的主体基质材料(无机或有机或其组合物)的其它多孔膜。即使某些组成膜材料会与该选择性硅去除试剂反应,但只要形成多孔膜,此方法即在本发明范围内。
实例之一是以本发明方法通过在二氧化硅—硅膜中共沉积含碳物质,可形成多孔掺杂碳之二氧化硅膜。使用诸如氟之选择性硅去除试剂会侵蚀该膜中的部分碳,在该去除硅步骤过程中形成氟碳化合物物质。根据该膜组成与该加工条件,该反应产物可具有挥发性且可与该硅之氟化物一同去除,或其可为非挥发性并在该膜中留下氟碳化合物组份。(须注意该C—F键有利于对该膜提供疏水性质)。对于该膜的需求有待决定,但只要依照硅共沉积和选择性去除硅的基本特性来形成多孔膜,则该方法在本发明范围内。
其后,在图5中,本发明人给出使用本发明基本概念形成多孔膜的通用流程图。与图1所示加工流程相似,但是代替步骤106的是,在步骤506中该共沉积包括所有构成膜材料与硅。步骤508中,该选择性硅去除试剂自该共沉积物去除硅。该膜中的其它成份亦与该选择性硅去除试剂反应,但构成所需之主体基质材料的成份必须对该选择性硅去除试剂呈相对惰性。用于二氧化硅膜的相同具体实施例可适用于此等实例。
总结地说,可进行本发明以提供用于半导体集成电路制造之具有宽范围低介电常数的多孔二氧化硅膜与掺杂的二氧化硅膜。相同的循环加工方法可以更广泛扩展至提供其它使用硅作为牺牲材料并使用至少一种选择性硅去除试剂该硅以形成多孔膜的多孔膜。本方法有利于用在许多用途,包括但不局限于半导体、高级封装、能量储存与高级微系统。
虽然上述说明有关本发明具体实施例,但在不违背本发明基本范围之下可想出其它与另外的本发明具体实施例。例如,使用在仟赫范围的低RF频率或是在13.56MHz以外之兆赫频率范围所产生的等离子体、使用混合频率RF功率,或以不同产生等离子体方式(不论是电容耦合或电感耦合或去耦)均应视为本发明中具体实现之同一PECVD实施方法的不同改造方式。另外须注意的是该循环加工的变化,诸如添加任何沉积前与沉积后处理,包括等离子体、电子束、离子束、紫外线、化学或热处理步骤以活化曝露之膜表面或改良该膜性质,此等均不违背本发明精神。沉积额外材料以加强该膜性质或促进硅去除反应亦不违背本发明精神。
Claims (37)
1.一种将主体基质材料的多孔膜沉积在一基材上的方法,其包括数个加工循环,其中每个循环包括:
—共沉积该主体基质材料与硅;
—在共沉积之后,将该共沉积物置于包括至少一种选择性硅去除试剂的反应环境,从而使该共沉积物中的硅通过该选择性硅去除试剂优先化学去除,在该共沉积物中形成孔;
重复进行该共沉积与该选择性硅去除步骤,构成该多孔膜的厚度。
2.如权利要求1所述的方法,其特征在于该共沉积步骤是以选自旋涂、热化学气相沉积、物理气相沉积的沉积技术,以及以在射频至微波频谱范围内的电磁能量辅助的沉积技术进行的。
3.一种在真空环境下在一基材上沉积主体基质材料的多孔膜的方法,其包括数个加工循环,其中每个循环包括:
—以化学气相沉积技术,在有或无等离子体强化协助之下,共沉积该主体基质材料与硅;
—在共沉积之后,将该共沉积物置于包括至少一种选择性硅去除试剂的反应环境中,从而用选择性硅去除试剂优先化学去除该共沉积物中的硅,在该共沉积物中形成孔;
重复进行该共沉积与该选择性硅去除步骤,构成该多孔膜的厚度。
4.一种在真空环境下基于等离子体增强的化学气相沉积技术在一基材上沉积主体基质材料之多孔膜的方法,其包括:
—向一真空环境提供一基材;
—向该真空环境中导入本领域普通技术人员已知的用于促进所述主体基质材料之PECVD与硅之PECVD的化学试剂的前体;
—还向该真空环境中导入至少一种选择性硅去除试剂;
—在该真空环境中对所述前体和所述选择性硅去除试剂的混合物施加RF功率调制,以控制多个加工循环之操作,在每个调制循环过程中,先进行该主体基质材料与硅之PECVD共沉积,然后优先化学去除该共沉积物中之硅,以在该共沉积物中形成孔。
5.如权利要求4所述的方法,其特征在于该调制循环中一段时间内的RF功率水准设定为同时适于该主体基质材料之沉积与硅之沉积,而在同一循环中以后的时间段内则将该RF功率水准关闭或降到低于选择性硅去除试剂发生任何沉积或解离所需之水准。
6.如权利要求1、3或4所述的方法,其特征在于所述主体基质材料是无机或有机材料,或其组合物。
7.如权利要求1、3或4所述的方法,其特征在于所述主体基质材料选自:二氧化硅、掺杂碳之二氧化硅、掺杂氟之二氧化硅(FSG)、掺杂硼之二氧化硅(BSG)、掺杂磷之二氧化硅(PSG)、掺杂硼磷之二氧化硅(BPSG)、掺杂锗之二氧化硅(GSG)、氢硅倍半氧烷(HSQ)、甲基硅倍半氧烷(MSQ)、氮化硅、氧氮化硅、碳化硅、氧化铝、氮化铝、氧氮化铝、氮化硼、氧氮化硼,及其组合物。
8.如权利要求1、3或4所述的方法,其特征在于所述选择性硅去除试剂选自包括氟、氯、溴及其衍生物的分子卤化物或卤化物质。
9.如权利要求1、3或4所述的方法,其特征在于所述选择性硅去除试剂选自分子氟、二氟化氙与其组合物。
10.如权利要求1、3或4所述的方法,其特征在于该选择性硅去除试剂是一种溶液的蒸气,所述溶液含有至少一种选自下列的化学物质:氢氧化钾、氢氧化四甲铵(TMAH)、乙二胺焦儿茶酚(EDP)及其衍生物,还可任选地混以对该选择性硅去除试剂呈化学惰性之高蒸气压载体气体。
11.如权利要求1或3所述的方法,其特征在于该共沉积与该选择性硅去除步骤是在同一组装置的分立加工室中进行的。
12.如权利要求1或3所述的方法,其特征在于所述共沉积与该选择性硅去除步骤是在同一加工室中进行的。
13.如权利要求3所述的方法,其是在一PECVD系统中使用配方程序进行的,包括在该配方程序中之一组加工步骤,以促进该共沉积与该选择性硅去除步骤之循环进行。
14.如权利要求3所述的方法,它是在一多段反应器中的多个独立段中进行的,所述共沉积步骤是通过用RF功率的PECVD在其中的一个独立段中进行的,而所述选择性硅去除步骤是在无RF功率的另一个独立段中进行的。
15.如权利要求4所述的方法,其是在装有RF功率调制能力之PECVD系统中进行的。
16.如权利要求4所述的方法,其是在一PECVD系统中进行的,所述PECVD系统经改良以提供可以控制RF功率水准变化的机构,以促进需要RF功率之共沉积步骤与不需要RF功率的选择性硅去除步骤的循环运行,但是所述不需要RF功率的选择性硅去除步骤能使RF功率水准低于选择性硅去除剂解离所需的RF功率水准。
17.如权利要求4所述的方法,其特征在于该RF功率是以0.0005Hz至500Hz之加工循环频率输出的,共沉积工作循环自1%至99%,所述工作循环是循环周期内发生共沉积之时间的比例。
18.如权利要求3或4所述的方法,其特征在于该PECVD条件包括RF激励频率为100kHZ至100MHz的单频模式。
19.如权利要求3或4所述的方法,其特征在于该PECVD条件包括RF激励频率为100kHZ至100MHz的混频模式。
20.如权利要求3或4所述的方法,其特征在于该共沉积是以介于0.01与5W/cm2之RF功率密度进行的。
21.如权利要求3或4所述的方法,其特征在于该共沉积是以保持0.1与3英时之电极间距进行的。
22.如权利要求3或4所述的方法,其特征在于该共沉积是以保持在介于25℃与500℃间之基材温度进行的。
23.如权利要求3或4所述的方法,其特征在于该共沉积是以维持在介于0.01与15乇之加工室压力下进行的。
24.如权利要求1或3所述的方法,其特征在于该选择性去除硅的步骤是以维持在介于25℃与500℃间之温度下进行的。
25.如权利要求1或3所述的方法,其特征在于该选择性去除硅的步骤是以维持在介于0.01与700乇的加工室压力下进行的。
26.如权利要求3或4所述的方法,其特征在于该共沉积试剂混合物包括硅烷与一氧化二氮,其流量比介于0.005与100间,并任选包括可改善共沉积期间之离子撞击的气体,该气体选自氩、氢、氦或其组合物。
27.如权利要求1或3所述的方法,其特征在于该加工室中之选择性硅去除试剂浓度介于0.1%与100%。
28.如权利要求1或3所述的方法,其特征在于该选择性硅去除步骤之试剂流包括浓度介于0.1%与100%之分子氟。
29.如权利要求4所述的方法,其特征在于该试剂混合物中之选择性硅去除试剂的浓度介于0.1%与50%。
30.如权利要求4所述的方法,其特征在于该试剂混合物包括浓度介于1%与30%之分子氟。
31.如权利要求1、3或4所述的方法,其特征在于共沉积与选择性去除硅循环中的一者或多者使用不同的加工条件,以改变该膜之孔率分布。
32.如权利要求1、3或4所述的方法,用于制造孔大小自0.3nm至50nm的多孔膜。
33.如权利要求1、3或4所述的方法,用于制造孔率自0.5%至90%的多孔膜。
34.如权利要求1、3或4所述的方法,它还包括至少一个在该方法选定循环间隔之间进行的其它加工步骤,所述加工步骤选自用等离子体、电子束、离子束、电磁辐射、化学或热辐照进行处理。
35.如权利要求1、3或4所述的方法,它还包括在毋须中断真空之情况下,于同一沉积室中在沉积该多孔膜之前于该基材上沉积一衬垫层。
36.如权利要求1、3或4所述的方法,它还包括在毋须中断真空之情况下,于同一沉积室中在多孔膜上面沉积一覆盖层。
37.如权利要求1、3或4所述的方法,它还包括在毋须中断真空之情况下,于同一沉积室中在该多孔膜上面沉积一低k蚀刻中止层。
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