KR102266360B1 - 반도체 구조물 및 디바이스 그리고 선택적 에피택셜 프로세스를 사용한 이의 형성 방법 - Google Patents
반도체 구조물 및 디바이스 그리고 선택적 에피택셜 프로세스를 사용한 이의 형성 방법 Download PDFInfo
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Abstract
반도체 구조물, 디바이스들 및 그 구조물 및 디바이스의 형성 방법이 개시된다. 예시적인 구조물들은, CMOS 구조물 및 디바이스들을 기판에 형성하기 위하여 NMOS (n-channel MOS) 및 PMOS (p-channel MOS) 디바이스들 양자 모두를 포함할 수 있는 멀티-게이트 또는 FinFET 구조물들을 포함한다. 디바이스들은, 선택적 에피택시 및 얕은 트렌치 격리 기법들을 사용하여 형성될 수 있다.
Description
본 개시는 일반적으로 반도체 구조물 및 디바이스에 관한 것이다. 보다 상세하게는, 본 개시는 선택적 에피택셜 성막 프로세스를 사용하여 형성된 하나 이상의 층들을 포함하는 반도체 구조물 및 디바이스에 관한 것이다.
FinFET 디바이스들을 포함하고 일반적으로 FinFET 디바이스들로도 지칭되는 멀티게이트 반도체 디바이스들은 최근 더 많이 주목받고 있는데, 왜냐하면, 이 디바이스들이 유사한 단일 게이트/평면형 디바이스들에 비하여 전력 단위 당 더 높은 성능을 제공하기 때문이다. 통상적인 금속 산화물 반도체 (MOS) 디바이스의 경우, 디바이스의 성능을 증가시키기 위한 노력으로 디바이스 지오메트리가 계속 축소됨에 따라, 오프 상태 누설 전류와 같은 쇼트 채널 효과가 증가된다. 결국, 누설은 디바이스에 대한 아이들 (idle) 전력 요구를 증가시킨다.
FinFET 디바이스는, 누설 전류를 완화시킬 수 있는 게이트 구조를 포함한다. 감소된 누설 전류는, 디바이스가 오프 상태에 있을 때 전력 소비를 감소시킬 뿐만 아니라, 디바이스의 임계 전압을 감소시킬 수도 있는데, 이는 증가된 스위칭 속도 및 감소된 동작 전력 소비로 이어질 수 있다.
FinFET 디바이스들은 바람직하게는 디바이스의 채널 영역에서 게르마늄을 포함할 수도 있다. 채널 영역에서의 게르마늄의 포함은 전하 캐리어들의 이동도를 증가시킬 수 있고, 이는 결국 증가된 디바이스 성능으로 이어질 수 있다. 불행하게도, 채널 영역에서 게르마늄의 포함은 CMOS (complimentary MOS) 디바이스내에 통합하기 힘든 것으로 밝혀졌다. CMOS FinFET 디바이스들을 형성하기 위한 다양한 접근법들은 디바이스의 얕은 트랜치 격리 구조를 따라 많은 결함들을 감소시키기 위한 종횡비 트랩핑 (aspect ratio trapping) 의 사용을 포함한다. 하지만, 그러한 프로세스들은 일반적으로, 에피택셜 재료로 좁은 (예를 들어, 폭이 10 nm 미만인) 트렌치를 충전하는 것을 필요로 하는데, 이는 어렵다. 또한, 그러한 디바이스들에서 버퍼 리세스 제어는 바람직한 것에 못미칠 수 있으며, 바람직한 것에 못미치는 채널 높이 균일성 (channel height uniformity) 을 초래한다. 따라서, 상대적으로 균일한 채널 높이로 제조가 상대적으로 용이한, 향상된 구조, 디바이스 그리고 그 구조 및 디바이스의 형성 방법이 요망된다.
본 개시의 개요
본 개시의 다양한 실시형태들은, 반도체 구조물 및 디바이스 그리고 그 구조물 및 디바이스의 형성 방법에 관한 것이다. 보다 구체적으로는, 본 개시는 멀티게이트 또는 FinFET 구조 및 디바이스 그리고 이의 형성 방법에 관한 것이다. 본 개시의 다양한 실시형태들이 종래 기술의 방법들의 결점들을 다루는 방식들은 이하에서 더 자세히 논의되지만, 일반적으로, 본 개시는, CMOS 구조 및 디바이스를 형성하기 위하여 NMOS (n-channel MOS) 및 PMOS (p-channel MOS) 디바이스들 양자 모두를 포함할 수 있는 FinFET 구조 및 디바이스를 제공한다.
본 개시의 예시적인 실시형태들에 따르면, 반도체 구조물의 형성 방법은, 실리콘을 포함하는 기판을 제공하는 단계, 상기 기판 위에 놓이는 Si1-xGex (식중, x는 0 내지 약 0.8 또는 0 내지 약 0.5 의 범위이다) 를 포함하는 버퍼 층을 형성하는 단계, 제 1 선택적 에피택셜 프로세스를 사용하여, 상기 버퍼 층의 표면 위에 놓이는 실리콘 - 예를 들어 Si1-zGez (식중, z는 (예를 들면, NMOS 디바이스에 대해) 0 내지 약 0.7의 범위이다) - 을 포함하는 제 1 피쳐를 형성하는 단계, 및 제 2 선택적 에피택셜 프로세스를 사용하여 Si1-yGey (식중, y는 (예를 들면, PMOS 디바이스에 대해) 약 0.1 내지 1의 범위이다) 를 포함하는 제 2 피쳐를 상기 표면 상에 형성하는 단계를 포함한다. 아래에 더 자세히 제시된 바처럼, 이들 실시형태들에 따라 형성된 구조들은 기판 상에 CMOS FinFET 디바이스들 및 구조들을 형성하는데 적합하다. 이들 실시형태들의 다양한 양태들에 따르면, 제 1 피쳐 또는 영역은 버퍼 층에서 p 웰 영역 (well region) 위에 놓이게 형성되고 제 2 피쳐 또는 영역은 버퍼 층에서 n 웰 영역 위에 놓이게 형성된다. 이들 실시형태들의 다른 양태들에 따르면, 제 1 피쳐들은, 하드 마스크를 성막하고, 하드 마스크를 패터닝하고, 하드 마스크에서 개구들을 형성하는데 적합한 에천트를 사용하여 하드 마스크를 에칭하고, 선택적 에피택셜 기법들을 사용하여 피쳐를 형성하는 것에 의해 형성된다. 제 1 피쳐들이 형성된 후에, 하드 마스크는 적합한 에천트를 사용하여 제거된다. 제 2 피쳐들은 동일하거나 유사한 기법들을 사용하여 형성될 수도 있다. 이들 실시형태들의 다른 양태들에 따르면, 하드 마스크는 실리콘 산화물 또는 실리콘 질화물 재료로 형성된다. 또한 다른 양태들에 따르면, 제 2 피쳐들을 위한 하드 마스크를 형성하는 단계는, 제 1 피쳐와 제 2 피쳐 사이에 갭이 형성되도록 - 예를 들어, 약 2nm ∼ 50nm 또는 약 10 nm 범위일 수도 있는 공간이 디바이스의 부분을 형성하는 구조물의 제 1 과 제 2 피쳐들 사이에 형성되도록 제 1 피쳐 위 적어도 일 측에 돌출하는 하드 마스크를 형성하는 단계를 포함한다. 예시적인 방법들은 또한, 버퍼 층 및 제 1 및 제 2 피쳐들을 사용하여 핀 (fin) 또는 돌기 (protrusion) 를 형성하는 단계를 포함할 수도 있다. 이들 경우들에서, 방법은, 제 1 피쳐 및 제 2 피쳐를 에칭하여, 실리콘을 포함하는 하나 이상의 핀들 및 Si1-yGey (식중, y는 (예를 들어, PMOS 디바이스에 대해) 약 0.1 내지 1 범위이다) 또는 Si1-zGez (식중, z 는 (예를 들어, NMOS 디바이스에 대해) 0 내지 약 0.7 의 범위이다) 를 포함하는 하나 이상의 핀들을 형성하는 단계, 약 400℃ 미만의 온도로 절연 재료를 성막하는 단계, 및 절연 재료의 일부를 제거하는 단계를 추가적으로 포함한다. 이들 실시형태들의 다양한 양태들에 따르면, 절연 재료는 실리콘 산화물이고 절연 재료를 성막하는데 사용되는 전구체들은 H2Si[N(C2H5)2]2 및 O2 플라즈마를 포함한다.
본 개시의 추가 실시형태들에 따르면, 반도체 구조물은 실리콘을 포함하는 기판, 상기 기판 위에 놓이는 Si1-xGex (식중, x 는 0 내지 약 0.8 또는 0 내지 약 0.5 이다) 를 포함하는 버퍼 층, 상기 버퍼 층 내에 형성되는 p 웰 영역, 상기 버퍼층 내에 형성되는 n 웰 영역, 상기 p 웰 영역 및 실리콘 (예를 들어, Si1-zGez (식중, z 는 0 내지 약 0.7 의 범위이다)) 을 포함하는 층을 이용하여 형성되는 하나 이상의 핀 구조들, 상기 n 웰 영역 및 Si1-yGey (식중, y 는 약 0.1 내지 1 의 범위이다) 를 포함하는 층을 이용하여 형성되는 하나 이상의 핀 구조들, 및 상기 버퍼 층의 일부 위에 놓이게 형성되는 절연 층을 포함한다. 여기에 기재된 구조들은 전술된 방법들을 사용하여 형성될 수 있다. 예를 들어, 하나 이상의 절연 층들이, 예를 들어 H2Si[N(C2H5)2]2 및 O2 플라즈마를 이용하는 등, 약 400℃ 미만의 온도에서 형성될 수도 있다.
본 개시의 추가 양태들에 따르면, 반도체 구조물은, 실리콘을 포함하는 기판, 상기 기판 위에 놓이는 Si1-xGex (식중 x 는 0 내지 약 0.8 또는 0 내지 약 0.5 의 범위이다) 를 포함하는 버퍼 층, 상기 버퍼 층 위에 놓이는 실리콘 (예를 들어, Si1-zGez (식중, z 는 0 내지 약 0.7 의 범위이다)) 을 포함하는 제 1 피쳐, 상기 버퍼 층 위에 놓이고 상기 제 1 피쳐와 동일 표면상의 Si1-yGey (식중, y 는 약 0.1 내지 1 의 범위이다) 를 포함하는 제 2 피쳐를 포함한다. 이들 실시형태들의 예시적인 양태들에 따르면, 예를 들어, 약 2 ∼ 50 또는 약 10 또는 50 nm 미만의 길이가 제 1 피쳐와 제 2 피쳐를 분리시킨다. 이들 구조들은, 여기에 기재된 방법들을 사용하여 형성될 수도 있다.
본 개시의 또 추가의 예시적인 실시형태들에 따르면, CMOS 디바이스는 실리콘을 포함하는 기판, 상기 기판 위에 놓이는 Si1-xGex (식중, x 는 0 내지 약 0.8 또는 0 내지 약 0.5 이다) 를 포함하는 버퍼 층, 상기 버퍼 층 내에 형성되는 p 웰 영역, 상기 버퍼층 내에 형성되는 n 웰 영역, 상기 p 웰 영역 및 실리콘 (예를 들어, Si1-zGez (식중, z 는 0 내지 약 0.7 의 범위이다)) 을 포함하는 층을 이용하여 형성되는 하나 이상의 핀 구조들, 상기 n 웰 영역 및 Si1-yGey (식중, y 는 약 0.1 내지 1 의 범위이다) 를 포함하는 층을 이용하여 형성되는 하나 이상의 핀 구조들, 및 상기 버퍼 층의 일부 위에 놓이게 형성되는 절연 층을 포함한다.
CMOS 디바이스를 형성하는 예시적인 방법들은 여기에 기재된 바처럼 반도체 구조물을 형성하는 방법을 포함한다. CMOS 디바이스를 형성하는 방법은 적합하게는 그러한 디바이스를 형성하는데 통상적으로 사용되는 추가 성막, 에치, 및 다른 프로세스들을 포함할 수도 있다.
본 개시의 예시적인 실시형태들의 보다 완전한 이해는, 다음의 예시적인 도면들과 연결하여 고려될 때 상세한 설명 및 청구항들을 참조함으로써 도출될 수도 있다.
도 1은 본 개시의 예시적인 실시형태들에 따른 기판을 도시한다.
도 2는 본 개시의 다른 예시적인 실시형태들에 따른 기판 위에 놓여 있는 버퍼 층을 포함하는 구조를 예시한다.
도 3은 본 개시의 예시적인 실시형태들에 따른 버퍼 층내에 형성된 p 웰 영역 및 n 웰 영역을 포함하는 구조를 도시한다.
도 4는 본 개시의 예시적인 실시형태들에 따른 버퍼 층 위에 놓인 패터닝된 하드 마스크를 포함하는 구조를 도시한다.
도 5는 본 개시의 또한 추가적인 예시적인 실시형태들에 따른 하드 마스크의 개구 내에 형성되고 버퍼 층의 표면 상의 제 1 피쳐를 포함하는 구조를 도시한다.
도 6은 본 개시의 추가의 예시적인 실시형태들에 따라 제 1 피쳐를 형성하는데 사용된 하드 마스가 제거된 버퍼 층의 표면상에 제 1 피쳐를 갖는 구조를 도시한다.
도 7은 본 개시의 다른 예시적인 실시형태들에 따른 제 1 피쳐 위에 놓여 있고 그 위로 돌출되는 하드 마스크를 포함하는 구조를 예시한다.
도 8은 본 개시의 또한 추가적인 예시적인 실시형태들에 따른 하드 마스크의 개구 내에 형성되고 버퍼 층의 표면 상의 제 2 피쳐를 포함하는 구조를 도시한다.
도 9는 본 발명의 다양한 실시형태들에 따른 버퍼 층 위에 놓인 제 1 피쳐 및 제 2 피쳐를 포함하는 구조를 도시한다.
도 10 은 본 발명의 다양한 실시형태들에 따른 제 1 피쳐, 제 2 피쳐 및 버퍼 층의 부분들을 에칭하는 것에 의해 형성된 핀들을 포함하는 구조를 도시한다.
도 11 은 본 발명의 다양한 실시형태들에 따른 버퍼 층의 부분들 상에 성막된 절연 재료들 및 인접하는 핀들을 포함하는 구조를 도시한다.
도 12는 본 개시의 다양한 실시형태들에 따른 핀들을 포함하는 구조를 도시한다.
도 13은 본 개시의 다양한 실시형태들에 따른 핀들을 포함하는 구조를 갖는 CMOS 디바이스를 도시한다.
도면들에 있는 엘리먼트들은 간결성 및 명료성을 위해 예시되었고 반드시 스케일 (scale) 대로 그려진 것은 아니라는 것이 인식될 것이다. 예를 들면, 도면들에 있는 엘리먼트들의 일부의 치수들은 본 개시의 예시된 실시형태들의 이해를 향상시키는 것을 돕기 위해 다른 엘리먼트들에 비해 과장될 수도 있다.
도 1은 본 개시의 예시적인 실시형태들에 따른 기판을 도시한다.
도 2는 본 개시의 다른 예시적인 실시형태들에 따른 기판 위에 놓여 있는 버퍼 층을 포함하는 구조를 예시한다.
도 3은 본 개시의 예시적인 실시형태들에 따른 버퍼 층내에 형성된 p 웰 영역 및 n 웰 영역을 포함하는 구조를 도시한다.
도 4는 본 개시의 예시적인 실시형태들에 따른 버퍼 층 위에 놓인 패터닝된 하드 마스크를 포함하는 구조를 도시한다.
도 5는 본 개시의 또한 추가적인 예시적인 실시형태들에 따른 하드 마스크의 개구 내에 형성되고 버퍼 층의 표면 상의 제 1 피쳐를 포함하는 구조를 도시한다.
도 6은 본 개시의 추가의 예시적인 실시형태들에 따라 제 1 피쳐를 형성하는데 사용된 하드 마스가 제거된 버퍼 층의 표면상에 제 1 피쳐를 갖는 구조를 도시한다.
도 7은 본 개시의 다른 예시적인 실시형태들에 따른 제 1 피쳐 위에 놓여 있고 그 위로 돌출되는 하드 마스크를 포함하는 구조를 예시한다.
도 8은 본 개시의 또한 추가적인 예시적인 실시형태들에 따른 하드 마스크의 개구 내에 형성되고 버퍼 층의 표면 상의 제 2 피쳐를 포함하는 구조를 도시한다.
도 9는 본 발명의 다양한 실시형태들에 따른 버퍼 층 위에 놓인 제 1 피쳐 및 제 2 피쳐를 포함하는 구조를 도시한다.
도 10 은 본 발명의 다양한 실시형태들에 따른 제 1 피쳐, 제 2 피쳐 및 버퍼 층의 부분들을 에칭하는 것에 의해 형성된 핀들을 포함하는 구조를 도시한다.
도 11 은 본 발명의 다양한 실시형태들에 따른 버퍼 층의 부분들 상에 성막된 절연 재료들 및 인접하는 핀들을 포함하는 구조를 도시한다.
도 12는 본 개시의 다양한 실시형태들에 따른 핀들을 포함하는 구조를 도시한다.
도 13은 본 개시의 다양한 실시형태들에 따른 핀들을 포함하는 구조를 갖는 CMOS 디바이스를 도시한다.
도면들에 있는 엘리먼트들은 간결성 및 명료성을 위해 예시되었고 반드시 스케일 (scale) 대로 그려진 것은 아니라는 것이 인식될 것이다. 예를 들면, 도면들에 있는 엘리먼트들의 일부의 치수들은 본 개시의 예시된 실시형태들의 이해를 향상시키는 것을 돕기 위해 다른 엘리먼트들에 비해 과장될 수도 있다.
아래에 제공된 방법들, 구조들 및 디바이스들의 예시적인 실시형태들의 설명은 단지 예시적이고 예시의 목적으로만 의도되고; 다음의 설명은 본 개시 또는 청구항의 범위를 제한하도록 의도되지 않는다. 또한, 언급된 피쳐 (feature) 들을 갖는 다수의 실시형태들의 기재는 추가 피쳐들을 갖는 다른 실시형태들 또는 언급된 피쳐들의 상이한 조합들을 포함하는 다른 실시형태들을 배제하도록 의도되지 않는다.
본 개시는 일반적으로 반도체 디바이스 및 구조에 관한 것이고 그 디바이스 및 구조의 형성 방법에 관한 것이다. 아래에 더 자세히 제시된 바처럼, 그 구조물은, 채널 영역에서 게르마늄을 갖는, FinFET 디바이스들과 같은, 다수의 게이트들을 포함하는 디바이스들을 형성하는데 사용될 수도 있다.
도 12는, 본 개시의 예시적인 실시형태들에 따른 구조물 (1200) 을 도시하고, 도 1 내지 도 11은 구조물 (1200) 의 제조 동안 형성된 구조물을 예시한다. 구조물 (1200) 은, 아래에 더 자세히 논의되는 바처럼 CMOS 디바이스를 형성하는데 적합하다. 구조물 (1200) 은, NMOS 핀들 (1204) 을 포함하는 NMOS 영역 (1202), 및 PMOS 핀들 (1208) 을 포함하는 PMOS 영역 (1206) 을 포함한다. 구조물 (1200) 은, 다른 CMOS 구조물들에 비해 유리한데, 왜냐햐면 구조물 (1200) 은, NMOS 영역들 (1202) 및 PMOS 영역들 (1206) 양자 모두를 포함하며 각각은 다중 게이트 디바이스를 위한 핀들을 포함하고, 여기서 구조물 (1200) 은 또한 게르마늄을 포함하는 고이동도 채널을 포함하기 때문이다.
이제 도 1을 참조하면, 구조물 (1200) 과 같은 구조물의 형성 방법은 기판 (100) 을 제공하는 단계를 포함한다. 여기서 사용된 "기판" 은, 재료가 성막될 수 있는 표면을 갖는 임의의 재료를 지칭한다. 기판은 벌크 재료 이를테면 실리콘 (예를 들어, 단결정 실리콘) 을 포함할 수도 있거나 또는 벌크 재료 위에 놓이는 하나 이상의 층들을 포함할 수도 있다. 또한, 기판은 기판의 층의 적어도 일 부분 상에 또는 내부에 형성된 트렌치, 비아, 라인 등과 같은 다양한 토폴로지를 포함할 수도 있다. 예로써, 기판 (100) 은 약 1e19/cm3 보론 원자들로 도핑된 실리콘 웨이퍼를 포함한다.
도 2는, 기판 (100) 및 기판 (100) 위에 놓인 스트레인 이완 (strain relaxed) Si1-xGex (식중 x는 0 내지 약 0.8 또는 0 내지 약 0.5이다) 층 (202) 을 포함하는 구조물 (200) 을 도시한다. 도시된 예에서, 층 (202) 은 기판 (100) 에 인접한다; 하지만, 본 개시에 따른 다른 구조들은 기판 (100) 과 층 (202) 사이에 개재된 하나 이상의 층들을 포함할 수도 있다. 층 (202) 의 두께는 약 100 nm 내지 약 5 ㎛, 약 300 nm 내지 약 2 ㎛, 또는 약 2㎛ 의 범위일 수도 있다. 버퍼 층 (202) 은, 약 5e15/cm3 보론 원자들과 같은 적합한 도펀트로 도핑될 수도 있다.
층 (202) 은 기판 (100) 위에 놓인 스트레인 이완 Si1-xGex 를 에피텍셜로 성장시키는 것에 의해 형성될 수도 있다. 예로써, 층 (202) 은, 약 10 Torr 의 압력에서 약 700℃ 이상의 온도로 전구체 또는 반응물들로서 디클로로실란 (SiH2Cl2), 게르만 (GeH4), 및 수소 (H2) 를 사용하여 형성될 수도 있다. 층 (202) 을 형성하는 다른 예시적인 방법은, 약 10 Torr 의 압력에서 약 600℃ 이상의 온도로 반응물로서 실란 (SiH4), 게르만 및 수소를 사용하는 단계를 포함한다. 층 (202) 을 형성함에 있어서의 사용을 위한 적합한 반응기는 명칭 IntrepidTM XP 또는 Epsilon® 하에 ASM 으로부터 입수가능하다.
도 3은, 층 (202) 내에 형성된 p 웰 영역 (302) 및 n 웰 영역 (304) 을 포함하는 구조물 (300) 을 도시한다. p 웰 영역 (302) 및 n 웰 영역 (304) 은, 임의의 적합한 방법을 사용하여, 이를테면 p 웰 영역 (302) 를 형성하기 위하여 패터닝 및 마스킹 기법 및 보론 이온 주입 (예를 들어, 약 5e17/cm3 보론) 을 사용하여 그리고 유사하게 n 웰 영역 형성을 위하여 패터닝 및 마스킹 기법 및 비소 또는 인 이온 주입 (예를 들어, 약 5e17/cm3 비소 또는 인) 을 사용하여 형성될 수도 있다. p 웰 및 n 웰 형성 프로세스 양자 모두는, 그러한 영역들을 형성하는데 통상 사용되는 바처럼 어닐 프로세스를 포함할 수도 있다.
이제 도 4를 참조하면, p 웰 영역 (302) 및 n 웰 영역 (304) 이 형성된 후에, 구조물 (400) 은, 하드 마스크 재료, 이를테면 실리콘 산화물 (SiOx), 예를 들어, 실리콘 이산화물 (SiO2) 을 성막, 패터닝 및 에칭하여 하드 마스크 층 (402) 을 형성하는 것에 의해 형성된다. 하드 마스크 재료는, 예를 들면, 플라즈마 강화 원자 층 증착을 사용하여 - 예를 들어 약 400℃ 또는 300℃ 이하에서 성막된 SAM.24 (H2Si[N(C2H5)2]2) 및 산소 (O2) 플라즈마를 사용하여, 성막될 수도 있다. 그러한 프로세스는, 예를 들어, 명칭 Eagle® XP하에 판매되는 ASM 반응기를 사용하여 수행될 수도 있다. 다르게는, 층 (402) 을 형성하는데 사용된 하드 마스크 재료는 실란 또는 테트라에틸 오르토실리케이트 (TEOS) 를 사용한 화학 기상 증착에 의해 성막될 수도 있다. 층 (402) 의 두께는 약 10 nm 내지 약 100 nm 의 범위일 수도 있다.
다음으로, 도 5에 도시된 바처럼, 구조물 (500) 은, 버퍼 층 (202) 위에 놓인 에피택셜 실리콘과 같은 에피택셜 재료를 선택적으로 성막하여 층 (502) 을 형성하는 것에 의해 형성된다. 층 (502) 은, 약 700℃ 내지 1000℃ 의 반응 온도 및 약 10 Torr의 반응기 압력에서 반응물로서 디클로로실란, 염화수소 (HCl), 및 수소를 이용하여 층 (202) 위에 (예를 들어, 영역 (302) 위에) 선택적으로 성막될 수도 있다. 층 (502) 을 성장시키기 위한 다른 예시적인 프로세스는 약 400 ∼ 600℃ 에서 트리실란 (Si3H8) 기반 순환 성막-에치 프로세스 (cyclic deposit-etch process) 를 사용하는 것을 포함한다. 각각의 프로세스는, 예를 들어, 명칭 IntrepidTM XP 또는 Epsilon® 하에 ASM 으로부터 입수가능한 반응기를 사용하여 수행될 수 있다. 게르마늄 전구체는 또한, 층 (502) 이 게르마늄을 포함할 때 이 단계 동안 사용될 수도 있다. 층 (502) 의 두께는 약 10 nm 에서 약 50 nm 까지 달라질 수 있다. 예를 들면, 층 (502) 의 두께는 약 30 nm일 수 있다.
다음으로, 도 6에 도시된 바처럼, 하드 마스크 층 (402) 이 제거되어 구조물 (600) 을 형성한다. 예로써, 층 (402) 은, 묽은 불화수소산 (HF) 용액을 사용하여 선택적으로 제거될 수 있다. 구조물 (700) 은, 층 (502) 위에 놓여 있는, 실리콘 산화물과 같은 하드 마스크 재료의 층을 성막하고, 하드 마스크 재료를 마스킹 및 패터닝하여 층 (702) 을 형성하는 것에 의해 형성된다. 도시된 예에서, 층 (702) 은 영역 (704) 에서 층 (502) 위로 돌출된다. 돌출부 (706) 는, 이하에서 더 자세히 논의되는 바처럼, 영역 (304) 위에 성막된 에피택셜 재료의 분리를 허용한다. 층 (702) 은, 층 (404) 을 성막하는데 사용된 동일하거나 유사한 기법들을 사용하여 성막될 수도 있다. 예를 들면, 하드 마스크 재료는, 플라즈마 강화 원자 층 증착을 사용하여-예를 들어 약 400℃ 또는 300℃ 이하에서 성막된 SAM.24 (H2Si[N(C2H5)2]2) 및 산소 (O2) 플라즈마를 사용하여, 성막될 수도 있다. 그러한 프로세스는, 예를 들어, 명칭 Eagle® XP하에 판매되는 ASM 반응기를 사용하여 수행될 수도 있다. 다르게는, 층 (402) 을 형성하는데 사용된 하드 마스크 재료는 실란 또는 테트라에틸 오르토실리케이트 (TEOS) 를 사용한 화학 기상 증착에 의해 성막될 수도 있다. 층 (702) 의 두께는 약 2 nm 내지 약 50 nm 의 범위일 수도 있다.
다음으로, Si1-yGey (식중, y는 약 0.1 내지 1의 범위이다) 의 에피택셜 층 (802) 이 영역 (304) 위에 형성되어, 도 8에 도시된 구조물 (800) 을 형성한다. 예로써, 층 (802) 은, 약 350℃ 내지 약 550℃ 의 온도 및 약 10 Torr 의 압력으로 질소 (N2) 캐리어 가스에서 게르만을 사용한 에피택셜 프로세스, 예를 들면, ASM IntrepidTM XP 또는 Epsilon® 반응기를 사용하여, 형성될 수도 있다. 층 (802) 의 두께는 일반적으로 층 (502) 의 두께와 대략 동일하고 약 10 nm 내지 약 50 nm 의 범위일 수 있고; 예를 들어, 이 두께는 약 30 nm 일 수도 있다. 층 (802) 의 성막 전에, 그렇지 않다면 표면에 존재할 수도 있는 산소를 감소시키기 위하여, 구조물 (700) 은 인시츄 불화수소산 세정 프로세스 (in-situ hydrofluoric acid clean process) 에 노출될 수 있다.
도 9에 도시된 구조물 (900) 은, 하드 마스크 층 (702) 을 선택적으로 제거하는 것에 의해 형성될 수도 있다. 예로써, 층 (702) 이 실리콘 산화물을 포함할 때, 층 (702) 은 묽은 불화수소산 에치 프로세스를 사용하여 제거될 수 있다. 위에 언급된 바처럼, 층 (702) 이 돌출 영역을 포함할 때, 층 (502) 과 층 (802) 사이에 공간 (902) 이 형성될 수 있다. 이것은, 구조물 (900) 을 사용하여 형성된 NMOS 와 PMOS 디바이스들 사이에 적합한 격리를 허용한다.
이제 도 10을 참조하면, p 웰 영역 및 층 (502) 로부터의 재료를 포함하는 핀들 (1002), 및 n 웰 영역 (304) 및 층 (802) 로부터의 재료를 포함하는 PMOS 핀들 (1004) 을 포함하는 구조물 (1000) 이 형성된다. 핀들 (1002 및 1004) 는, 예를 들어, 브롬화 수소 (HBr)/염소 (Cl2)/산소/디플루오르메탄 (CH2F2) 에치 프로세스를 사용하여 형성될 수도 있다.
핀들 (1002 및 1004) 이 형성된 후에, 도 11에 예시된 구조물 (1100) 은, 예를 들어, 구조물 (1000) 위에 놓인 절연 재료를 성막하여 층 (1102) 을 형성하는 것에 의한 얕은 트렌치 격리 (shallow trench isolation; STI) 기법들을 사용하여 형성된다. 예로써, 구조물 (1100) 은, 구조물 (1000) 상에 저온 (예를 들어, 약 400℃ 또는 약 300℃ 이하) 원자 층 증착 프로세스를 사용하여 실리콘 산화물을 성막하는 것에 의해 형성될 수도 있다. 이 프로세스를 위한 예시적인 반응물들은 SAM.24 및 산소 플라즈마를 포함한다. 층 (1102) 를 형성하기 위한 프로세스는 ASM Eagle® XP 반응기에서 수행될 수도 있다.
구조물 (1200) 은 층 (1102) 의 일부를 제거하여 층 (1210) 및 핀들 (1204 및 1208) 을 형성하는 것에 의해 형성된다. 층 (1102) 의 일부를 제거하기 위한 예시적인 프로세스는 반응성 이온 에치 프로세스를 포함할 수도 있고, 여기서 실리콘을 포함하는 층 및 p 웰 영역을 사용하여 형성된 하나 이상의 핀 구조들 및 Si1-yGey 을 포함하는 층 및 n 웰 영역을 사용하여 형성된 하나 이상의 핀 구조들 내의 버퍼 층의 두께는 약 20 nm 내지 약 200 nm 이다.
도 13은 구조물, 이를테면 구조물 (1200) 을 포함하는 CMOS 디바이스 (1300) 를 도시한다. 디바이스 (1300) 은, NMOS 영역 (1302) 및 PMOS 영역 (1304) 을 포함한다. 예시된 바처럼, NMOS 영역은 핀 (1306) 을 포함하고 PMOS 영역은 핀 (1308) 을 포함하고, 이들은 도 1 내지 도 12와 관련하여 전술된 재료 및 프로세스들을 사용하여 형성될 수도 있다. 구조물 (1300) 은 또한, 유전체 층 (1310), 및 PMOS 핀들 및 NMOS 핀들 위에 각각 형성된 게이트 금속 층 (1312, 1314) 을 포함한다. 층들 (1312 및 1314) 은 동일하거나 상이한 게이트 금속일 수도 있다. 유사하게는, 단일 게이트 유전체 층으로서 예시되었지만, 층 (1310) 은, PMOS 디바이스에 대해서는 제 1 재료 그리고 NMOS 디바이스에 대해서는 제 2 재료로 형성될 수도 있다. 층 (1310) 을 위한 예시적인 유전체 재료는 HfO2 를 포함한다. 예시적인 게이트 금속들은 TiN 을 포함하고, 이는 TiCl4 및 NH3 를 사용하여 성막될 수도 있다. 다음으로, 콘택트 금속 층 (1316) 이 NMOS 및 PMOS 디바이스들에 대해 게이트 금속 위에 놓이게 형성될 수도 있다. 예시적인 콘택트 금속들은, 예를 들어, WF6 및 Si2H6 를 사용하여, 성막된 텅스텐을 포함한다. 구조물 (1300) 은 또한, 도 13에 도시된 바처럼, 특히 PMOS 디바이스들에서 캐리어 이동도를 증가시키기 위하여 피쳐 (1318) 와 같은 추가적인 스트레서 피쳐들을 포함할 수도 있다.
여기에 기재된 구성들 및/또는 접근법들은 성질상 예시적이고, 이들 특정 실시형태들 또는 예들은 제한적인 의미로 고려되지 않아야 한다는 것이 이해되야 한다. 여기에 기재된 특정 루틴 또는 방법들은 임의의 수의 프로세싱 전략들 중 하나 이상을 나타낼 수도 있다. 따라서, 예시된 다양한 행위들은 예시된 순서로 수행되거나, 다른 순서로 수행되거나, 동시에 수행되거나, 또는 몇몇 경우들에서 생략될 수도 있다.
본 개시의 요지는 다양한 프로세스들, 구조들 및 디바이스들의 모든 신규하고 비자명한 조합들 및 하위 조합, 그리고 여기에 개시된 다른 특징들, 기능들, 행위들 및/또는 특성들, 그리고 그의 임의의 그리고 모든 균등물들을 포함한다.
Claims (20)
- 반도체 구조물의 형성 방법으로서,
실리콘을 포함하는 기판을 제공하는 단계;
상기 기판 위에 놓이는, Si1-xGex (식중, x는 0 내지 0.8 의 범위이다) 를 포함하는 스트레인 이완 (strain relaxed) 버퍼 층을 형성하는 단계;
제 1 선택적 에피택셜 프로세스를 이용하여, 상기 버퍼 층의 표면 위에 놓이는 실리콘을 포함하는 제 1 피쳐를 형성하는 단계; 및
제 2 선택적 에피택셜 프로세스를 이용하여, 상기 표면에 Si1-yGey (식중, y는 0.1 내지 1 의 범위이다) 를 포함하는 제 2 피쳐를 형성하는 단계를 포함하고,
상기 제 1 피쳐는 상기 버퍼 층에서 p 웰 영역 (well region) 위에 놓이게 형성되고 상기 제 2 피쳐는 상기 버퍼 층에서 n 웰 영역 위에 놓이게 형성되는, 반도체 구조물의 형성 방법. - 제 1 항에 있어서,
상기 x는 0 보다 큰, 반도체 구조물의 형성 방법. - 제 1 항에 있어서,
상기 제 1 피쳐를 형성하는 단계는 하드 마스크를 형성하는 단계, 상기 하드 마스크에서 개구들을 형성하는 단계, 및 상기 개구들의 적어도 하나 내에 상기 제 1 피쳐를 선택적으로 형성하는 단계를 포함하는, 반도체 구조물의 형성 방법. - 제 3 항에 있어서,
상기 하드 마스크를 제거하는 단계를 더 포함하는, 반도체 구조물의 형성 방법. - 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,
상기 제 2 피쳐를 형성하는 단계는 하드 마스크를 형성하는 단계, 상기 하드 마스크에서 개구들을 형성하는 단계, 및 상기 개구들의 적어도 하나 내에 상기 제 2 피쳐를 선택적으로 형성하는 단계를 포함하는, 반도체 구조물의 형성 방법. - 제 5 항에 있어서,
상기 하드 마스크를 제거하는 단계를 더 포함하는, 반도체 구조물의 형성 방법. - 제 5 항에 있어서,
상기 하드 마스크는 상기 제 1 피쳐 위로 돌출되는, 반도체 구조물의 형성 방법. - 제 7 항에 있어서,
상기 제 1 피쳐와 상기 제 2 피쳐 사이에 공간을 형성하는 단계를 더 포함하고, 상기 공간은 50nm 미만인, 반도체 구조물의 형성 방법. - 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,
상기 제 1 피쳐 및 상기 제 2 피쳐를 에칭하여 실리콘을 포함하는 하나 이상의 핀들 및 Si1-yGey (식중, y는 0.1 내지 1이다) 을 포함하는 하나 이상의 핀들을 형성하는 단계를 더 포함하는, 반도체 구조물의 형성 방법. - 제 9 항에 있어서,
400℃ 미만의 온도에서 절연 재료를 성막하는 단계를 더 포함하는, 반도체 구조물의 형성 방법. - 제 10 항에 있어서,
상기 절연 재료를 성막하는 단계는, H2Si[N(C2H5)2]2 및 O2 플라즈마를 이용하여 산화물 층을 형성하는 단계를 포함하는, 반도체 구조물의 형성 방법. - 제 10 항에 있어서,
상기 절연 재료의 일부를 제거하는 단계를 더 포함하는, 반도체 구조물의 형성 방법. - 반도체 구조물로서,
실리콘을 포함하는 기판;
상기 기판 위에 놓이는, Si1-xGex (식중, x는 0 내지 0.5 의 범위이다) 를 포함하는 스트레인 이완 (strain relaxed) 버퍼 층;
상기 버퍼 층 내에 형성된 p 웰 영역;
상기 버퍼 층 내에 형성된 n 웰 영역;
상기 p 웰 영역 및 실리콘을 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들;
상기 n 웰 영역 및 Si1-yGey (식중, y는 0.1 내지 1의 범위이다) 를 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들; 및
상기 버퍼 층의 일부 위에 놓이게 형성되는 절연 층을 포함하는, 반도체 구조물. - 제 13 항에 있어서,
상기 절연 층은 400℃ 미만의 온도에서 형성되는, 반도체 구조물. - 제 13 항에 있어서,
상기 절연 층은, H2Si[N(C2H5)2]2 및 O2 플라즈마를 이용하여 형성되는, 반도체 구조물. - 제 13 항 내지 제 15 항 중 어느 한 항에 있어서,
상기 p 웰 영역 및 실리콘을 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들 및 상기 n 웰 영역 및 Si1-yGey 를 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들 내의 상기 버퍼 층의 두께는 20 nm 내지 200 nm 인, 반도체 구조물. - CMOS 디바이스로서,
실리콘을 포함하는 기판;
상기 기판 위에 놓이는, Si1-xGex (식중, x는 0 내지 0.5 의 범위이다) 를 포함하는 스트레인 이완 (strain relaxed) 버퍼 층;
상기 버퍼 층 내에 형성된 p 웰 영역;
상기 버퍼 층 내에 형성된 n 웰 영역;
상기 p 웰 영역 및 실리콘을 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들;
상기 n 웰 영역 및 Si1-yGey (식중, y는 0.1 내지 1의 범위이다) 를 포함하는 층을 이용하여 형성된 하나 이상의 핀 구조들; 및
상기 버퍼 층의 일부 위에 놓이게 형성되는 절연 층을 포함하는, CMOS 디바이스. - 제 17 항에 있어서,
상기 절연 층은 실리콘 산화물을 포함하는, CMOS 디바이스. - 제 17 항 또는 제 18 항에 있어서,
상기 절연 층은 400℃ 미만의 온도에서 형성되는, CMOS 디바이스. - 제 17 항 또는 제 18 항에 있어서,
상기 절연 층은, H2Si[N(C2H5)2]2 및 O2 플라즈마를 이용하여 형성되는, CMOS 디바이스.
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