JP2011009412A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 114
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 32
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 56
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052691 Erbium Inorganic materials 0.000 description 2
- -1 NiPt Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
【解決手段】本発明の一態様に係る半導体装置1は、ファセット面13fを有するエピタキシャル結晶層13を有するMISFET10と、MISFET10を他の素子から電気的に分離し、上層3aのゲート電極12側の端部の水平方向の位置が下層3bのそれよりもゲート電極12に近く、上層3aの一部がファセット面13fに接する素子分離絶縁膜3と、エピタキシャル結晶層13の上面、およびファセット面13fの上層3aとの接触部よりも上側の領域に形成されたシリサイド層18と、を有する。
【選択図】図1
Description
(半導体装置の構成)
図1は、本発明の実施の形態に係る半導体装置1の断面図である。半導体装置1は、半導体基板2上の素子分離絶縁膜3により囲まれた素子形成領域に形成されたMISFET(Metal Insulator Semiconductor Field Effect Transistor)10を有する。
図2A(a)〜(d)、図2B(e)〜(h)、図2C(i)〜(l)は、本発明の実施の形態に係る半導体装置1の製造工程を示す断面図である。
Z−Y≦X・tanθ・・・(1)
本発明の実施の形態によれば、シリサイド層19はファセット面13fの上層3aとの接触部よりも上側の領域に選択的に形成され、接触部よりも下側の領域には形成されないため、エピタキシャル結晶層13下の半導体基板2とシリサイド層19との距離を大きくし、接合リークの発生を抑えることができる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。例えば、図2B(e)に示した素子分離絶縁膜3を形成する工程の後、半導体基板2の素子形成領域23上にSiGe結晶をエピタキシャル成長させ、このSiGe結晶をチャネル領域の一部として用いてもよい。
Claims (5)
- 半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、前記半導体基板中の前記ゲート電極の両側の領域のうち少なくとも一方に形成され、前記半導体基板の主面と異なる面方位を有するファセット面を有するエピタキシャル結晶層と、を有するトランジスタと、
前記半導体基板中に形成され、前記トランジスタを他の素子から電気的に分離し、下層および前記下層上の上層を含み、前記上層の前記ゲート電極側の端部の水平方向の位置が前記下層のそれよりもゲート電極に近く、前記上層の一部が前記ファセット面に接する素子分離絶縁膜と、
前記エピタキシャル結晶層の上面、および前記ファセット面の前記上層との接触部よりも上側の領域に形成された金属シリサイド層と、
を有する半導体装置。 - 前記金属シリサイド層の最下部が前記エピタキシャル結晶層中に位置する、
請求項1に記載の半導体装置。 - 前記トランジスタはp型トランジスタであり、
前記エピタキシャル結晶層はSiGe結晶からなる、
請求項1または2に記載の半導体装置。 - 前記半導体基板は、主面の面方位が{100}であるSi系結晶であり、
前記トランジスタのチャネル方向は<110>である、
請求項1〜3のいずれか1つに記載の半導体装置。 - 半導体基板中に、前記半導体基板の素子形成領域を囲むように、上部の前記素子形成領域側の端部の水平方向の位置が下部のそれよりも前記素子形成領域に近い素子分離溝を形成する工程と、
前記素子分離溝中に絶縁膜を埋め込み、上層の前記素子形成領域側の端部の水平方向の位置が下層のそれよりも前記素子形成領域に近い素子分離絶縁膜を形成する工程と、
前記半導体基板の前記素子分離絶縁間に囲まれた前記素子形成領域上に、ゲート絶縁膜を介して位置するゲート電極を形成する工程と、
前記素子形成領域内の前記半導体基板中の前記ゲート電極の両側の領域のうち少なくとも一方に溝を形成する工程と、
前記溝内に露出した前記半導体基板の表面を下地として、前記半導体基板の主面と異なる面方位を有するファセット面が前記素子分離絶縁膜の前記上層に接触するように、結晶をエピタキシャル成長させる工程と、
前記結晶の上面、および前記ファセット面の前記上層との接触部よりも上側の領域に、金属シリサイド層を形成する工程と、
を含む半導体装置の製造方法。
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JP2009150755A JP2011009412A (ja) | 2009-06-25 | 2009-06-25 | 半導体装置およびその製造方法 |
US12/816,890 US20100327329A1 (en) | 2009-06-25 | 2010-06-16 | Semiconductor device and method of fabricating the same |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012142440A (ja) * | 2010-12-28 | 2012-07-26 | Fujitsu Semiconductor Ltd | 半導体基板の製造方法及び半導体装置の製造方法 |
JP2013073946A (ja) * | 2011-09-26 | 2013-04-22 | Dainippon Screen Mfg Co Ltd | 熱処理方法 |
JP2017504192A (ja) * | 2013-12-12 | 2017-02-02 | 日本テキサス・インスツルメンツ株式会社 | 埋め込みエピタキシャルファセットにおけるシリサイド及びコンタクトの形成 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101776926B1 (ko) * | 2010-09-07 | 2017-09-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8623713B2 (en) * | 2011-09-15 | 2014-01-07 | International Business Machines Corporation | Trench isolation structure |
US8927374B2 (en) | 2011-10-04 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabrication method thereof |
US9012310B2 (en) * | 2012-06-11 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial formation of source and drain regions |
CN103413758B (zh) * | 2013-07-17 | 2017-02-08 | 华为技术有限公司 | 半导体鳍条的制作方法、FinFET器件的制作方法 |
CN104392956A (zh) * | 2014-11-26 | 2015-03-04 | 上海华力微电子有限公司 | 半导体器件制造方法 |
US20220336614A1 (en) * | 2021-04-15 | 2022-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/Drain Silicide for Multigate Device Performance and Method of Fabricating Thereof |
Family Cites Families (2)
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US7579617B2 (en) * | 2005-06-22 | 2009-08-25 | Fujitsu Microelectronics Limited | Semiconductor device and production method thereof |
JP5329835B2 (ja) * | 2008-04-10 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
-
2009
- 2009-06-25 JP JP2009150755A patent/JP2011009412A/ja not_active Withdrawn
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- 2010-06-16 US US12/816,890 patent/US20100327329A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012142440A (ja) * | 2010-12-28 | 2012-07-26 | Fujitsu Semiconductor Ltd | 半導体基板の製造方法及び半導体装置の製造方法 |
JP2013073946A (ja) * | 2011-09-26 | 2013-04-22 | Dainippon Screen Mfg Co Ltd | 熱処理方法 |
JP2017504192A (ja) * | 2013-12-12 | 2017-02-02 | 日本テキサス・インスツルメンツ株式会社 | 埋め込みエピタキシャルファセットにおけるシリサイド及びコンタクトの形成 |
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