JP2017504192A - 埋め込みエピタキシャルファセットにおけるシリサイド及びコンタクトの形成 - Google Patents
埋め込みエピタキシャルファセットにおけるシリサイド及びコンタクトの形成 Download PDFInfo
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 38
- 230000015572 biosynthetic process Effects 0.000 title description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 43
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 43
- 239000000945 filler Substances 0.000 claims abstract description 26
- 125000006850 spacer group Chemical group 0.000 claims description 114
- 239000000463 material Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000003989 dielectric material Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 20
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 14
- 239000000203 mixture Substances 0.000 description 12
- 238000000407 epitaxy Methods 0.000 description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- -1 diborane Chemical compound 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical class Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
Description
Claims (19)
- 集積回路であって、
基板であって、前記基板の頂部表面まで延在する半導体材料を含む前記基板、
前記基板に配置されるフィールド酸化物、
第1の極性の第1の金属酸化物半導体(MOS)トランジスタであって、
前記半導体材料の前記頂部表面におけるゲート誘電体層と、
前記第1のMOSトランジスタの前記ゲート誘電体層の上のゲートと、
前記第1のMOSトランジスタの前記ゲートと前記フィールド酸化物との間の前記基板における第1のエピタキシャルソース−ドレイン領域であって、前記フィールド酸化物に隣接し、前記第1のエピタキシャルソース−ドレイン領域が前記フィールド酸化物の頂部表面において前記フィールド酸化物から或るギャップにより横方向に分離されるように前記フィールド酸化物に面する或る角度のファセットを有し、前記ギャップが前記フィールド酸化物の前記頂部表面から少なくとも20ナノメートル下方に延在する、前記第1のエピタキシャルソース−ドレイン領域と、
前記第1のエピタキシャルソース−ドレイン領域とは反対側で、前記第1のMOSトランジスタの前記ゲートに近接する前記基板における第2のエピタキシャルソース−ドレイン領域と、
前記第1のMOSトランジスタの前記ゲートに横方向に近接するソース−ドレインスペーサと、
を含む、前記第1のMOSトランジスタ、
前記フィールド酸化物の上のゲート構造であって、
前記フィールド酸化物の上のゲートであって、前記ゲート構造のゲートが前記フィールド酸化物の端部に重ならないような、前記ゲートと、
前記ゲート構造の前記ゲートに横方向に近接するソース−ドレインスペーサと、
を含む、前記ゲート構造、
前記ギャップにおける二酸化シリコンベースの誘電性材料のギャップ充填材であって、前記フィールド酸化物に隣接し、前記第1のエピタキシャルソース−ドレイン領域へ下方に延在し、前記ギャップの底部で前記第1のエピタキシャルソース−ドレイン領域に接する、前記ギャップ充填材、
前記第1のエピタキシャルソース−ドレイン領域の前記或る角度のファセット上の金属シリサイド、及び
前記第1のエピタキシャルソース−ドレイン領域の前記或る角度のファセット上の前記金属シリサイド上のコンタクト、
を含む、集積回路。 - 請求項1に記載の集積回路であって、前記フィールド酸化物の頂部表面が、前記ゲート誘電体層の下の前記基板の前記頂部表面の、20ナノメートル内の共面である、集積回路。
- 請求項1に記載の集積回路であって、前記ゲート構造の前記ソース−ドレインスペーサが、主として非シリコン二酸化物の誘電性材料であり、前記金属シリサイドが、前記第1のエピタキシャルソース−ドレイン領域の少なくとも半分を覆う、集積回路。
- 請求項3に記載の集積回路であって、前記第1のMOSトランジスタの前記ソース−ドレインスペーサ及び前記ゲート構造の前記ソース−ドレインスペーサの下に二酸化シリコンベースの誘電性材料のスペーサライナーを更に含む、集積回路。
- 請求項1に記載の集積回路であって、前記ゲート構造の前記ソース−ドレインスペーサが、主として二酸化シリコンベースの誘電性材料であり、前記ギャップ充填材が、前記ゲート構造の前記ソース−ドレインスペーサの一部であり、前記金属シリサイドが、前記第1のエピタキシャルソース−ドレイン領域の少なくとも3分の1を覆う、集積回路。
- 請求項1に記載の集積回路であって、前記金属シリサイドが、主としてニッケルシリサイドである、集積回路。
- 請求項1に記載の集積回路であって、第2の反対の極性の第2のMOSトランジスタを更に含む、集積回路。
- 請求項1に記載の集積回路であって、
前記第1のMOSトランジスタが、pチャネル金属酸化物半導体(PMOS)トランジスタであり、
前記第1のエピタキシャルソース−ドレイン領域及び前記第2のエピタキシャルソース−ドレイン領域が、シリコンゲルマニウムを含む、
集積回路。 - 請求項1に記載の集積回路であって、
前記第1のMOSトランジスタが、nチャネル金属酸化物半導体(NMOS)トランジスタであり、
前記第1のエピタキシャルソース−ドレイン領域及び前記第2のエピタキシャルソース−ドレイン領域が、リンドープされたシリコンを含む、
集積回路。 - 集積回路を形成する方法であって、
基板の頂部表面まで延在する半導体材料を含む前記基板を提供すること、
前記基板にフィールド酸化物を形成すること、
第1のMOSトランジスタのゲートと前記フィールド酸化物との間で前記基板に前記第1のMOSトランジスタの第1のエピタキシャルソース−ドレイン領域を形成することであって、前記第1のエピタキシャルソース−ドレイン領域が、前記フィールド酸化物に面する或る角度のファセットを有し、且つ、前記フィールド酸化物に隣接するように、及び前記第1のエピタキシャルソース−ドレイン領域が、前記フィールド酸化物の頂部表面において或るギャップにより前記フィールド酸化物から横方向に分離されるようにし、前記ギャップが前記フィールド酸化物の前記頂部表面から少なくとも20ナノメートル下方に延在する、前記第1のエピタキシャルソース−ドレイン領域を形成すること、及び同時に、前記第1のMOSトランジスタの前記ゲートに近接し、且つ、前記第1のエピタキシャルソース−ドレイン領域とは反対側の、前記基板において前記第1のMOSトランジスタの第2のエピタキシャルソース−ドレイン領域を形成することであって、前記第1のMOSトランジスタが第1の極性であること、
前記第1のMOSトランジスタの上に二酸化シリコンベースの誘電性材料の層及び前記第1のエピタキシャルソース−ドレイン領域に近接して前記フィールド酸化物の上に位置するゲート構造を形成することであって、前記ゲート構造のゲートが前記フィールド酸化物の端部に重ならず、二酸化シリコンベースの誘電性材料の前記層が前記ギャップ内へ延在すること、
前記フィールド酸化物に隣接し、前記第1のエピタキシャルソース−ドレイン領域へ下方に延在し、前記ギャップの底部で前記第1のエピタキシャルソース−ドレイン領域に接するギャップ充填材を形成するように、前記ギャップにおける二酸化シリコンベースの誘電体の前記層の一部を残して、前記第1のエピタキシャルソース−ドレイン領域の上から二酸化シリコンベースの誘電性材料の前記層の一部を取り除くこと、
前記第1のエピタキシャルソース−ドレイン領域の前記或る角度のファセット上の金属シリサイドを形成すること、及び
前記第1のエピタキシャルソース−ドレイン領域の前記或る角度のファセット上の前記金属シリサイド上のコンタクトを形成すること、
を含む、方法。 - 請求項10に記載の方法であって、前記フィールド酸化物の頂部表面が、前記第1のMOSトランジスタのゲート誘電体層の下の前記基板の前記頂部表面の20ナノメートル内の共面である、方法。
- 請求項10に記載の方法であって、
前記第1のMOSトランジスタ、前記ゲート構造、及び前記ギャップ充填材の上に、スペーサ材料のコンフォーマル層を形成することであって、スペーサ材料の前記コンフォーマル層が主として非シリコン二酸化物材料であること、及び
前記第1のMOSトランジスタの前記ゲートに横方向に近接するソース−ドレインスペーサと、前記ゲート構造の前記ゲートに横方向に近接するソース−ドレインスペーサとを形成するために、前記金属シリサイドが前記第1のエピタキシャルソース−ドレイン領域の少なくとも半分を覆うように、前記ギャップ充填材及び前記第1のエピタキシャルソース−ドレイン領域及び前記第2のエピタキシャルソース−ドレイン領域の上から及び前記第1のMOSトランジスタ及び前記ゲート構造の前記ゲートの頂部の上から、スペーサ材料の前記コンフォーマル層を取り除くこと、
を更に含む、方法。 - 請求項12に記載の方法であって、スペーサ材料の前記コンフォーマル層が、主としてシリコン窒化物である、方法。
- 請求項1に記載の方法であって、
スペーサ材料の前記コンフォーマル層を形成する前に、前記第1のMOSトランジスタ、前記ゲート構造、及び前記ギャップ充填材の上に二酸化シリコンベースの誘電性材料のスペーサライナーを形成すること、及び
スペーサ材料の前記コンフォーマル層を取り除いた後、前記第1のMOSトランジスタの前記ゲートに横方向に近接する前記ソース−ドレインスペーサと前記ゲート構造の前記ゲートに横方向に近接する前記ソース−ドレインスペーサとにより露出された前記スペーサライナーを取り除くこと、
を更に含む、方法。 - 請求項10に記載の方法であって、
二酸化シリコンベースの誘電性材料の前記層がスペーサ層であり、
二酸化シリコンベースの誘電性材料の前記層の前記一部を取り除くことが、前記ギャップ充填材が、前記ゲート構造の前記ゲートに横方向に近接する前記ソース−ドレインスペーサの一部であるように、及び前記金属シリサイドが前記第1のエピタキシャルソース−ドレイン領域の少なくとも3分の1を覆うように、前記第1のMOSトランジスタの前記ゲートに横方向に近接するソース−ドレインスペーサと前記ゲート構造の前記ゲートに横方向に近接するソース−ドレインスペーサとを残す異方性エッチングプロセスによって実施される、
方法。 - 請求項15に記載の方法であって、
前記第1のMOSトランジスタ、前記ゲート構造、前記ギャップ充填材、前記第1のMOSトランジスタの前記ゲートに横方向に近接する前記ソース−ドレインスペーサ、及び前記ゲート構造の前記ゲートに横方向に近接する前記ソース−ドレインスペーサの上に、非シリコン二酸化物ベースの犠牲層を形成すること、
前記金属シリサイドを形成する前に、前記第1のMOSトランジスタの前記ソース−ドレインスペーサ上の犠牲スペーサと前記ゲート構造の前記ソース−ドレインスペーサ上の犠牲スペーサとを形成するために、前記第1のエピタキシャルソース−ドレイン領域の一部及び前記第2のエピタキシャルソース−ドレイン領域の一部の上から、及び前記第1のMOSトランジスタ及び前記ゲート構造の前記ゲートの頂部の上から、異方性エッチングプロセスにより前記非シリコン二酸化物ベースの犠牲層を取り除くこと、及び
前記金属シリサイドを形成した後、前記第1のMOSトランジスタの前記ソース−ドレインスペーサ上の前記犠牲スペーサと前記ゲート構造の前記ソース−ドレインスペーサ上の犠牲スペーサとを取り除くこと、
を更に含む、方法。 - 請求項10に記載の方法であって、前記集積回路が、第2の反対の極性の第2のMOSトランジスタを含む、方法。
- 請求項10に記載の方法であって、
前記第1のMOSトランジスタがPMOSトランジスタであり、
前記第1のエピタキシャルソース−ドレイン領域及び前記第2のエピタキシャルソース−ドレイン領域が、シリコンゲルマニウムを含む、
方法。 - 請求項10に記載の方法であって、
前記第1のMOSトランジスタがNMOSトランジスタであり、
前記第1のエピタキシャルソース−ドレイン領域及び前記第2のエピタキシャルソース−ドレイン領域が、リンドープされたシリコンを含む、
方法。
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US9508601B2 (en) * | 2013-12-12 | 2016-11-29 | Texas Instruments Incorporated | Method to form silicide and contact at embedded epitaxial facet |
US20160064286A1 (en) * | 2014-09-03 | 2016-03-03 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits |
US9947753B2 (en) | 2015-05-15 | 2018-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
US10297602B2 (en) * | 2017-05-18 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implantations for forming source/drain regions of different transistors |
US20220336614A1 (en) * | 2021-04-15 | 2022-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/Drain Silicide for Multigate Device Performance and Method of Fabricating Thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5571733A (en) * | 1995-05-12 | 1996-11-05 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
US6358801B1 (en) * | 1998-02-27 | 2002-03-19 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
JP2008071890A (ja) * | 2006-09-13 | 2008-03-27 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2011009412A (ja) * | 2009-06-25 | 2011-01-13 | Toshiba Corp | 半導体装置およびその製造方法 |
US20120091539A1 (en) * | 2010-10-15 | 2012-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Facet-free semiconductor device |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4998150A (en) * | 1988-12-22 | 1991-03-05 | Texas Instruments Incorporated | Raised source/drain transistor |
JP2661561B2 (ja) * | 1994-10-27 | 1997-10-08 | 日本電気株式会社 | 薄膜トランジスタおよびその製造方法 |
KR100233832B1 (ko) * | 1996-12-14 | 1999-12-01 | 정선종 | 반도체 소자의 트랜지스터 및 그 제조방법 |
US5960291A (en) * | 1997-08-08 | 1999-09-28 | Advanced Micro Devices, Inc. | Asymmetric channel transistor and method for making same |
US6169011B1 (en) * | 1998-03-24 | 2001-01-02 | Sharp Laboratories Of America, Inc. | Trench isolation structure and method for same |
US6150212A (en) * | 1999-07-22 | 2000-11-21 | International Business Machines Corporation | Shallow trench isolation method utilizing combination of spacer and fill |
US6140232A (en) * | 1999-08-31 | 2000-10-31 | United Microelectronics Corp. | Method for reducing silicide resistance |
US6268255B1 (en) * | 2000-01-06 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device with metal silicide regions |
US6448129B1 (en) * | 2000-01-24 | 2002-09-10 | Micron Technology, Inc. | Applying epitaxial silicon in disposable spacer flow |
US6376885B1 (en) * | 2000-09-25 | 2002-04-23 | Vanguard International Semiconductor Corp. | Semiconductor structure with metal silicide and method for fabricated the structure |
US7238566B2 (en) * | 2003-10-08 | 2007-07-03 | Taiwan Semiconductor Manufacturing Company | Method of forming one-transistor memory cell and structure formed thereby |
US7265425B2 (en) * | 2004-11-15 | 2007-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device employing an extension spacer and a method of forming the same |
JP4945910B2 (ja) * | 2005-03-09 | 2012-06-06 | ソニー株式会社 | 半導体装置およびその製造方法 |
US7786518B2 (en) * | 2007-12-27 | 2010-08-31 | Texas Instruments Incorporated | Growth of unfaceted SiGe in MOS transistor fabrication |
DE102008011814B4 (de) * | 2008-02-29 | 2012-04-26 | Advanced Micro Devices, Inc. | CMOS-Bauelement mit vergrabener isolierender Schicht und verformten Kanalgebieten sowie Verfahren zum Herstellen derselben |
JP5329835B2 (ja) * | 2008-04-10 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
JP5588121B2 (ja) * | 2009-04-27 | 2014-09-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8502316B2 (en) * | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
JP2013243307A (ja) * | 2012-05-22 | 2013-12-05 | Toshiba Corp | 半導体製造装置および半導体装置の製造方法 |
KR101952119B1 (ko) * | 2012-05-24 | 2019-02-28 | 삼성전자 주식회사 | 메탈 실리사이드를 포함하는 반도체 장치 및 이의 제조 방법 |
US9508601B2 (en) * | 2013-12-12 | 2016-11-29 | Texas Instruments Incorporated | Method to form silicide and contact at embedded epitaxial facet |
-
2014
- 2014-12-08 US US14/563,062 patent/US9508601B2/en active Active
- 2014-12-12 EP EP14869386.4A patent/EP3080844B1/en active Active
- 2014-12-12 CN CN201480067520.2A patent/CN105814688B/zh active Active
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- 2017-10-03 US US15/723,373 patent/US10008499B2/en active Active
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- 2019-03-25 JP JP2019056248A patent/JP6685442B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5571733A (en) * | 1995-05-12 | 1996-11-05 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
US6358801B1 (en) * | 1998-02-27 | 2002-03-19 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
JP2008071890A (ja) * | 2006-09-13 | 2008-03-27 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2011009412A (ja) * | 2009-06-25 | 2011-01-13 | Toshiba Corp | 半導体装置およびその製造方法 |
US20120091539A1 (en) * | 2010-10-15 | 2012-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Facet-free semiconductor device |
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