TWI631602B - 半導體結構和裝置和使用選擇性磊晶製程以形成其的方法 - Google Patents
半導體結構和裝置和使用選擇性磊晶製程以形成其的方法 Download PDFInfo
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
茲揭示半導體結構和裝置以及形成該等結構和裝置的方法。示範性結構包含可含有n通道MOS(NMOS)及p通道MOS(PMOS)裝置兩者的多閘極或FinFET結構,藉以在一基板上形成CMOS結構和裝置。該等裝置可為利用選擇性磊晶術及淺型溝槽隔離技術所形成。
Description
本揭示概略關於半導體結構及裝置。尤其,本揭示是關於利用選擇性磊晶沉積製程所形成而含有一或更多疊層的半導體結構和裝置。
多閘極半導體裝置,包含且有時概稱為FinFET裝置,近來吸引更多關注,原因是這些裝置相較於類似、單一的閘極/平面裝置可提供每單位電力更高的效能。藉由傳統的金屬氧化物半導體(MOS)裝置,隨著裝置幾何性持續縮小以致力於提昇裝置效能,像是關閉狀態洩漏電流的微短通道效應就會增加。而此洩漏又會導致該裝置的閑置電力要求升高。
FinFET裝置包含可降減洩漏電流的閘極結構。所減少的洩漏電流不僅可降低當該裝置在關閉狀態下時的耗電量,同時亦能降低該裝置的門檻值電壓,如此獲以提高切換速度並減少操作耗電量。
FinFET裝置可能希望是能夠在該裝置的通道範圍裡含有鍺。將鍺納入在通道範圍內可提高電荷載體的遷移率,而如此又可獲以增加裝置效能。然不幸地,欲將鍺納入在通道範圍內對於整合至互補式MOS(CMOS)裝置裡而言已獲證確為困難重重。各種用以形成CMOS FinFET裝置的方式包含利用縱橫比捕捉(aspect ratio trapping)以降低沿該裝置之淺型溝槽
隔離結構上的瑕疵數量。不過,此等製程通常需要將磊晶材料填入狹窄溝槽(即如寬度小於10nm)內,然這確有其難處。此外,在該等裝置內的緩衝凹入控制可能較不理想,從而導致通道高度均勻度不如預期。因此,會需要可供相對易於製造並且擁有相當均勻通道高度之經改善結構、裝置以及形成該等結構、裝置的方法。
本揭示的各種具體實施例是有關於半導體結構和裝置,並且關於構成該等結構和裝置的方法。尤其,本揭示是關於一種多閘極或FinFET結構和裝置以及形成其等的方法。在後文詳細說明中雖為針對於先前技藝方法的缺點以敘述本揭示的各式具體實施例,然廣義而言,本揭示提供可納入n通道MOS(NMOS)及p通道MOS(PMOS)兩者裝置的FinFET結構和裝置以供形成CMOS結構和裝置。
根據本揭示的示範性具體實施例,一種用以形成一半導體結構的方法包含下列步驟:提供一含有矽的基板;形成一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8或自0至約0.5,並且疊覆於該基板上;利用一第一選擇性磊晶製程以形成含有矽的第一特徵(即如Si1-zGez,其中z的範圍為自0至約0.7(像是對於NMOS裝置))且在一表面上疊覆於該緩衝層上;以及利用一第二選擇性磊晶製程以在該表面上形成含有Si1-yGey的第二特徵,其中y的範圍為自約0.1至1(像是對於PMOS裝置)。即如後文所詳述,根據這些具體實施例所形成的結構適用於在一基板上形成CMOSFinFET裝置和結構。根據這些具體實施例的各種特點,在疊覆於緩衝層內的一p井區範圍上形成第一特徵或範圍,並且在疊覆於緩衝層內的一n井
區範圍上形成第二特徵或範圍。根據這些具體實施例的進一步特點,該等第一特徵是藉由以下步驟所形成:沉積一硬遮罩;圖案化該硬遮罩;利用適當的蝕刻劑以蝕刻該硬遮罩,藉以在該硬遮罩內形成開口;以及利用選擇性磊晶技術以形成該特徵。在形成該等第一特徵之後,可利用適當的蝕刻劑以移除該硬遮罩。該等第二特徵可為利用相同或類似的技術所形成。根據這些具體實施例的進一步特點,該硬遮罩是由氧化矽或氮化矽材料所形成。根據又進一步特點,一形成對於該等第二特徵之硬遮罩的步驟包含形成在至少一側上伸出於該等第一特徵的硬遮罩,使得能夠在該等第一特徵與該等第二特徵之間形成一間隔(即如在該構成一裝置的局部之結構裡的第一與第二特徵間形成一可自約2nm至50nm或是約10nm之範圍的空間)。示範性方法亦可包含利用該緩衝層以及該等第一特徵與第二特徵來形成多個翼片或凸出物。在這些情況下,一方法可另外包含下列步驟,即蝕刻該等第一特徵和該等第二特徵,藉以形成一或更多由矽所組成的翼片,以及一或更多含有Si1-yGey,其中y的範圍是自約0.1至1(即如對於PMOS裝置),或者是Si1-zGez,其中z的範圍是自0至約0.7(即如對於NMOS裝置),的翼片;在低於約400℃的溫度處沉積絕緣材料;以及移除該絕緣材料的一局部。根據這些具體實施例的各種特點,該絕緣材料為氧化矽,並且用以沉積該絕緣材料的先質包含H2Si[N(C2H5)2]2和O2電漿。
根據本揭示的其他具體實施例,一半導體結構包含:一含有矽的基板;一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8或自0至約0.5,並且疊覆於該基板上;一形成於該緩衝層之內的p井區範圍;一形成於該緩衝層之內的n井區範圍;一或更多翼片結構,該等是利用該p井
區範圍和一含有矽(即如Si1-zGez,其中z的範圍是自0至約0.7)的疊層所形成;一或更多翼片結構,該等是利用該n井區範圍和一含有Si1-yGey的疊層所形成,其中y的範圍為自約0.1至1;以及一絕緣層,此者為疊覆於該緩衝層之一局部上所形成。本揭所述結構可為利用前述方法所形成。例如,該等絕緣層的一或更多者可為在低於約400℃的溫度處所形成,例如像是利用H2Si[N(C2H5)2]2和O2電漿。
根據本揭示的其他具體實施例,一半導體結構可包含:一含有矽的基板;一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8或自0至約0.5,並且疊覆於該基板上;一第一特徵,此者含有矽(即如Si1-zGez,其中z的範圍是自0至約0.7)並且疊覆於該緩衝層上;一第二特徵,此者含有Si1-yGey,其中y的範圍是自0.1至1,並疊覆於該緩衝層上且位於與該第一特徵相同的表面上。根據這些具體實施例的示範性特點,一即如約2-50或者約10或是小於50nm的長度可分隔該第一特徵及該第二特徵。這些結構可為利用本揭示的方法所形成。
根據本揭示的其他示範性具體實施例,一CMOS裝置包含一含有矽的基板;一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8或自0至約0.5,並且疊覆於該基板上;一形成於該緩衝層之內的p井區範圍;一形成於該緩衝層之內的n井區範圍;一或更多翼片結構,其是利用該p井區範圍和一含有矽(即如Si1-zGez,其中z的範圍是自0至約0.7)的疊層所形成;一或更多翼片結構,其是利用該n井區範圍和一含有Si1-yGey的疊層所形成,其中y的範圍為自約0.1至1;以及一絕緣層,此者為疊覆於該緩衝層之一局部上所形成。
為形成一CMOS裝置的示範性方法包含一種形成如本文所述之半導體結構的方法。為形成CMOS裝置的方法可適當地包含常見用以形成此等裝置的額外沉積、蝕刻與其他製程。
100‧‧‧基板
200‧‧‧結構
202‧‧‧疊層
300‧‧‧結構
302‧‧‧p井區範圍
304‧‧‧n井區範圍
400‧‧‧結構
402‧‧‧硬遮罩層
500‧‧‧結構
502‧‧‧疊層
600‧‧‧結構
700‧‧‧結構
702‧‧‧疊層
704‧‧‧範圍
706‧‧‧伸出
800‧‧‧結構
802‧‧‧磊晶層
900‧‧‧結構
902‧‧‧空間
1000‧‧‧結構
1002‧‧‧NMOS翼片
1004‧‧‧PMOS翼片
1100‧‧‧結構
1102‧‧‧疊層
1200‧‧‧結構
1202‧‧‧NMOS範圍
1204‧‧‧NMOS翼片
1206‧‧‧PMOS範圍
1208‧‧‧PMOS翼片
1210‧‧‧疊層
1300‧‧‧CMOS裝置
1302‧‧‧NMOS範圍
1304‧‧‧PMOS範圍
1306‧‧‧翼片
1308‧‧‧翼片
1310‧‧‧介電層
1312‧‧‧閘極金屬層
1314‧‧‧閘極金屬層
1316‧‧‧接觸金屬層
1318‧‧‧額外特徵
可藉由參照本案詳細說明與申請專利範圍,並關聯於後載隨附圖式,以更完整地瞭解本揭示的示範性具體實施例。
圖1說明一根據本揭示之示範性具體實施例的基板。
圖2說明根據本揭示之進一步示範性具體實施例之一含有疊覆於基板上之緩衝層的結構。
圖3說明根據本揭示之示範性具體實施例之一含有經形成於緩衝層內之p井區範圍和n井區範圍的結構。
圖4說明根據本揭示之示範性具體實施例之一含有疊覆於緩衝層上之圖案化硬遮罩的結構。
圖5說明根據本揭示之其他示範性具體實施例之一含有經形成於硬遮罩的開口內並且位於緩衝層的表面上之第一特徵的結構。
圖6說明根據本揭示之其他示範性具體實施例之一具有位於緩衝層的表面上之第一特徵的結構,而用以形成該第一特徵的硬遮罩則經移除。
圖7說明根據本揭示之進一步示範性具體實施例之一含有疊覆於且伸出於第一特徵之硬遮罩的結構。
圖8說明根據本揭示之其他示範性具體實施例之一含有經形成於硬遮罩的開口內並且位於緩衝層的表面上之第二特徵的結構。
圖9說明根據本發明之各式具體實施例之一含有疊覆於緩衝層上之第
一特徵及第二特徵的結構。
圖10說明根據本發明之各式具體實施例之一含有藉由蝕刻第一特徵、第二特徵與緩衝層的多個局部所形成之翼片的結構。
圖11說明根據本發明之各式具體實施例之一含有經沉積於緩衝層和鄰近翼片的局部上之絕緣材料的結構。
圖12說明一含有根據本發明各式具體實施例之翼片的結構。
圖13說明,根據本發明之各式具體實施例,一具有包含翼片之結構的CMOS裝置。
將能瞭解該等圖式內的構件係為簡要與清晰之目的所敘述,而且並非必然地依比例繪製。例如,該等圖式中部分構件的維度可為相對於其他構件而誇炫,藉以有助於更加瞭解本揭示所敘述的具體實施例。
後文中所提供對於本揭方法、結構及裝置之示範性具體實施例的說明僅屬示範性質且僅為敘述之目的;後文說明並非欲以侷限本揭示或申請專利範圍的範疇。此外,引述多項具備所述特性的具體實施例並非欲以排除其他擁有額外特性的具體實施例或是其他併入該等所述特性之不同組合的具體實施例。
本揭示概略關於半導體裝置和結構以及形成該等裝置和結構的方法。即如後文中進一步詳細說明,該結構可用以形成含有在通道範圍中具有鍺之多個閘極的裝置,像是FinFET裝置。
圖12說明一根據本揭示之示範性具體實施例的結構1200,並且圖1至11說明在該結構1200之製造過程中所形成的結構。該結構1200
適用於形成CMOS裝置,即如後文中進一步詳細討論。該結構1200含有:一NMOS範圍1202,此範圍含有多個NMOS翼片1204;以及一PMOS範圍1206,此範圍則含有多個PMOS翼片1208。該結構1200優於其他的CMOS結構,理由是該結構1200含有NMOS範圍1202及PMOS範圍1206兩者,而各者含有用於一多重閘極裝置的多個翼片,其中該結構1200亦包含包括鍺的高遷移率通道。
現參照圖1,一種形成例如結構1200之結構的方法,其包含提供一基板100的步驟。即如在本揭中所使用者,「基板」是指任何具有一表面而可於其上沉積材料的材料。基板可含有體型材料(bulk material),像是矽(即如單晶矽),或者是包含經疊覆於該體型材料之上的一或更多疊層。除此之外,該基板可含有例如溝槽、通道、線路等等的各式拓墣,而構成於該基板之疊層裡的至少一局部之內或之上。藉由範例,該基板100包含經摻質有約1e19/cm3硼原子的矽晶圓。
圖2說明一結構200,此者含有該基板100以及一經應力鬆弛的Si1-xGex,其中x的範圍為自0至約0.8或0至約0.5,該疊層202疊覆於該基板100上。在所示範例中,該疊層202為鄰接於該基板100;不過,根據本揭示的其他結構,確可包含一或更多疊層安插在該基板100與該疊層202之間。該疊層202的厚度範圍可為自約100nm至約5μm,約300nm至約2μm,或是約為2μm。緩衝層202可經摻質以適當的摻質物,像是約5e15/cm3的硼原子。
疊層202可為藉由磊晶成長該經應力鬆弛的Si1-xGex且疊覆於該基板100之上所形成。藉由範例,該疊層202可為利用二氯矽烷
(SiH2Cl2)、鍺烷(GeH4)及氫氣(H2)作為先質或反應劑,並在約700℃或更高的溫度處且以約10Torr的壓力,所形成。另一種形成該疊層202的示範性方法包含利用矽烷(SiH4)、鍺烷及氫氣作為反應劑,並在約600℃或更高的溫度處且在約10Torr的壓力處進行。用於形成該疊層202的適當反應器可自ASM依產品名稱IntrepidTM XP或Epsilon®獲用。
圖3說明一結構300,此結構含有一經形成於該疊層202之內的p井區範圍302及n井區範圍304。可利用任何適當技術來形成p井區範圍302和n井區範圍304,像是利用圖案化和遮罩技術以及硼離子植入作業(即如約5e17/cm3的硼質)以形成p井區範圍302,並且同樣地利用圖案化和遮罩技術以及砷或磷離子植入作業(即如約5e17/cm3的砷質或磷質)以形成n井區範圍。該等p井區及n井區的形成製程中可包含退火製程,即如為形成此等範圍所常用者。
現參照圖4,在形成p井區範圍302及n井區範圍304之後,可藉由沉積、圖案化和蝕刻一硬遮罩材料,像是即如二氧化矽(SiO2)的氧化矽(SiOx),來形成一硬遮罩層402,以形成結構400。可例如利用電漿強化原子層沉積(即如在約400℃或300℃或是更低的溫度處利用SAM.24(H2Si[N(C2H5)2]2)和氧氣(O2)電漿)以沉積該硬遮罩材料。此項製程可利用例如依Eagle® XP品名而銷售的ASM反應器進行。或另者,為形成該疊層402的硬遮罩材料可利用矽烷或四乙基矽氧烷(TEOS)藉由化學汽相沉積所沉積而得。該疊層402厚度的範圍可為自約10nm至約100nm。
其次,即如圖5所示,一結構500是藉由選擇性地沉積像是磊晶矽的磊晶材料而疊覆於緩衝層202以形成疊層502所形成。該疊層502
可為利用二氯矽烷、氯化氫(HCl)和氫氣作為反應劑,在約700℃至1000℃的反應溫度處以及約10Torr的反應器壓力,選擇性地沉積在該疊層202上(即如在該範圍302上)。用於成長該疊層502的另一種示範性製程則包含在約400-600℃處利用三矽烷(Si3H8)基循環沉積-蝕刻製程。任一製程皆可利用例如可自ASM獲用且產品名稱為IntrepidTM XP或Epsilon®的反應器所執行。當該疊層502含有鍺時,在此項步驟過程中亦可採用鍺先質。該疊層502的厚度可為自約10nm至約50nm而變。例如,該疊層502的厚度可約為30nm。
接著,即如圖6所示,移除硬遮罩層402以形成一結構600。藉由範例,可利用稀釋的氫氟酸(HF)溶液以選擇性地移除該疊層402。可藉由沉積一層像是氧化矽的硬遮罩材料而疊覆於該疊層502上,並且令該硬遮罩材料圖案化俾形成一疊層702,以形成結構700。在所示範例中,該疊層702在範圍704裡伸出於該疊層502。此伸出706可供分隔經沉積在該範圍304上的磊晶材料,即如後文中進一步詳述。可利用與用以沉積疊層404相同或類似的技術來沉積該疊層702。例如,可利用電漿強化原子層沉積(即如在約400℃或300℃或更低的溫度處利用SAM.24(H2Si[N(C2H5)2]2)和氧氣(O2)電漿),以沉積該硬遮罩材料。此項製程可利用例如依Eagle® XP品名而銷售的ASM反應器進行。或另者,為形成該疊層402的硬遮罩材料可利用矽烷或四乙基矽氧烷(TEOS)藉由化學汽相沉積所沉積而得。該疊層702厚度的範圍可為自約2nm至約50nm。
然後在該範圍304上形成一Si1-yGey的磊晶層802,其中y的範圍為約0.1至1,藉以形成一如圖8中所示的結構800。即以範例而言,
該疊層802可為利用在約350℃至約550℃溫度處以及約10Torr的壓力下,並且運用例如一ASM IntrepidTM XP或Epsilon®反應器,於氮氣(N2)載體氣體中利用鍺的磊晶製程所形成。該疊層802的厚度概略為與該疊層502的厚度相同,同時其範圍可為自約10nm至約50nm;例如其厚度可約為30nm。為減少可能會出現在表面處的氧質,在沉積該疊層802之前,可先令一結構700受曝於一現場氫氟酸潔淨製程。
再藉由選擇性地移除該硬遮罩層702以形成如圖9所示的結構900。藉由範例,當該疊層702含有氧化矽時,可利用稀釋氫氟酸蝕刻製程以移除該疊層702。如前所述,當該疊層702含有伸出範圍時,可在該疊層502與該疊層802之間形成一空間902。如此可在利用該結構900所形成之NMOS與PMOS裝置間提供適當的隔離。
現參照圖10,圖中形成有一結構1000,此結構包含多個翼片1002,這些包含來自p井區範圍和疊層502的材料,以及多個PMOS翼片1004,這些包含來自n井區範圍304和疊層802的材料。該等翼片1002及1004可利用例如溴化氫(HBr)/氯(Cl2)/氧/二氟甲烷(CH2F2)的蝕刻製程形成。
在形成該等翼片1002和1004之後,即可利用淺型溝槽隔離(STI)技術藉由沉積絕緣材料而疊覆於該結構1000上以形成一疊層1102,形成如圖11所示的結構1100。即以範例而言,可藉由利用低溫(即如約400℃或約300℃或者更低)原子層沉積製程以將氧化矽沉積在該結構1000上來形成該結構1100。對於此項製程的示範性反應劑包含SAM.24及氧氣電漿。而用以形成該疊層1102的製程可在一ASM Eagle® XP反應器中進行。
該結構1200是藉由移除疊層1102的一局部來形成疊層1210
以及翼片1204和1208而形成。一種用以移除疊層1102之一局部的示範性製程可包含反應性離子蝕刻製程,其中該緩衝層在利用該p井區範圍和一含有矽的疊層所形成之一或更多翼片結構以及利用該n井區範圍和一含有Si1-yGey的疊層所形成之一或更多翼片結構之內的厚度為約20nm至約200nm。
圖13說明一CMOS裝置1300,此者含有一例如結構1200的結構。該裝置1300包含NMOS範圍1302及PMOS範圍1304。即如圖示,該NMOS範圍包含多個翼片1306並且該PMOS範圍包含多個翼片1308,這些可為利用前文中關聯於圖1-12所敘述的材料及製程所形成。該結構1300另外包含一介電層1310以及一分別地形成於該等PMOS翼片及NMOS翼片上的閘極金屬層1312、1314。該等疊層1312及1314可為相同或互異的閘極金屬。同樣地,圖中雖顯示為單一閘極介電層,然該疊層1310可為由對於該PMOS裝置為第一材料並且對於該NMOS裝置為第二材料所形成。對於該疊層1310的示範性介電材料包含HfO2。示範性閘極金屬包含TiN,此者可為利用TiCl4及NH3所沉積。然後可疊覆於該閘極金屬上形成一接觸金屬層1316以用於該等NMOS及PMOS裝置。示範性接觸金屬包含鎢,這可利用例如WF6及Si2H6沉積而得。該結構1300亦可包含額外的應力器特徵,像是特徵1318,藉以提高特別是在PMOS裝置中的載體遷移率,即如圖13中所示者。
應瞭解本揭所述之組態及/或方式在本質上為示範性,並且該等特定具體實施例或範例並不應按限制性質所考量。本揭所述之特定副程式或方法可表示任意數量之處理策略的一或更多者。因此,各種所述動
作可為按所示序列執行、按其他序列執行、以同時方式執行,或者在某些情況下則逕予省略。
本揭示的主題項目包含各種製程、結構及裝置,本揭其他的特性、功能、動作及/或性質,以及該等的任何與所有等同項目之所有新穎且非顯知的組合與子組合。
Claims (20)
- 一種形成半導體結構的方法,該方法包含下列步驟:提供一含有矽的基板;形成一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8,並且疊覆於該基板上;利用一第一選擇性磊晶製程,形成含有矽且在一表面上疊覆於該緩衝層上的第一特徵;以及利用一第二選擇性磊晶製程,在該表面上形成含有Si1-yGey的第二特徵,其中y的範圍為自約0.1至1,其中該第一特徵是形成為疊覆於該緩衝層內的一p井區範圍,並且該第二特徵是形成為疊覆於該緩衝層內的一n井區範圍。
- 如申請專利範圍第1項所述之形成半導體結構的方法,其中形成一第一特徵的步驟包含形成一硬遮罩,在該硬遮罩內形成多個開口,並且在該等開口的至少一者內選擇性地形成該第一特徵。
- 如申請專利範圍第2項所述之形成半導體結構的方法,進一步包含移除該硬遮罩的步驟。
- 如申請專利範圍第1至3項任一項所述之形成半導體結構的方法,其中形成一第二特徵的步驟包含形成一硬遮罩,在該硬遮罩內形成多個開口,並且在該等開口的至少一者內選擇性地形成該第二特徵。
- 如申請專利範圍第4項所述之形成半導體結構的方法,進一步包含移除該硬遮罩的步驟。
- 如申請專利範圍第4項所述之形成半導體結構的方法,其中該硬遮 罩伸出於該第一特徵。
- 如申請專利範圍第6項所述之形成半導體結構的方法,進一步包含在該第一特徵與該第二特徵之間形成一空間,其中該空間小於50nm。
- 如申請專利範圍第1至3項任一項所述之形成半導體結構的方法,進一步包含蝕刻該第一特徵與該第二特徵以形成一或更多含有矽之翼片及一或更多含有Si1-yGey之翼片的步驟,其中y的範圍為自約0.1至1。
- 如申請專利範圍第8項所述之形成半導體結構的方法,進一步包含在低於約400℃的溫度處沉積絕緣材料的步驟。
- 如申請專利範圍第9項所述之形成半導體結構的方法,其中沉積絕緣材料的步驟包含利用H2Si[N(C2H5)2]2及O2電漿形成氧化物層。
- 如申請專利範圍第9項所述之形成半導體結構的方法,進一步包含移除該絕緣材料之一局部的步驟。
- 一種半導體結構,其包含:一含有矽的基板;一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.5,並且疊覆於該基板上;一形成於該緩衝層之內的p井區範圍;一形成於該緩衝層之內的n井區範圍;一或更多翼片結構,其是利用該p井區範圍和一含有矽的疊層所形成;一或更多翼片結構,其是利用該n井區範圍和一含有Si1-yGey的疊層所形成,其中y的範圍為自約0.1至1;以及 一絕緣層,此者為疊覆於該緩衝層之一局部上所形成。
- 如申請專利範圍第12項所述之半導體結構,其中該絕緣層是在低於約400℃的溫度處所形成。
- 如申請專利範圍第12項所述之半導體結構,其中該絕緣層是利用H2Si[N(C2H5)2]2和O2電漿所形成。
- 如申請專利範圍第12至14項任一項所述之半導體結構,其中該緩衝層在利用該p井區範圍和一含有矽的疊層所形成之一或更多翼片結構以及利用該n井區範圍和一含有Si1-yGey的疊層所形成之一或更多翼片結構之內的厚度為約20nm至約200nm。
- 一種CMOS裝置,其中包含:一含有矽的基板;一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.5,並且疊覆於該基板上;一形成於該緩衝層之內的p井區範圍;一形成於該緩衝層之內的n井區範圍;一或更多翼片結構,該等是利用該p井區範圍和一含有矽的疊層所形成;一或更多翼片結構,該等是利用該n井區範圍和一含有Si1-yGey的疊層所形成,其中y的範圍為自約0.1至1;以及一絕緣層,此者為疊覆於該緩衝層之一局部上所形成。
- 如申請專利範圍第16項所述之CMOS裝置,其中該絕緣層含有氧化矽。
- 如申請專利範圍第16或17項所述之CMOS裝置,其中該絕緣層是在低於約400℃的溫度處所形成。
- 如申請專利範圍第16或17項所述之CMOS裝置,其中該絕緣層是利用H2Si[N(C2H5)2]2和O2電漿所形成。
- 一種形成半導體結構的方法,該方法包含下列步驟:提供一含有矽的基板;形成一含有Si1-xGex的緩衝層,其中x的範圍為自0至約0.8,並且疊覆於該基板上;利用一第一選擇性磊晶製程,形成含有矽且在一表面上疊覆於該緩衝層上的第一特徵;以及利用一第二選擇性磊晶製程,在該表面上形成含有Si1-yGey的第二特徵,其中y的範圍為自約0.1至1,其中形成一第一特徵的步驟包含形成一硬遮罩,在該硬遮罩內形成多個開口,並且在該等開口的至少一者內選擇性地形成該第一特徵。
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KR20150035436A (ko) | 2015-04-06 |
US20160133628A1 (en) | 2016-05-12 |
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US10361201B2 (en) | 2019-07-23 |
US9240412B2 (en) | 2016-01-19 |
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