KR20180002061A - 전위 필터링을 통한 에피택셜층들의 형성 - Google Patents
전위 필터링을 통한 에피택셜층들의 형성 Download PDFInfo
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- KR20180002061A KR20180002061A KR1020170081515A KR20170081515A KR20180002061A KR 20180002061 A KR20180002061 A KR 20180002061A KR 1020170081515 A KR1020170081515 A KR 1020170081515A KR 20170081515 A KR20170081515 A KR 20170081515A KR 20180002061 A KR20180002061 A KR 20180002061A
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- 238000001914 filtration Methods 0.000 title claims description 17
- 230000015572 biosynthetic process Effects 0.000 title description 30
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000002243 precursor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- KAJBHOLJPAFYGK-UHFFFAOYSA-N [Sn].[Ge].[Si] Chemical compound [Sn].[Ge].[Si] KAJBHOLJPAFYGK-UHFFFAOYSA-N 0.000 claims description 12
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- 229910000078 germane Inorganic materials 0.000 claims description 9
- 239000012686 silicon precursor Substances 0.000 claims description 8
- 229910052805 deuterium Inorganic materials 0.000 claims description 6
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 125000005843 halogen group Chemical group 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 150000004756 silanes Chemical class 0.000 claims description 3
- KXCAEQNNTZANTK-UHFFFAOYSA-N stannane Chemical class [SnH4] KXCAEQNNTZANTK-UHFFFAOYSA-N 0.000 claims description 3
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 claims description 3
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 claims description 3
- VXGHASBVNMHGDI-UHFFFAOYSA-N digermane Chemical compound [Ge][Ge] VXGHASBVNMHGDI-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 9
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 8
- 230000002950 deficient Effects 0.000 description 7
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000005693 optoelectronics Effects 0.000 description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910005898 GeSn Inorganic materials 0.000 description 2
- 229920002472 Starch Polymers 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000019698 starch Nutrition 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- QCAWEPFNJXQPAN-UHFFFAOYSA-N methoxyfenozide Chemical compound COC1=CC=CC(C(=O)NN(C(=O)C=2C=C(C)C=C(C)C=2)C(C)(C)C)=C1C QCAWEPFNJXQPAN-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
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Abstract
두꺼운 결함 없는 에피택셜층의 형성 방법이 개시된다. 상기 방법은 두꺼운 결함 없는 에피택셜층을 형성하기 이전에 버퍼층 및 희생층을 형성하는 단계를 포함할 수 있다. 희생층 및 두꺼운 결함 없는 에피택셜층은 동일한 물질로, 동일한 공정 조건들에서 형성될 수 있다.
Description
[1] 본 발명은 에피택셜막들의 형성을 위한 공정들에 관한 것이다. 구체적으로, 본 발명은 전위 필터링과 연관된 에피택셜층들을 형성하기 위한 공정들에 관한 것이다. 더욱 상세하게는, 상기 공정들은 저머늄-주석 및 실리콘-저머늄-주석 에피택셜층들을 형성한다.
[2] 저머늄-주석 및 실리콘-저머늄-주석 층들은 광전자 어플리케이션들을 위한 우수한 적용 가능성을 가진다. 구체적으로, 두꺼운 스트레인-프리(strain-free) 층들은 다양한 광전자 소자 아키텍쳐들 내에서 요구될 수 있다. 격자-불일치된 기판들 상의 성장은 이러한 층들 내의 전위 형성을 통한 스트레인 완화(relaxation)를 필요로 한다. 그러나, 전위들의 존재에 의해 상기 에피택셜층의 전자 및 광학 특성들이 저하된다. 그 결과로, 두껍고 전위가 없는 에피택셜층의 형성을 가능하게 하는 기술이 요구된다.
본 발명은 전술한 문제점들을 해결하기 위한 금속성 막들의 선택적 퇴적 방법을 제공한다.
[3] 본 발명의 적어도 하나의 실시예에서 공정이 개시된다. 상기 공정은 기판 상에 에피택셜막을 형성하기 위한 것일 수 있고, 처리될 기판을 홀딩하는 반응 챔버를 제공하는 단계; 상기 기판 상에 버퍼층을 형성하는 단계; 상기 버퍼층의 상면(top) 상에, 저머늄-주석 또는 실리콘-저머늄-주석 중 적어도 하나를 포함하는 희생층을 형성하는 단계; 및 상기 희생층의 상면 상에, 상기 희생층과 동일한 물질을 포함하는 벌크층을 형성하는 단계;를 포함하며, 상기 희생층은 계면 스트레인에 의해 유발되는 적어도 하나의 전위(dislocation)를 포함하고; 상기 벌크층은 계면 스트레인에 의해 유발되는 전위들이 실질적으로 없다(free from).
[4] 본 발명 및 종래 기술에 대비하여 얻어지는 이점들을 요약하기 위한 목적들로서, 본 발명의 특정한 목적들 및 이점들이 여기서 위에 설명되었다. 물론, 본 발명의 임의의 특정한 실시예에 따라 이러한 목적들 또는 이점들 모두가 필수적으로 달성될 필요는 없음이 이해되어야 한다. 따라서, 예를 들어 당업자들은 본 발명이 여기서 개시되거나 제안될 수 있는 다른 목적들 또는 이점들을 필수적으로 달성하지 않고, 여기서 개시되거나 제안된 하나의 이점 또는 일군의 이점들을 달성하거나 최적화하는 방식으로 구체화되거나 수행될 수 있다는 점을 인식할 것이다.
[5] 이러한 실시예들 모두는 여기 개시된 본 발명의 범위 내에 속할 것이 의도된다. 이러한 및 다른 실시예들은 첨부된 도면들을 참조로 하는, 하기의 특정한 실시예들의 상세한 설명으로부터 당업자들에게 즉각적으로 명백해질 것이며, 본 발명이 개시된 임의의 특정 실시예(들)에 제한되는 것은 아니다.
[6] 여기 개시된 본 발명의 이러한 및 다른 특징들, 태양들 및 이점들은 특정한 실시예들의 도면들을 참조로 아래에서 설명되나, 도면들은 본 발명을 도시하도록 의도되며, 본 발명을 제한하도록 의도되지 않는다.
[7] 도 1은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[8] 도 2는 본 발명의 적어도 하나의 실시예에 따른 플로우차트이다.
[9] 도 3은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[10] 도 4는 본 발명의 적어도 하나의 실시예에 따른 플로우차트이다.
[11] 도 5는 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[12] 도면들에서의 구성요소들은 단순화와 명확성을 위하여 도시되었으며 필수적으로 치수에 맞추어 그려지지는 않았음이 이해될 것이다. 예를 들어, 본 개시의 도시된 실시예들의 이해를 향상시키도록 도면들에서 구성요소들 일부의 치수들은 다른 구성요소들에 대하여 과장될 수 있다.
[7] 도 1은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[8] 도 2는 본 발명의 적어도 하나의 실시예에 따른 플로우차트이다.
[9] 도 3은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[10] 도 4는 본 발명의 적어도 하나의 실시예에 따른 플로우차트이다.
[11] 도 5는 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물의 단면도이다.
[12] 도면들에서의 구성요소들은 단순화와 명확성을 위하여 도시되었으며 필수적으로 치수에 맞추어 그려지지는 않았음이 이해될 것이다. 예를 들어, 본 개시의 도시된 실시예들의 이해를 향상시키도록 도면들에서 구성요소들 일부의 치수들은 다른 구성요소들에 대하여 과장될 수 있다.
[13] 특정한 실시예들 및 실험예들이 아래에 개시되었지만, 본 발명이 특정하게 개시된 실시예들 및/또는 본 발명의 용법들 및 이들의 명백한 개조들 및 등가물들을 넘어 연장됨이 당업자에 의해 이해될 것이다. 따라서, 개시된 본 발명의 범위는 아래에 설명된 특정하게 개시된 실시예들에 의해 제한되어서는 안됨이 의도된다.
[14] 저머늄-주석 및 실리콘-저머늄-주석은 에피택셜하게 성장될 수 있다. 이러한 막들을 성장시키기 위한 접근법들은 "Methods of Forming Highly p-Type Doped Germanium Tin Films and Structures and Devices Including the Films"라는 발명의 명칭의 미국 특허 출원 번호 제14/827,177호, 및 "Methods of Forming Silicon Germanium Tin Films and Structures and Devices Including the Films"라는 발명의 명칭의 미국 특허 출원 번호 제14/956,115호에 개시되며, 이들은 참조문헌으로서 병합된다.
[15] 그러나 저머늄-주석 및 실리콘-저머늄-주석 막들의 형성 동안에 전위들이 형성될 수 있고, 상기 층을 통해 전파할(propagate) 수 있다. 이러한 전파된 전위들은 광전자 어플리케이션들에서 층들의 동작성에 악영향을 줄 수 있다.
[16] 본 발명의 적어도 하나의 실시예에 따르면, 상기 막들의 형성은 예를 들어 ASM International N.V.에 의해 제조된 Epsilon® 2000 Plus, Epsilon® 3200, 또는 Intrepid XP와 같은 에피택셜 화학 기상 퇴적(CVD) 공정을 위하여 사용되는 반응 시스템 내에서 일어날 수 있다. 반응 시스템은 직접 플라즈마, 및/또는 리모트 플라즈마 장치, 및/또는 방사성, 유도성, 및/또는 저항성 가열 시스템들과 같은 다양한 가열 시스템들을 포함할 수 있다.
[17] 도 1은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물(100)을 도시한다. 반도체 구조물(100)은 기판(110), 버퍼층(120), 희생층(130), 및 벌크층(140)을 포함할 수 있다. 기판(110)은 벌크 Si 웨이퍼, 벌크 Ge 웨이퍼, 또는 III-V족 반도체 물질들로 형성된 웨이퍼들로 구성될 수 있다.
[18] 버퍼층(120)은 기판(110)의 상면 상에 퇴적될 수 있다. 버퍼층(120)은 저머늄 또는 실리콘-저머늄-주석(SiGeSn)을 포함할 수 있다. 저머늄 또는 SiGeSn을 포함하는 버퍼층(120)은 대략 0.5 ㎛ 내지 1.5 ㎛의 두께까지 성장될 수 있다.
[19] 희생층(130)은 버퍼층(120)의 상면 상에 퇴적될 수 있다. 희생층(130)은 저머늄-주석 또는 실리콘-저머늄-주석을 포함할 수 있다. 희생층(130)은 1 내지 10 nm, 20 내지 100 nm, 또는 100 내지 200 nm 범위의 두께까지 성장될 수 있다. 희생층(130)은 버퍼층(120)보다 크지만, 벌크층(140)보다는 작거나 같은 격자상수(lattice constant)를 가질 수 있다.
[20] 희생층(130)은 고도로 결함이 있을 수 있고, 광전자 어플리케이션들에 유용성을 제공하지 못할 수 있다. 전위들은 격자 불일치의 결과로서 계면 스트레인 에너지에 기인할 수 있다. 예를 들어, 증가된 온도 및 압력은 전위들의 형성을 유발할 수 있다. 희생층(130)은 0.5 내지 5 at%, 5 내지 10 at%, 또는 10 내지 15 at% 범위의 퍼센트의 주석을 가질 수 있다.
[21] 벌크층(140)은 희생층(130)의 상면 상에 퇴적될 수 있다. 벌크층(140)은 희생층(130)과 동일한 물질, 저머늄-주석 또는 실리콘-저머늄-주석을 포함할 수 있다. 벌크층(140)은 100 내지 300 nm, 300 nm 내지 1000 nm, 또는 1000 내지 2000 nm 범위의 두께까지 성장될 수 있다. 벌크층(140)은 희생층(130)보다 더 크거나 같은 격자 상수를 가질 수 있다.
[22] 벌크층(140)이 희생층(130)의 전위들을 가지지 않을 수 있기 때문에, 벌크층(140)은 희생층(130)과는 다를 수 있다. 이는 벌크층(140)이 희생층(130)과 동일한 공정 조건들에서 성장될지라도 가능할 수 있다. 희생층(130)이 성장 동안에 임계 두께에 도달함에 따라, 이는 스트레인 완화된다. 희생층(130)의 스트레인 완화는 두 개의 구분된 층들이 형성되도록, 후속 공정 동안에 증가된 주석-병합을 가능하게 한다. 희생층 내의 결함들의 속성은 벌크층 내로의 추가적인 전파를 억제할 수 있다. 추가적으로, 벌크층(140)은 0.5 내지 5 at%, 5 내지 10 at%, 또는 10 내지 15 at% 범위의 퍼센트를 갖는 주석을 가질 수 있고, 이는 희생층(130)보다 더 높을 수 있다.
[23] 도 2는 본 발명의 적어도 하나의 실시예에 따른 반도체 장치의 제조를 위한 방법(200)을 나타낸다. 상기 공정은 반응 시스템과, 상기 반응 시스템 내에 처리될 기판을 제공하는 단계를 포함할 수 있다. 상기 공정은 또한 버퍼층 형성 단계(210), 희생층 형성 단계(220), 및 벌크층 형성 단계(230)를 포함할 수 있다.
[24] 버퍼층 형성 단계(210)는 저메인(germane, GeH4) 또는 디저메인(digermane, Ge2H6) 중 적어도 하나를 포함하는 전구체 가스의 흐름을 포함할 수 있다. 버퍼층 형성 단계(210) 동안의 반응 챔버의 압력은 5 내지 20 Torr, 20 내지 100 Torr, 또는 100 내지 760 Torr의 범위일 수 있다. 버퍼층 형성 단계(210) 동안의 반응 챔버의 온도는 300℃ 내지 400℃, 400℃ 내지 600℃, 또는 600℃ 내지 850℃의 범위일 수 있다.
[25] 희생층 형성 단계(220)는 실리콘 전구체 가스, 저머늄 전구체 가스, 및 주석 전구체 가스의 흐름을 포함할 수 있다. 실리콘 전구체 가스는 실레인(silane), 디실레인(disilane), 트리실레인(trisilane), 테트라실레인(tetrasilane), 네오펜타실레인(neopentasilane), 또는 다른 더 높은 차수의 실레인들 중 적어도 하나를 포함할 수 있다. 실리콘 전구체 가스는 또한 디보레인(diborane), 포스파인(phosphine) 또는 아르신(arsine)과 같은 포토닉 및/또는 반도체 장치들을 제조하는 데 사용되는 것들과 같이 하나 또는 그 이상의 도펀트 화합물들을 포함할 수 있다. 저머늄 전구체 가스는 저메인, 또는 더 높은 차수의 저메인들 중 적어도 하나를 포함할 수 있다. 저머늄 전구체 가스는 또한 디보레인, 포스파인 또는 아르신과 같은 포토닉 및/또는 반도체 장치들을 제조하는 데 사용되는 것들과 같이 하나 또는 그 이상의 도펀트 화합물들을 포함할 수 있다.
[26] 주석 전구체 가스는 염화주석(SnCl4), 듀테로화 스타난(deuterated stannane, SnD4), 및 Sn(CH3)4 - nXn (여기서, X는 H, D (deuterium), Cl, 또는 Br 이고, n은 0, 1, 2, 또는 3), ZSn(CH3)3 - nXn (여기서, Z는 H 또는 D이고, X 는 Cl 또는 Br이고, n은 0, 1, 또는 2), Z2Sn(CH3)2 - nXn (여기서, Z는 H 또는 D이고, X는 Cl 또는 Br이고, n은 0 또는 1), 또는 SnBr4의 화학식을 갖는 화합물들과 같은 메틸 및/또는 할라이드 치환된 스타난들 중 적어도 하나를 포함할 수 있다. 본 개시에서의 사용을 위하여 적합한 일부 예시적인 주석 전구체들은 "TIN PRECURSORS FOR VAPOR DEPOSITION AND DEPOSITION PROCESSES"라는 발명의 명칭의, 2013년 3월 4일 출원된 미국 출원 번호 제13/783,762호에 더욱 상세히 논의되며, 내용들이 본 개시와 상충되지 않는 한도까지 여기에 참조문헌으로서 병합된다.
[27] 희생층 형성 단계(220) 동안의 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위일 수 있다. 희생층 형성 단계(220) 동안의 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위일 수 있다.
[28] 벌크층 형성 단계(230)는 희생층 형성 단계(220) 내에서와 동일한 전구체 가스들의 흐름을 포함할 수 있다. 추가적으로, 벌크층 형성 단계(230) 동안의 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위일 수 있다. 벌크층 형성 단계(230) 동안의 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위일 수 있다.
[29] 도 3은 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물(300)을 나타낸다. 반도체 구조물(300)은 기판(310), 버퍼층(320), 전위 필터링층(들)(330), 및 벌크층(들)(340)을 포함할 수 있다. 기판(310)은 벌크 Si 웨이퍼, 벌크 Ge 웨이퍼, 또는 III-V족 반도체 물질들로 형성된 웨이퍼들로 구성될 수 있다.
[30] 버퍼층(320)은 기판(310)의 상면 상에 퇴적될 수 있다. 버퍼층(320)은 저머늄 또는 실리콘-저머늄-주석(SiGeSn)을 포함할 수 있다. 저머늄 또는 SiGeSn을 포함하는 버퍼층(320)은 대략 0.5 ㎛ 내지 1.5 ㎛의 두께까지 성장될 수 있다.
[31] 이러한 실시예에서, 층 벌크 조성 및 전위 필터링층 조성으로 구성되는 교대하는 층들이 상기 버퍼층 상에 퇴적된다. 전위 필터링층(들)(330)은 저머늄-주석 또는 실리콘-저머늄-주석을 포함할 수 있다. 상기 층(들)(330)은 1 내지 10 nm, 10 내지 20 nm, 또는 30 내지 40 nm 범위의 두께까지 성장될 수 있다. 상기 필터링층들은 상기 벌크층 또는 층들보다 작은 격자 상수들을 가질 수 있거나, 더 큰 격자 상수들을 가질 수 있다.
[32] 벌크층(들)(340)의 초기 에피택셜 성장은 고도로 결함성이 있을 수 있다. 상기 필터링층들 또는 층들(330)은 전위들이 최종 벌크층을 향해 전파하는 것을 차단하도록 교대하는 구성으로서 벌크층(340)을 형성하는 단계 내에 삽입될 수 있고, 상기 최종 벌크층은 전자 및 광전자 소자 어플리케이션들을 위하여 관심이 있는 층이다.
[33] 벌크층(들)(340)은 필터링층(들)(330)의 상면 상에 퇴적될 수 있다. 벌크층(340)은 희생층(330)과 동일한 물질, 저머늄-주석 또는 실리콘-저머늄-주석을 포함할 수 있다. 벌크층(340)은 1 내지 10 nm, 10 nm 내지 20 nm, 또는 20 내지 30 nm 범위의 두께까지 성장될 수 있다. 벌크층들(340)은 필터링층 또는 층들의 격자상수들보다 더 작거나, 더 큰 격자 상수를 가질 수 있다.
[34] 희생층(330) 및 벌크층(340)의 샌드위치 구조는 이러한 층들의 형성을 반복하는 단계에 의해 형성될 수 있다. 희생층들(330)은 복수의 벌크층들(340)을 포함하는 두꺼운 활성층에 대한 전위 필터들로서 작용할 수 있다.
[35] 도 4는 본 발명의 적어도 하나의 실시예에 따른 반도체 장치의 제조를 위한 방법(400)을 도시한다. 상기 방법은 반응 시스템과, 상기 반응 시스템 내에 처리될 기판을 제공하는 단계를 포함할 수 있다. 상기 공정은 또한 버퍼층 형성 단계(410), 전위 필터링층 형성 단계(420), 및 벌크층 형성 단계(430) 및 반복 루프(440)를 포함할 수 있다.
[36] 버퍼층 형성 단계(410)는 저메인 또는 디저메인 중 적어도 하나를 포함하는 전구체 가스의 흐름을 포함할 수 있다. 버퍼층 형성 단계(410) 동안의 반응 챔버의 압력은 5 내지 20 Torr, 20 내지 100 Torr, 또는 100 내지 760 Torr의 범위일 수 있다. 버퍼층 형성 단계(410) 동안의 반응 챔버의 온도는 300℃ 내지 400℃, 400℃ 내지 600℃, 또는 600℃ 내지 850℃의 범위일 수 있다.
[37] 전위 필터링층 형성 단계(420)는 실리콘 전구체 가스, 저머늄 전구체 가스, 및 주석 전구체 가스의 흐름을 포함할 수 있다. 실리콘 전구체 가스는 실레인, 디실레인, 트리실레인, 테트라실레인, 네오펜타실레인, 또는 다른 더 높은 차수의 실레인들 중 적어도 하나를 포함할 수 있다. 실리콘 전구체 가스는 또한 디보레인, 포스파인 또는 아르신과 같은 포토닉 및/또는 반도체 장치들을 제조하는 데 사용되는 것들과 같이 하나 또는 그 이상의 도펀트 화합물들을 포함할 수 있다. 저머늄 전구체 가스는 저메인, 또는 더 높은 차수의 저메인들 중 적어도 하나를 포함할 수 있다. 저머늄 전구체 가스는 또한 디보레인, 포스파인 또는 아르신과 같은 포토닉 및/또는 반도체 장치들을 제조하는 데 사용되는 것들과 같이 하나 또는 그 이상의 도펀트 화합물들을 포함할 수 있다.
[38] 주석 전구체 가스는 염화주석(SnCl4), 듀테로화 스타난(deuterated stannane, SnD4), 및 Sn(CH3)4 - nXn (여기서, X는 H, D (deuterium), Cl, 또는 Br 이고, n은 0, 1, 2, 또는 3), ZSn(CH3)3 - nXn (여기서, Z는 H 또는 D이고, X 는 Cl 또는 Br이고, n은 0, 1, 또는 2), Z2Sn(CH3)2 - nXn (여기서, Z는 H 또는 D이고, X는 Cl 또는 Br이고, n은 0 또는 1), 또는 SnBr4의 화학식을 갖는 화합물들과 같은 메틸 및/또는 할라이드 치환된 스타난들 중 적어도 하나를 포함할 수 있다. 본 개시에서의 사용을 위하여 적합한 일부 예시적인 주석 전구체들은 "TIN PRECURSORS FOR VAPOR DEPOSITION AND DEPOSITION PROCESSES"라는 발명의 명칭의, 2013년 3월 4일 출원된 미국 출원 번호 제13/783,762호에 더욱 상세히 논의되며, 내용들이 본 개시와 상충되지 않는 한도까지 여기에 참조문헌으로서 병합된다.
[39] 전위 필터링층 형성 단계(420) 동안의 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위일 수 있다. 전위 필터링층 형성 단계(420) 동안의 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위일 수 있다.
[40] 벌크층 형성 단계(430)는 전위 필터링층(420) 내에서와 동일한 전구체 가스들의 흐름을 포함할 수 있다. 추가적으로, 반응 챔버 내의 조건들은 다른 층들을 형성하기 위하여 두 단계들 사이에서 달라질 수 있다. 예를 들어, 벌크층 형성 단계(430) 동안의 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위일 수 있다. 벌크층 형성 단계(430) 동안의 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위일 수 있다. 벌크층과 전위 필터링층의 샌드위치 구조는 반복 루프(440)를 통해 달성될 수 있다.
[41] 도 5는 본 발명의 적어도 하나의 실시예에 따라 형성된 반도체 구조물(500)을 나타낸다. 반도체 구조물(500)은 기판(510), 버퍼층(520), 결함성 중간층(530), 및 벌크층(540)을 포함할 수 있다. 기판(510)은 벌크 Si 웨이퍼, 벌크 Ge 웨이퍼, 또는 III-V족 반도체 물질들로 형성된 웨이퍼들로 구성될 수 있다.
[42] 버퍼층(520)은 Ge 버퍼 층을 포함할 수 있다. 버퍼층(520)은 낮은 밀도의 스레딩 전위들(threading dislocations)을 갖는 스트레인-완화된 층일 수 있다.
[43] 결함성 중간층(530)은 저머늄 주석(GeSn)을 포함할 수 있다. 결함성 중간층(530)은 버퍼층(520) 및 벌크층(540) 사이의 격자 불일치로부터 기인할 수 있는 스레딩 전위들에 의해 특징지어질 수 있다. 결함성 중간층(530)은 버퍼층(520) 또는 벌크층(540)과 비교하여 더 얇은 층일 수 있다. 결함성 중간층(530)은 상기 층(530) 내로 고정된(pinned) 전위들을 갖는다.
[44] 벌크층(540)은 상대적으로 결함이 없는(defect-free) GeSn층을 포함할 수 있다. 벌크층(540)은 결함성 중간층(530) 내에 고정된 전위들에 기인하여 스트레인 완화될 수 있다.
[45] 다수의 변형들이 가능하기 때문에 여기 설명된 구성들 및/또는 접근법들은 속성에 있어서 예시적이며, 이러한 특정한 실시예들 또는 실험예들이 제한적 의미로 인식되지 않아야 함이 이해되어야 할 것이다. 여기 설명된 특정한 루틴들 또는 방법들은 임의의 수의 공정 전략들 중 하나 또는 그 이상을 대표할 수 있다. 따라서, 도시된 다양한 행위들은 도시된 순서들 내에서, 다른 순서들 내에서 수행될 수 있고, 일부 경우들에서 생략될 수 있다.
[46] 본 개시의 기술적 사상은 여기에 개시된 다양한 공정들, 시스템들, 및 구성들, 및 다른 피쳐들, 기능들, 행위들, 및/또는 특성들의 모든 신규하고 비자명한 조합 및 부조합들뿐 아니라 이들의 임의의 및 모든 등가물들을 포함한다.
Claims (19)
- 기판 상에 에피택셜막을 형성하기 위한 방법으로서,
처리될 기판을 홀딩하는 반응 챔버를 제공하는 단계;
상기 기판 상에 버퍼층을 형성하는 단계;
상기 버퍼층의 상면(top) 상에 희생층을 형성하는 단계; 및
상기 희생층의 상면 상에 벌크층을 형성하는 단계;를 포함하고,
상기 희생층은 계면 스트레인에 의해 유발되는 적어도 하나의 전위(dislocation)를 포함하고,
상기 벌크층은 계면 스트레인에 의해 유발되는 전위들이 실질적으로 없는(free from) 것을 특징으로 하는 방법. - 청구항 1에 있어서,
상기 희생층을 형성하는 단계 및 상기 벌크층을 형성하는 단계는 교대로 반복되는 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 벌크층은 상기 희생층과 동일한 물질을 포함하는 것을 특징으로 하는 방법. - 청구항 3에 있어서,
상기 벌크층은 0.5 내지 5 at%, 5 내지 10 at%, 또는 10 내지 15 at% 범위의 퍼센트를 갖는 주석을 갖는 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 희생층은 저머늄-주석 또는 실리콘-저머늄-주석 중 적어도 하나를 포함하는 것을 특징으로 하는 방법. - 청구항 5에 있어서,
상기 희생층은 0.5 내지 5 at%, 5 내지 10 at%, 또는 10 내지 15 at% 범위의 퍼센트를 갖는 주석을 갖는 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 기판은 벌크 실리콘 웨이퍼, 벌크 저머늄 웨이퍼, 또는 III-V족 반도체 물질로 형성된 웨이퍼 중 적어도 하나를 포함하는 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 희생층 내의 상기 적어도 하나의 전위는 격자 불일치(lattice mismatch)로부터의 계면 스트레인 에너지에 의해 유발되는 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 버퍼층을 형성하는 단계는, 저메인(germane) 또는 디저메인(digermane) 중 적어도 하나를 포함하는 전구체 가스를 흘리는 단계를 포함하는 것을 특징으로 하는 방법. - 청구항 9에 있어서,
상기 버퍼층을 형성하는 단계 동안의 상기 반응 챔버의 압력은 5 내지 20 Torr, 20 내지 100 Torr, 또는 100 내지 760 Torr의 범위이고,
상기 버퍼층을 형성하는 단계 동안의 상기 반응 챔버의 온도는 300℃ 내지 400℃, 400℃ 내지 600℃, 또는 600℃ 내지 850℃의 범위인 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 희생층을 형성하는 단계는, 실리콘 전구체 가스를 흘리는 단계, 저머늄 전구체 가스를 흘리는 단계, 및 주석 전구체 가스를 흘리는 단계를 포함하는 것을 특징으로 하는 방법. - 청구항 11에 있어서,
상기 실리콘 전구체 가스는 실레인(silane), 디실레인(disilane), 트리실레인(trisilane), 테트라실레인(tetrasilane), 네오펜타실레인(neopentasilane), 또는 다른 더 높은 차수의 실레인들 중 적어도 하나를 포함하는 것을 특징으로 하는 방법. - 청구항 11에 있어서,
상기 저머늄 전구체 가스는 저메인, 또는 더 높은 차수의 저메인들 중 적어도 하나를 포함하는 것을 특징으로 하는 방법. - 청구항 11에 있어서,
상기 주석 전구체 가스는 염화주석(SnCl4), 듀테로화 스타난(deuterated stannane, SnD4), 및 Sn(CH3)4 - nXn (여기서, X는 H, D (deuterium), Cl, 또는 Br 이고, n은 0, 1, 2, 또는 3), ZSn(CH3)3 - nXn (여기서, Z는 H 또는 D이고, X 는 Cl 또는 Br이고, n은 0, 1, 또는 2), Z2Sn(CH3)2 - nXn (여기서, Z는 H 또는 D이고, X는 Cl 또는 Br이고, n은 0 또는 1), 또는 SnBr4의 화학식을 갖는 화합물들과 같은 메틸 및/또는 할라이드 치환된 스타난들 중 적어도 하나를 포함하는 것을 특징으로 하는 방법. - 청구항 11에 있어서,
상기 희생층을 형성하는 단계 동안의 상기 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위이고,
상기 희생층을 형성하는 단계 동안의 상기 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위인 것을 특징으로 하는 방법. - 청구항 1 또는 청구항 2에 있어서,
상기 벌크층을 형성하는 단계는, 저메인 또는 디저메인 중 적어도 하나를 포함하는 전구체 가스를 흘리는 단계를 포함하는 것을 특징으로 하는 방법. - 청구항 16에 있어서,
상기 벌크층을 형성하는 단계 동안의 상기 반응 챔버의 압력은 500 내지 800 Torr, 600 내지 780 Torr, 또는 700 내지 760 Torr의 범위이고,
상기 벌크층을 형성하는 단계 동안의 상기 반응 챔버의 온도는 200℃ 내지 500℃, 275℃ 내지 475℃, 또는 300℃ 내지 420℃의 범위인 것을 특징으로 하는 방법. - 청구항 1의 방법에 의해 형성된 반도체 장치.
- 기판 상에 에피택셜막을 형성하기 위한 방법으로서,
처리될 기판을 홀딩하는 반응 챔버를 제공하는 단계;
상기 기판 상에 버퍼층을 형성하는 단계;
상기 버퍼층의 상면(top) 상에 제1 전위 필터링층을 형성하는 단계;
상기 제1 전위 필터링층의 상면 상에 제1 벌크층을 형성하는 단계;
상기 제1 벌크층의 상면 상에 제2 전위 필터링층을 형성하는 단계; 및
상기 제2 전위 필터링층의 상면 상에 제2 벌크층을 형성하는 단계;를 포함하고,
상기 제1 전위 필터링층 및 상기 제2 전위 필터링층은 계면 스트레인에 의해 유발되는 적어도 하나의 전위를 포함하고,
상기 제1 벌크층 및 상기 제2 벌크층은 계면 스트레인에 의해 유발되는 전위들이 실질적으로 없는 것을 특징으로 하는 방법.
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