CN107393867B - 形成金属内连线的方法和使用其制造半导体装置的方法 - Google Patents

形成金属内连线的方法和使用其制造半导体装置的方法 Download PDF

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CN107393867B
CN107393867B CN201710345544.5A CN201710345544A CN107393867B CN 107393867 B CN107393867 B CN 107393867B CN 201710345544 A CN201710345544 A CN 201710345544A CN 107393867 B CN107393867 B CN 107393867B
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layer
plasma
gas
metal
aln
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CN107393867A (zh
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李忠满
刘龙珉
金永宰
千承珠
金仙子
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ASM IP Holding BV
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Abstract

本发明揭示一种形成金属内连线的方法和使用其制造半导体装置的方法，所述形成金属内连线的方法包含：沉积低介电常数介电层、在所述低介电常数介电层中形成沟槽、在所述沟槽中形成势垒层、在所述势垒层上填充金属、使所述金属平坦化和在经平坦化的所述金属上形成罩盖层，其中所述罩盖层包含至少两个层。本揭示的半导体装置中的罩盖层具有更薄的厚度且具有优异的密封性质。

Description

形成金属内连线的方法和使用其制造半导体装置的方法
相关申请案的交叉参考
本申请案要求2016年5月17日在韩国知识产权局递交的韩国专利申请案第10-2016-0060210号的权益，所述申请案的揭示内容被以引用的方式全部并入本文中。
技术领域
一或多个实施例涉及一种形成金属内连线的方法和一种使用所述方法制造半导体装置制造设备中的半导体装置的方法。
背景技术
随着半导体装置的大小缩小，半导体装置的响应时间放慢，这是归因于布线结构中的金属内连线的线路电阻和包围金属内连线的层间介电层的介电常数。此类问题被称作电阻-电容(resistance-capacitance；RC)延迟。为了减小RC延迟，将金属内连线的材料从铝改变到具有低于铝的电阻的电阻的铜，且将包围金属内连线的层间介电层的材料改变到具有较低介电常数的材料。
根据现有技术，在化学机械平坦化(chemical-mechanical planarization；CMP)工艺后，将SiCN层沉积于布线层上。SiCN层防止蚀刻气体(例如干式蚀刻气体)或水(H2O)穿透到具有多孔结构和低介电常数的层间介电层内，且用作蚀刻终止层(etch-stop layer；ESL)。同时，随着装置的大小缩小，存在对于更薄SiCN层的需求。然而，更薄SiCN膜(例如具有小于的厚度)导致在防止水分或水穿透到子层低介电常数膜过程中的限制(归因于介电常数的限制等)。
发明内容
一或多个实施例包含一种沉积具有小于现有罩盖层(即，SiCN层)的厚度的厚度和用于保护子层低介电常数层不受水或水分的优异密封性质的薄膜的方法。
额外方面将部分地在接下来的描述中得到阐述，并且部分地将从所述描述显而易见或者可以通过对所提出的实施例的实践获悉。
根据一或多个实施例，一种形成金属内连线的方法包含：沉积低介电常数介电层；在所述低介电常数介电层中形成沟槽；在所述沟槽中形成势垒层；在所述势垒层上填充金属；使所述金属平坦化；以及在经平坦化的所述金属上形成罩盖层，其中所述罩盖层包含至少两个层且具有等于或小于的厚度。
形成所述罩盖层可包含沉积第一氮化物层和第二氮化物层。
沉积所述第一氮化物层和所述第二氮化物层可包含：沉积氮化铝(AlN)层；以及沉积氮化硅(SiN)层。
可通过使用等离子增强型原子层沉积(plasma-enhanced atomic layerdeposition；PEALD)方法来形成所述氮化铝层。沉积所述氮化铝层的沉积可包含进行多个循环，其中所述多个循环中的每一个包含：供应铝(A1)源气体；供应冲洗气体；供应反应性气体和通过使用等离子来活化所述反应性气体；以及供应所述冲洗气体，其中在所述多个循环期间将所述冲洗气体连续地供应到反应性空间。所述铝源气体可包含三甲基铝(Al(CH3)3或TMA)，且所述反应性气体可包含氮与氢的气体混合物。
可通过使用脉冲式等离子增强型化学气相沉积(脉冲式-PECVD、P-PECVD)方法来形成所述氮化硅层。沉积所述氮化硅层可包含进行多个循环，其中所述多个循环中的每一个包含：供应硅(Si)源气体；供应冲洗气体；供应反应性气体和通过使用等离子来活化所述反应性气体；以及供应所述冲洗气体，其中在所述多个循环期间将所述反应性气体、所述冲洗气体和所述等离子连续地供应到反应性空间。
所述硅源气体可包含硅烷气体。
所述硅源气体可包含来自硅甲烷、双(二乙胺基)硅烷(BDEAS)和二异丙胺基硅烷(DIPAS)当中的至少一种。
所述反应性气体可包含氮与氢的气体混合物。
所述氮化硅层的厚度可为至少
所述方法可进一步包含在沉积所述第一氮化物层和所述第二氮化物层的期间执行等离子处理，其中执行等离子处理包含进行至少一个循环，其中所述至少一个循环中的每一个包含：供应含氮气体；通过使用等离子来活化所述含氮气体；以及供应冲洗气体，其中在所述至少一个循环期间将所述金属上的金属氧化物还原成金属。
形成所述罩盖层可在范围从约250℃到约350℃的温度下执行。
所述第一氮化物层和所述第二氮化物层可在同一反应器中就地形成。
所述氮化铝层的厚度对所述氮化硅层的厚度的比率范围可从1∶1.5到1∶2。
当包含所述氮化铝层和所述氮化硅层的所述罩盖层在85℃的温度和85％的湿度下暴露达17小时时，薄膜的应力的改变可等于或小于50MPa。
在沉积所述氮化铝层的期间供应的等离子的功率对在沉积所述氮化硅层的期间供应的等离子的功率的比率范围可从约10∶1到8∶1。
根据一或多个实施例，一种制造半导体设备中的装置的方法包含：沉积低介电常数介电层；在所述低介电常数介电层中形成沟槽；在所述沟槽中形成势垒层；在所述势垒层上填充铜以形成铜层；使所述铜层平坦化；将等离子施加到经平坦化的所述铜层；通过使用等离子增强型原子层沉积(PEALD)方法在经平坦化的所述铜层上形成氮化铝(AlN)层；以及在已形成所述氮化铝层的反应器中就地在所述氮化铝层上形成氮化硅(SiN)层，其中所述氮化铝层的厚度与所述氮化硅层的厚度的总和范围从约到约其中形成所述氮化铝层和形成所述氮化硅层的是在范围从约250℃到约350℃的温度下执行。
根据一或多个实施例，一种制造半导体设备中的装置的方法包含：形成第一介电层；在所述第一介电层中形成第一金属层；以及在所述第一介电层和所述第一金属层上形成具有小于的厚度的罩盖层，其中形成所述罩盖层包含：形成氮化铝层；以及在所述氮化铝层上形成氮化硅层。
根据一或多个实施例，一种在半导体设备中制造的半导体装置包含：第一金属层；包围所述第一金属层的侧表面的第一介电层；接触所述第一金属层和所述第一介电层的至少一部分的氮化铝层；在所述氮化铝层上的氮化硅层；接触所述第一金属层的顶表面、所述氮化铝层的侧表面和所述氮化硅层的侧表面的第二金属层；以及包围所述第二金属层的侧表面的第二介电层，其中所述氮化铝层的厚度与所述氮化硅层的厚度的总和小于
附图说明
从以下结合附图进行的对实施例的描述，这些和/或其他方面将变得显而易见且更易于被了解。
图1到图8为用于解释根据实施例的形成金属内连线的方法的横截面图。
图9为根据实施例的形成金属内连线的方法和制造半导体制造设备中的装置的方法的流程图。
图10为用于解释根据实施例的形成金属内连线的方法和制造半导体制造设备中的装置的方法的时序图。
图11到图12为用于解释根据其它实施例的形成金属内连线的方法的横截面图。
图13为用于解释根据实施例的用于确定双层结构在基底上是否具有适当密封性质的实验的图。
具体实施方式
现在将参看附图更加充分地描述本揭示内容，在所述附图中示出了本揭示内容的实施例。
现在将参看附图在下文中更加充分地描述本揭示内容。然而，本揭示内容可以用许多不同形式体现，并且不应被解释为限于本文中所阐述的实施例。相反地，提供这些实施例使得本发明将透彻并且完整，并且将充分地向所属领域的一般技术人员传达本揭示内容的范围。
本文中所使用的术语仅仅是出于描述实施例的目的，且并不希望限制本揭示内容的实施例。如本文中所使用，除非上下文另外清晰地指示，否则单数形式“一”和“所述”也希望包含复数形式。将进一步理解，术语“包括”和/或“包含”在于本文中使用时指定所陈述的特征、整数、步骤、操作、元件、组件和/或群组的存在，但并不排除一或多个其它特征、整数、步骤、操作、元件、组件和/或其群组的存在或添加。如本文中所使用，术语“和/或”包含相关联的所列项目中的一或多个的任何和所有组合。
应理解，虽然本文中可使用术语“第一”、“第二”等来描述各种部件、区域、层和/或部分，但这些部件、区域、层和/或部分不应受这些术语限制。所述术语并不指具体次序、垂直关系或偏好，且仅用于区分一个部件、区域或部分与另一部件、区域或部分。因此，在不脱离本揭示内容的教示的情况下，下文将描述的第一部件、第一区域或第一部分可指第二部件、第二区域或第二部分。
现在将参看附图更加充分地描述本揭示内容，在所述附图中示出了本揭示内容的实施例。在附图中，应预期作为(例如)制造技术和/或公差的结果而从图示的形状的变化。因此，实施例不应当解释为限于本文中所说明的区域的特定形状，而是可包含(例如)由制造引起的形状偏差。
当在元件列表之前时，例如“...中的至少一个”的表述修饰元件的整个列表，而不是修饰所述列表中的个别元件。
图1到图8为用于解释根据实施例的形成金属内连线的方法(和制造半导体制造设备的方法)的横截面图。
首先，参看图1，电路元件20形成于基底10上。虽然电路元件20具有图1中的简单四边形形状，但电路元件20可具有各种其它形状中的任一个。举例来说，电路元件20可为存储器装置的栅极结构或电容器结构；或可为图像装置的光电二极管或驱动晶体管。绝缘层30可围绕电路元件20形成。
虽然在图1中电路元件20从基底10突出，但电路元件20可为形成于基底10中的掺杂区域或形成于基底10中的结构(例如埋栅结构)。在此情况下，绝缘层30可为包含于基底10中的元件。
参看图2，层间介电层1形成于电路元件20上。层间介电层1可形成于绝缘层30上。在任选实施例中，层间介电层1和绝缘层30可在相同时间形成。可沉积层间介电层1使得层间介电层1具有适合于通孔结构的厚度。
参看图3，通过蚀刻层间介电层1来暴露电路元件20。虽然在图3中说明包含双沟槽的通孔结构(即，包含具有不同厚度的上部孔洞UH和下部孔洞LH的孔洞结构)，但通孔结构不限于此。通孔结构可具有包含单个沟槽的形状或包含多个沟槽的形状。
为了形成包含双沟槽的通孔结构，可使用以下工艺。
-第一步骤：具有具第一宽度的开口的第一感光性图案形成于层间介电层1上。
-第二步骤：通过第一蚀刻(即，通过将第一感光性图案用作掩模来蚀刻层间介电层1)形成具有第一宽度的上部孔洞UH。
-第三步骤：形成接触上部孔洞UH的侧壁且暴露上部孔洞UH的底部的部分的第二感光性图案。
-第四步骤：通过第二蚀刻(即，通过将第二感光性图案用作掩模来蚀刻层间介电层1)形成具有第二宽度的下部孔洞LH，第二宽度小于第一宽度。
-第五步骤：去除第二感光性图案(和第一感光性图案)。
本揭示内容不限于以上工艺，且可使用用于形成包含双沟槽的通孔结构的其它工艺中的任一个。举例来说，在形成层间介电层1时可形成下部层间介电层，具有具第二宽度的开口的蚀刻终止层可形成于下部层间介电层上，且然后，上部层间介电层可形成于蚀刻终止层上。在此情况下，当蚀刻上部层间介电层时，暴露蚀刻终止层和具有第二宽度的开口，且不蚀刻在蚀刻终止层下的下部绝缘层，且蚀刻在具有第二宽度的开口下的下部绝缘层。因此，具有第一宽度的上部孔洞可形成于上部层间介电层中，且具有第二宽度的下部孔洞可形成于下部层间介电层中。
参看图4，扩散势垒层3形成于包含双沟槽的通孔结构上。扩散势垒层3可防止通孔结构的金属元件扩散到层间介电层1内。扩散势垒层3可包含来自(例如)钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钨(W)、氮化钨(WN)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)和氮化钨硅(WSiN)当中的至少一个。
参看图5，金属层2形成于扩散势垒层3上。金属层2可包含(例如)铜，且考虑与环境材料的热膨胀系数差，金属层2可由另一金属材料形成。虽未在图5中示出，但当通过使用铜形成金属层2时，铜种子层可首先形成于扩散势垒层3上，且然后可通过使用铜种子层形成金属层2。
参看图6，通过使用平坦化工艺去除金属层2的部分来使金属层2的顶表面平坦化。化学机械抛光(chemical mechanical polishing；CMP)工艺可用以使金属层2的顶表面平坦化。
参看图7和图8，具有双层结构的罩盖层可形成于经平坦化的金属层2上。罩盖层可防止干式蚀刻气体、水(H2O)、氧气(O2)或在CMP中使用的可溶化学物质在后续布线过程期间扩散/穿透到层间介电层1或金属内连线(例如铜布线)内。
一旦水或氧气穿透到层间介电层1内，那么层间介电层1的介电常数可增大，RC延迟可增大，且装置的响应时间可放慢。根据本发明，由于使用具有双层结构的罩盖层，因此可解决此类问题。并且，当上部层间介电层形成于下部金属层2上以便形成包含两个金属层的罩盖层时，归因于双层结构的罩盖层，可防止金属组件从金属层2扩散到上部层间介电层1和防止金属层2腐蚀。
本申请人已认识到，随着装置的大小缩小(和罩盖层的厚度减小)，包含现有SiCN单层的罩盖层防水或水分的密封性质降低，且因此已发明了甚至通过使用具有更薄厚度的罩盖层来沉积具有优异密封性质的膜的方法。
可通过使用以下工艺来执行方法。
-将第一层4沉积于金属层2上(见图7)。
-将第二层5沉积于第一层4上(见图8)。
第一层4与第二层5的厚度的总和可等于或小于并且，第一层4和第二层5中的每一个可为(例如)氮化物层。因此，根据实施例的具有双层结构的罩盖层的形成可包含沉积第一氮化物层和第二氮化物层。第一氮化物层和第二氮化物层可依序沉积，且可(例如)在同一反应器中就地形成。
在实施例中，第一层4可为氮化铝(AlN)层且第二层5可为氮化硅(SiN)层。举例来说，AlN层可通过使用等离子增强型(PEALD)来形成。并且，可通过使用PEALD或脉冲式等离子增强型化学气相沉积(P-PECVD)来形成SiN层。因此，可在范围从(例如)约250℃到约350℃的低温下执行罩盖层的形成。
在PEALD方法中，可重复地将前驱体与等离子交替且间歇地供应到反应器。在P-PECVD方法中，可连续地将等离子供应到反应器且可间歇地供应前驱体。
图9为根据实施例的形成金属内连线的方法和制造半导体制造设备中的装置的方法的流程图。制造方法可为根据以上实施例的制造方法的修改，且将不给出其重复解释。
参看图9，可如下执行在金属层2上形成具有双层结构的罩盖层的工艺。
在操作S110中，执行等离子处理。
在操作S120中，通过使用PEALD沉积AlN。
在操作S130中，通过使用P-PECVD沉积SiN。
在范围从约250℃到约350℃的相同温度下在反应器中就地连续地执行操作S110到操作S130。
首先，执行等离子处理的操作S110为将在为前端工艺的CMP工艺中形成于金属层2(例如铜布线内连线)上的金属氧化物(例如氧化铜(CuO))还原成金属(例如铜)的步骤。
在本揭示内容中，将氨(NH3)、氮(N2)和氢(H2)的气体混合物供应到安装了基底10且等离子被活化的反应空间。等离子的功率可为从约50W到约300W的范围。随着等离子被活化，可还原金属氧化物且可去除留在经平坦化的金属层2(见图6)的表面上的工艺残余物。
操作S110具有包含活化等离子的步骤和执行冲洗工艺的步骤的循环。在本实施例中，只将所述循环执行一次。然而，在任选实施例中，可将所述循环执行多次。
执行等离子处理的操作S110中的工艺条件简述如下。
-工艺温度：250℃到350℃
-反应性气体：N2/H2/NH3(气体混合物)
-等离子的功率：100W到300W
-工艺压力：2托到4托
-工艺序列：等离子点火/冲洗
-重复数目：1个循环
虽然在本实施例中使用在反应性空间中产生等离子的方法，但根据任选实施例，可通过使用远程等离子产生活性物质来执行等离子处理，且可将活性物质供应到反应空间内。
通过使用PEALD方法来执行沉积AlN的操作S120。在本实施例中，将三甲基铝(Al(CH3)3或TMA)用作铝(Al)源气体且将N2/H2的气体混合物用作反应性气体。当沉积AlN层的操作S120具有包含供应TMA的步骤、执行冲洗工艺的步骤、将等离子连同N2/H2的气体混合物一起供应的步骤和执行冲洗工艺的步骤的循环时，将所述循环重复执行18次，直到AlN层具有的厚度。
沉积AlN层的操作S120中的工艺条件简述如下。
-工艺温度：250℃到350℃
-源气体：TMA(三甲基铝)
-反应性气体：N2/H2(气体混合物)
-冲洗气体：氩(Ar)
-等离子的功率：200W到400W
-工艺压力：2托到4托
-工艺序列：TMA供应/冲洗/等离子点火/冲洗
-重复数目：18个循环
虽然在本实施例中使用在反应性空间中产生等离子的方法，但根据任选实施例，可通过使用远程等离子产生活性物质来执行等离子处理，且可将活性物质供应到反应空间内，如上所述。
通过使用P-PECVD方法来执行沉积SiN的操作S130。在本实施例中，将硅烷(SiH4)用作硅(Si)源，且将N2/H2的气体混合物用作反应性气体。在本实施例中，连续地供应反应性气体、冲洗气体和等离子，且间歇地供应SiH4。在优选实施例中，当通过供应SiH4达0.2秒且供应冲洗气体达2秒来执行一个循环时，重复地执行所述循环，例如执行所述循环50次，直到SiN层的厚度为
沉积SiN层的操作S130中的工艺条件简述如下。
-工艺温度：250℃到350℃
-源气体：SiH4
-反应性气体：N2/H2(气体混合物)
-冲洗气体：氩(Ar)
-等离子的功率：20W到50W
-工艺压力：2托到4托
-工艺序列：SiH4供应/冲洗
-重复数目：50个循环
虽然在本实施例中使用在反应空间中产生等离子的方法，但根据任选实施例，可通过使用远程等离子产生活性物质来执行等离子处理，且可将活性物质供应到反应空间内，如上所述。并且，虽然在本实施例中将SiH4用作基于硅烷的源气体，但可使用其它基于硅烷的源气体中的任一种。即，在操作S130中，可将基于氨基硅烷的硅源气体(例如双二乙基氨基硅烷(BDEAS)、双乙基甲基氨基硅烷(BEMAS)或二异丙基氨基硅烷(DIPAS))、基于硅烷氯化物的硅源气体(例如二氯硅烷(DCS)、三氯硅烷(TCS)或六氯硅烷(HCD))或其组合用作源气体。
在以上实施例中，由于沉积具有AlN/SiN的双层结构的罩盖层，因此可确保防水或水分的优异的密封性质。可防止铜扩散到低介电常数层间介电层内，且可在金属(铜)布线过程中防止水分穿透到低介电常数层间介电层内。即，本申请人已发现，实现薄AlN/SiN层，替代现有厚SiCN层，且确保防水或水分的优异的密封性质，且可形成具有随着装置的大小缩小所需要的等于或小于的厚度的AiN/SiN的薄膜。
并且，在以上实施例中，由于在低温下使用等离子工艺，替代现有热工艺，因此可使子层低介电常数介电层的变形和对子层低介电常数介电层的损坏最小化。由于通过使用PEALD工艺沉积膜，因此所述膜可比通过使用CVD形成的膜细且均匀地沉积。用于更高效地达成此类效果的等离子的功率的比率与在以上实施例中获得的值相同。即，在AlN层的沉积期间供应的等离子的功率范围从约200W到约400W，且在SiN层的沉积期间供应的等离子的功率范围从约20W到约50W。本发明人已发现，在AlN层的沉积期间供应的等离子的功率对在SiN层的沉积期间供应的等离子的功率的比率范围从10∶1到8∶1是最适宜的。
此外，根据以上实施例，由于在一个反应器中就地连续地沉积两个层，因此可沉积具有优异的密封性质的膜，而不暴露到空气且无归因于暴露的变形。
图10为用于解释根据实施例的形成金属内连线的方法和制造半导体制造设备中的装置的方法的时序图。制造方法可为根据以上实施例的制造方法的修改，且因此将不给出其重复解释。
参看图10，操作S110为在从时间t0到时间t2的周期期间执行等离子处理过程的步骤。在操作S110期间，在CMP前端工艺期间形成于金属内连线(例如铜布线)的表面上的金属氧化物(例如氧化铜)还原成金属元素。
举例来说，可将铜布线用作金属内连线，且可将惰性冲洗气体(例如N2)用作反应性气体。在此情况下，可不供应源气体(例如前驱体)。
在任选实施例中，可将NH3作为反应性气体供应，且可通过使用等离子来活化反应性气体以还原氧化铜。在此情况下，可另外供应冲洗气体。
虽然可将操作S110执行x次，但在实施例中，只将操作S110执行一次。
操作S120为在从时间t2到时间t6的周期期间执行PEALD工艺的步骤。在操作S120期间，可依序供应为源气体和反应物(例如反应性气体)的前驱体。更详细地，可在从时间t2到时间t3的周期期间供应源气体，且可在从时间t4到时间t5的周期期间供应反应性气体。可在从时间t2到时间t6的周期期间供应冲洗气体。
随着在从时间t4到时间t5的周期期间供应等离子，可活化反应性气体且经活化的反应性气体可与沉积到原子层层面的厚度的源气体反应以在基底10上沉积膜。在实施例中，在操作S120期间，可通过将TMA用作源气体且将N2与H2或NH3的气体混合物用作反应性气体来沉积AlN层。
当在从时间t2到时间t6的周期期间执行的步骤被称作一个循环时，可通过将所述循环重复执行m次来沉积多个原子层。优选地，可通过重复执行所述循环来沉积具有等于或大于的厚度的AlN层。更优选地，AlN层可经形成以具有范围从约到约的厚度。
虽然在从时间t4到时间t5的周期期间(即，在时间t4后)供应反应性气体(在此期间，在图10的操作S120中供应等离子)，但反应性气体可在供应等离子的时间t4前开始供应。因此，反应空间中的反应性气体密度可变得更均匀。因此，由于在时间t4前供应反应性气体，因此反应空间中的活性物质密度可变得更均匀，且在基底上的经沉积的膜的性质(例如湿式蚀刻速率比率(wet etch rate ratio；WERR))可变得更均匀。
在一些实施例中，可将例如Ar的惰性气体用作冲洗气体。可在从时间t2到时间t6的周期期间连续地将冲洗气体供应到反应器。在此情况下，如上所述，可将N2与H2或NH3的气体混合物作为反应性气体供应。
在任选实施例中，可将氮气用作冲洗气体。可将氮气用作反应性冲洗气体，且在此情况下，可只在供应等离子时活化氮气，且氮气可与源气体反应以形成AlN层。
操作S130为通过使用P-PECVD方法沉积SiN薄膜的步骤。可在已通过使用PEALD方法执行操作S120的反应器中就地执行通过使用P-PECVD方法沉积SiN薄膜。
在操作S120中沉积的AlN层在暴露于空气时可被氧化。因此，可通过在同一反应器中连续地执行操作S130来就地沉积AlN/SiN层。可通过在同一反应器中连续地执行操作S130来沉积AlN/SiN层。
在操作S130中，在从时间t6到时间t10的周期期间连续地供应反应性气体、冲洗气体和等离子，而在从时间t6到时间t7的周期期间间歇地供应源气体。当在从时间t6到时间t10的周期的期间执行的步骤被称作一个循环时，可通过将所述循环重复执行n次来沉积具有所要的厚度的SiN薄膜。在操作S130中，N2与H2或NH3的气体混合物可用作反应性气体。在实施例中，可将SiN薄膜沉积到等于或大于的厚度。在优选实施例中，可将SiN薄膜沉积到范围从约到约的厚度。
由于AlN层可具有如上所述的范围从约到约的厚度，且SiN薄膜可具有如上所述的范围从约到约的厚度，因此AlN层的厚度对SiN层的厚度的比率的范围可从1∶1.5到1∶2。然而，AlN层的厚度、SiN层的厚度和以上厚度之间的比率是被引入以满足在设计装置中所需要的工艺条件(膜必须具有小于的厚度且具有优异的密封性质的条件)(见图13)。因此，根据本揭示内容的双膜结构的个别厚度(即，个别层的厚度)不限于此。
在任选实施例中，在操作S110到S130期间，可将工艺温度维持在范围从约250℃到约350℃的低温。因此，虽然形成多金属层结构，但可防止对子层间介电层(明确地说，低介电常数介电层)的损坏。并且，由于在操作S110到S130期间施加等离子，因此反应时间可加速，沉积速率可高于现有热ALD工艺的沉积速率，且每单位时间的生产力可增大。并且，由于在循环中沉积具有薄厚度的薄膜，因此可改善薄膜均匀性。
图11和图12为说明根据其它实施例的在半导体设备中制造的装置的金属内连线的横截面图。根据实施例的金属内连线和包含金属内连线的半导体装置可为通过使用根据以上实施例的制造方法形成的结构，且因此将不给出其重复解释。
参看图11，金属内连线可为(例如)铜布线，且可应用到逻辑装置或存储器装置。金属内连线可包含为低介电常数介电层的层间介电层1、金属层2、扩散势垒层3和罩盖层。
层间介电层1可以由具有等于或小于2.5的低介电常数的材料形成，且可包含基于原硅酸四乙酯(Si(C2H5O)4或TEOS)的材料(例如SiOC或SICOH)。层间介电层1可具有多孔结构。层间介电层1可包围金属层2和扩散势垒层3的侧表面。
扩散势垒层3可防止金属层2的金属元素扩散和影响如上所述的层间介电层1的膜质量。金属层2为由铝或铜形成的布线层，且扩散势垒层3和金属层2可被称作一个元件(例如金属层2)。
罩盖层可具有包含如上所述的第一层4和第二层5的双层结构，且可包含第一氮化物层(例如氮化铝层)和第二氮化物层(例如氮化硅层)。第一层4可接触金属层2和层间介电层1的至少部分(例如顶表面)。第一层4可直接接触金属层2和层间介电层1(即，其间无元件)。第二层5可位于第一层4上。在任选实施例中，由于第一层和第二层就地形成，因此第一层4与第二层5可直接相互接触。
图12为说明通过在图11的布线结构(即，金属层2(被称作第一金属层2))上形成额外布线结构(即，第二金属层2′)获得的双层布线结构。
参看图12，第二金属层2′可形成于第一金属层2上。更详细，举例来说，当第一层4为氮化铝层且第二层5为氮化硅层时，第二金属层2′可接触第一金属层2的顶表面、氮化铝层的侧表面和氮化硅层的侧表面。
虽然在图12的本实施例中第二金属层由标号2′表示，但金属层(或第二金属层)不限于为标号2′。举例来说，可将第二金属层解释为包含含如上所述的金属的扩散势垒层3′。在此情况下，第二金属层可直接接触第一金属层2的顶表面、氮化铝层的侧表面和氮化硅层的侧表面。
图13为用于解释根据实施例的用于确定双层结构在基底上是否具有适当密封性质的实验的图。根据以上实施例，所述基底包含金属层、扩散势垒层和层间介电层(包含(例如)TEOS)。明确地说，TEOS易于吸收水。因为TEOS吸收水，所以基底的体积增大且产生压缩应力(见右下角的部分不合格(FAIL))。
为了形成用于防止水的渗透的罩盖层，当在具有85℃的温度和85％的湿度的大气中将罩盖层暴露17小时时，基底的应力的改变必须小于50MPa。一般来说，随着罩盖层的厚度减小，罩盖层更易受水的渗透影响。当常规SiCN罩盖层具有等于或小于的厚度时，不满足应力的改变必须小于50MPa的条件。
然而，根据实施例，由于使用包含不同材料的双层结构，因此可满足应力的改变必须小于50MPa的条件。
表1示出在通过图13的实验评估根据实施例的双层结构(包含AlN /SiN)防水(H2O)的密封性质后获得的结果。
表1
槽编号 AlN厚度 SiN厚度 Si前驱体 应力的改变(ΔMPa) 合格/不合格
01 20 30 BDEAS -38 合格
02 20 40 BDEAS -40 合格
03 20 30 SiH<sub>4</sub> -4 合格
04 20 40 SiH<sub>4</sub> -5 合格
如表1中所示，具有等于或小于的厚度的现有SiCN层的密封性质降级，而根据本揭示内容的具有更薄厚度的层具有优异的密封性质。
根据一或多个实施例，替代为现有罩盖层的SiCN膜，沉积A1N薄膜，且将SiN薄膜沉积于AlN薄膜上。归因于此双层结构，罩盖层的厚度可小于SiCN膜的厚度的若干纳米，且罩盖层可确保优异的密封性质。
为了本揭示内容的更好理解，实施例不应当被解释为限于本文中所说明的部分的特定形状，而是可包含形状的偏差。
虽然已经参看附图描述一或多个实施例，但所属领域的一般技术人员将理解，在不脱离由所附权利要求定义的本揭示内容的精神和范围的情况下，可在其中作出各种形式和细节的改变。

Claims (15)

1.一种形成金属内连线的方法，其特征在于，所述方法包括：
沉积低介电常数介电层；
在所述低介电常数介电层中形成沟槽；
在所述沟槽中形成势垒层；
在所述势垒层上填充金属；
使所述金属平坦化；以及
在经平坦化的所述金属上形成罩盖层，其中所述罩盖层包括至少两个层且具有等于或小于的厚度，
其中形成所述罩盖层包括：
沉积第一氮化物层，包括通过使用等离子增强型原子层沉积方法形成氮化铝层；以及
沉积第二氮化物层，包括通过使用脉冲式等离子增强型化学气相沉积方法形成氮化硅层，
其中所述氮化铝层的厚度对所述氮化硅层的厚度的比率范围为从1:1.5到1:2，
其中在沉积所述氮化铝层的期间供应的等离子的功率对在沉积所述氮化硅层的期间供应的等离子的功率的比率范围为从10:1到8:1。
2.根据权利要求1所述的形成金属内连线的方法，其中沉积所述氮化铝层包括进行多个循环，
其中所述多个循环中的每一个包括：
供应铝源气体；
供应冲洗气体；
供应反应性气体且通过使用等离子以活化所述反应性气体；以及
供应所述冲洗气体，
其中在所述多个循环期间将所述冲洗气体连续地供应到反应空间。
3.根据权利要求2所述的形成金属内连线的方法，其中所述铝源气体包括三甲基铝，且所述反应性气体包括氮与氢的气体混合物。
4.根据权利要求1所述的形成金属内连线的方法，其中沉积所述氮化硅层包括进行多个循环，
其中所述多个循环中的每一个包括：
供应硅源气体；
供应冲洗气体；
供应反应性气体且通过使用等离子以活化所述反应性气体；以及
供应所述冲洗气体，
其中在所述多个循环期间将所述反应性气体、所述冲洗气体和所述等离子连续地供应到反应空间。
5.根据权利要求4所述的形成金属内连线的方法，其中所述硅源气体包括硅和氢元素。
6.根据权利要求5所述的形成金属内连线的方法，其中所述硅源气体包括来自硅甲烷、双(二乙胺基)硅烷和二异丙胺基硅烷当中的至少一种。
7.根据权利要求4所述的形成金属内连线的方法，其中所述反应性气体包括氮与氢的气体混合物。
8.根据权利要求1所述的形成金属内连线的方法，其中所述氮化硅层的厚度为至少
9.根据权利要求1所述的形成金属内连线的方法，进一步包括在沉积所述第一氮化物层和所述第二氮化物层前执行等离子处理，
其中执行所述等离子处理包括进行至少一个循环，
其中所述至少一个循环中的每一个包括：
供应含氮气体；
通过使用等离子以活化所述含氮气体；以及
供应冲洗气体，
其中在所述至少一个循环期间将所述金属上的金属氧化物还原成金属。
10.根据权利要求1所述的形成金属内连线的方法，其中形成所述罩盖层是在范围从250℃到350℃的温度下执行。
11.根据权利要求1所述的形成金属内连线的方法，其中所述第一氮化物层和所述第二氮化物层在同一反应器中就地形成。
12.根据权利要求1所述的形成金属内连线的方法，其中，当包括所述氮化铝层和所述氮化硅层的所述罩盖层在85℃的温度和85％的湿度下暴露达17小时时，薄膜的应力的改变为等于或小于50MPa。
13.一种制造半导体装置的方法，其特征在于，所述方法包括：
沉积低介电常数介电层；
在所述低介电常数介电层中形成沟槽；
在所述沟槽中形成势垒层；
在所述势垒层上填充铜以形成铜层；
使所述铜层平坦化；
将等离子施加到经平坦化的所述铜层；
通过使用等离子增强型原子层沉积方法在经平坦化的所述铜层上形成氮化铝层；以及
在已形成所述氮化铝层的反应器中就地在所述氮化铝层上，通过使用脉冲式等离子增强型化学气相沉积方法形成氮化硅层，
其中所述氮化铝层的厚度与所述氮化硅层的厚度的总和范围为从到
其中形成所述氮化铝层和形成所述氮化硅层为在范围从250℃到350℃的温度下执行，
其中所述氮化铝层的厚度对所述氮化硅层的厚度的比率范围为从1:1.5到1:2，
其中在沉积所述氮化铝层的期间供应的等离子的功率对在沉积所述氮化硅层的期间供应的等离子的功率的比率范围为从10:1到8:1。
14.一种制造半导体装置的方法，其特征在于，所述方法包括：
形成第一介电层；
在所述第一介电层中形成第一金属层；以及
在所述第一介电层和所述第一金属层上形成具有小于的厚度的第一罩盖层，
其中形成所述第一罩盖层包括：
通过使用等离子增强型原子层沉积方法形成氮化铝层；以及
在所述氮化铝层上，通过使用脉冲式等离子增强型化学气相沉积方法形成氮化硅层，
其中所述氮化铝层的厚度对所述氮化硅层的厚度的比率范围为从1:1.5到1:2，
其中在沉积所述氮化铝层的期间供应的等离子的功率对在沉积所述氮化硅层的期间供应的等离子的功率的比率范围为从10:1到8:1。
15.根据权利要求14所述的制造半导体装置的方法，进一步包括：
在所述第一罩盖层上形成第二介电层；
在所述第二介电层中形成第二金属层；以及
在所述第二介电层和所述第二金属层上形成具有小于的厚度的第二罩盖层，
其中形成所述第二罩盖层包括：
形成第二氮化铝层；以及
在所述第二氮化铝层上形成第二氮化硅层，且
其中所述第二金属层的部分接触所述第一金属层和所述第一罩盖层的侧壁。
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