TWI429086B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI429086B TWI429086B TW098136152A TW98136152A TWI429086B TW I429086 B TWI429086 B TW I429086B TW 098136152 A TW098136152 A TW 098136152A TW 98136152 A TW98136152 A TW 98136152A TW I429086 B TWI429086 B TW I429086B
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Description
本發明有關於使用氧化鋅(ZnO)之半導體裝置以及其之製造方法。
液晶顯示裝置或電致發光(EL)顯示裝置之顯示面板的半導體裝置,例如薄膜電晶體(TFT)之半導體部分通常係使用非晶矽(a-Si)或多晶矽(poly-Si)所形成。
矽(Si)沒有大能帶隙(例如,單晶矽為1.1eV)並且吸收肉眼可見之光。藉由光線照射,電子與電洞(載子)形成於Si中。若使用Si作為TFT之通道形成區域,則即使在關閉(OFF)狀態藉由光線照射仍會在通道形成區域中產生載子。接著,電流會流動於源極區域以及汲極區域之間。於OFF狀態中流動之電流稱為“OFF漏電流”。若此電流值為高,則顯示面板無法正常操作。因此,因此形成遮光薄膜使光線不會照射到Si薄膜。然而,當遮光薄膜形成時程序會變得負責,因為需要有沉積步驟、光微影步驟以及蝕刻步驟。
為了解決此問題,已開始致力於使用氧化鋅(ZnO)之透明電晶體,氧化鋅為具有比Si更大的3.4eV能帶隙之半導體。針對此種透明電晶體,能帶隙比可見光線中的光能量更大,並且不會吸收可見光。因此,具有若以光線照射仍不會增加OFF漏電流的優點。
使用ZnO作為通道形成區域之半導體裝置揭露例如於參考文獻1中。參考第7A圖揭露使用ZnO之半導體裝置的結構。
於第7A圖中之半導體裝置具有源極電極1001以及汲極電極1002、配置成為與源極電極1001以及汲極電極1002接觸之ZnO層1003,以及堆疊在ZnO層1003上之閘極絕緣層1004以及在絕緣基底1000之上的諸如玻璃基底之閘極電極1005。
針對源極電極1001以及汲極電極1002,使用導電ZnO。將導電ZnO摻雜下列之一:硼(B)、鋁(Al)、鎵(Ga)、銦(In)或鉈(Tl),這些為III族元件;氟(F)、氯(Cl)、溴(Br)或碘(I),這些為VII族元件;鋰(Li)、鈉(Na)、鉀(K)、銣(Rb)或鍶(Cs),這些為I族元件;以及氮(N)、磷(P)、砷(As)、銻(Sb)或鉍(Bi),這些為V族元件。
[參考文獻1]日本公開專利申請案第2000-150900號
根據本發明人之詳察,發現到當藉由蝕刻形成第7A圖中所示之頂部閘極半導體裝置的源極電極1001與汲極電極1002時,於某些情況中基底1會被蝕刻。即使在基底1000上形成藉由使用氧化矽薄膜或氮氧化矽薄膜而形成的底部薄膜1006的情況中,當蝕刻該底部薄膜時有時候會暴露出基底1000的表面。此外,在顯示於第7B圖中的底部閘極半導體裝置的情況中,發現到當藉由蝕刻形成源極電極1001與汲極電極1002時,會蝕刻藉由使用氧化矽薄膜或氮氧化矽薄膜而形成的閘極絕緣薄膜1004。
在頂部閘極半導體裝置的情況中,當蝕刻藉由使用氧化矽薄膜或氮氧化矽薄膜而形成的玻璃基底100或底部薄膜1006時,諸如鈉之雜質會從基底1000擴散至半導體薄膜1003中,因此使特性惡化。
在底部閘極半導體裝置(第7B圖)的情況中,若當藉由蝕刻形成源極電極1001與汲極電極1002時蝕刻閘極絕緣薄膜1004,則特性會不穩定並會導致故障。
有鑒於上述情形,本發明之一目的在於提供一種即使使用znO半導體薄膜作為通道形成區域以及使用添加有n型或p型雜質的znO薄膜作為源極電極與汲極電極仍不會產生缺陷或故障之半導體裝置以及其製造方法。
本發明之半導體裝置的一態樣具有於氧化矽薄膜或氮氧化矽薄膜上之Al薄膜或Al合金薄膜,以及於Al薄膜或Al合金薄膜上之添加有n型或p型雜質的znO薄膜。於此說明書中,“氧化矽薄膜”、“氮氧化矽薄膜”、“Al薄膜”、“Al合金薄膜”以及“znO薄膜”分別意指含有氧化矽之薄膜、含有氮氧化矽之薄膜、含有Al之薄膜、含有Al合金之薄膜、含有znO之薄膜。
本發明之半導體裝置的一態樣具有於閘極電極上藉由使用氧化矽薄膜或氮氧化矽薄膜而形成之閘極絕緣薄膜、於閘極絕緣薄膜上之Al薄膜或Al合金薄膜、於Al薄膜或Al合金薄膜上之添加有n型或p型雜質的ZnO薄膜以及於添加有n型或p型雜質的ZnO薄膜以及閘極絕緣薄膜上之ZnO半導體薄膜。
本發明之半導體裝置的一態樣具有於氧化矽薄膜或氮氧化矽薄膜上之Al薄膜或Al合金薄膜、於Al薄膜或Al合金薄膜上之添加有n型或p型雜質的ZnO薄膜、於氧化矽薄膜或氮氧化矽薄膜和添加有n型或p型雜質的ZnO薄膜上之ZnO半導體薄膜、於ZnO半導體薄膜上之閘極絕緣薄膜以及於閘極絕緣薄膜上之閘極電極。
本發明之半導體裝置的製造方法的一態樣具有下列步驟:形成氧化矽薄膜或氮氧化矽薄膜、於氧化矽薄膜或氮氧化矽薄膜上形成Al薄膜或Al合金薄膜、於Al薄膜或Al合金薄膜上形成添加有n型或p型雜質的ZnO薄膜,其中藉由第一蝕刻蝕刻添加有n型或p型雜質的ZnO薄膜以具有島狀的形狀,以及藉由第二蝕刻蝕刻Al薄膜或Al合金薄膜以具有島狀的形狀。
本發明之半導體裝置的製造方法的一態樣,其中在第二蝕刻之後於添加有n型或p型雜質的ZnO薄膜以及氧化矽薄膜或氮氧化矽薄膜之上形成ZnO半導體薄膜。
於底部閘極半導體裝置的情況中,在形成閘極電極之後,形成使用氧化矽薄膜或氮氧化矽薄膜形成的閘極絕緣薄膜於閘極電極之上。
於頂部閘極半導體裝置的情況中,在形成ZnO半導體薄膜之後,形成閘極絕緣薄膜並且形成閘極電極。
本發明之第一蝕刻可為濕蝕刻。
本發明之第一蝕刻可為使用緩衝的氟酸之濕蝕刻。
本發明之第一蝕刻可為乾蝕刻。
本發明之第一蝕刻可為使用CH4
(甲烷)氣體之乾蝕刻。
本發明之第二蝕刻可為濕蝕刻。
本發明之第二蝕刻可為使用光阻用之顯影溶液之濕蝕刻。
本發明之第二蝕刻可為使用有機鹼性溶液之濕蝕刻。
本發明之第二蝕刻可為使用氫氧化四甲基銨(TMAH)之濕蝕刻。
本發明之半導體裝置的一態樣具有閘極電極、於該閘極電極上之閘極絕緣薄膜、於該閘極絕緣薄膜上之包含金屬材料的第一薄膜、於該第一薄膜上之包含透明半導體材料以及n型或p型雜質之第二薄膜以及於該第二薄膜與該閘極絕緣薄膜上之包含該透明半導體材料之第三薄膜。
本發明之半導體裝置的一態樣具有於基底上之絕緣薄膜、於該絕緣薄膜上之包含金屬材料的第一薄膜、於該金屬薄膜上之包含透明半導體材料以及n型或p型雜質之第二薄膜、於該絕緣薄膜與該第二薄膜上之包含該透明半導體材料之第三薄膜、於該第三薄膜上之閘極絕緣薄膜以及於該閘極絕緣薄膜上之閘極電極。
本發明之製造半導體裝置的方法之一態樣具有下列步驟:於基底上形成絕緣薄膜、於該絕緣薄膜上形成包含金屬材料的第一薄膜、於該第一薄膜上形成包含透明半導體材料以及n型或p型雜質之第二薄膜、蝕刻該第二薄膜以及蝕刻該第一薄膜。
本發明之製造半導體裝置的方法之一態樣具有下列步驟:於基底上形成閘極電極、於該閘極電極上形成閘極絕緣薄膜、於該閘極絕緣薄膜上形成包含金屬材料的第一薄膜、於第二薄膜上形成包含透明半導體材料以及n型或p型雜質之第二薄膜、蝕刻該第二薄膜以及蝕刻該第一薄膜。
於頂部閘極半導體裝置中,不會蝕刻使用玻璃基底、氧化矽薄膜或氮氧化矽薄膜形成之底部薄膜,並且諸如鈉之雜質不會從基底擴散至半導體薄膜,所以不會惡化其之特性。
於底部閘極半導體裝置中,不會蝕刻閘極絕緣薄膜,並且其特性不會變得不穩定。
由於使用Al作為源極電極與汲極電極的一部分,得以降低電線的電阻。
在此描述底部閘極半導體裝置。
第1A圖為顯示本發明之一實施例的一範例的剖面圖。於第1A圖中,參考符號1代表基底、參考符號3代表閘極電極、參考符號5代表閘極絕緣薄膜、參考符號10代表源極電極、參考符號10a代表第一導電薄膜、參考符號10b代表第二導電薄膜、參考符號11代表汲極電極、參考符號11a代表第一導電薄膜、參考符號11b代表第二導電薄膜以及參考符號13代表半導體薄膜。可在半導體薄膜13上形成鈍化或平坦化用之絕緣薄膜。
閘極電極3形成於基底1上、閘極絕緣薄膜5形成於閘極電極3上以及源極電極10以及汲極電極11形成於閘極絕緣薄膜5上。源極電極10係由具有第一導電薄膜10a以及第二導電薄膜10b的多層薄膜形成,以及汲極電極11係由具有第一導電薄膜11a以及第二導電薄膜11b的多層薄膜形成。第三導電薄膜可形成於第一導電薄膜10a以及第二導電薄膜10b之間,或在第一導電薄膜11a以及第二導電薄膜11b之間。可分別形成源極電極10以及汲極電極11以經由閘極絕緣薄膜5與閘極電極3部分重疊。半導體薄膜13形成於在閘極絕緣薄膜5之上的源極電極10以及汲極電極11上。
在此描述各結構。
(1)基底
下述可用於形成基底:使用薄膜基底、諸如矽土之絕緣材料以及可在後續步驟中抵抗製程溫度之塑膠基底以及類似者形成基底。在使用塑膠基底作為基底1的情況中,可使用下列者:聚碳酸酯(PC)、聚醚碸(PES)、聚對苯二甲酸二乙酯(PET)、聚萘二酸乙二醇酯(PEN)或類似者。在塑膠基底的情況中,可在表面上提供無機或有機層作為氣體阻障層。於塑膠基底的製程中於基底表面上產生因為灰塵或類似者引起的隆起的情況中,可在將基底利用CMP磨光或將其表面平坦化之後使用基底。諸如氧化矽(SiOx)、氧化氮(SiNx)、氧氮化矽(SiOxNy)(X>Y)之絕緣薄膜可形成於基底上,以防止雜質或類似者從基底側擴散出去。
(2)閘極電極
可使用鋁(Al)薄膜、鎢(W)薄膜、鉬(Mo)薄膜、鉭(Ta)薄膜、銅(Cu)薄膜、鈦(Ti)薄膜以及含有元件為主要構件之合金材料(例如,Al合金薄膜、鉬鎢(MoW)合金薄膜)或類似者形成閘極電極。可使用由摻雜諸如磷(P)的雜質元件所代表之多晶矽薄膜。閘極電極3可為單一層或者兩或更多層堆疊的多層薄膜。
(3)閘極絕緣薄膜
可使用含有矽作為主要構件之絕緣薄膜(如氧化矽薄膜以及氮氧化矽薄膜)形成閘極絕緣薄膜5。此外,它可為單一層或多層薄膜。
(4)源極電極以及汲極電極
源極電極10係由具有第一導電薄膜10a以及第二導電薄膜10b之多層薄膜所形成,並且汲極電極11係由具有第一導電薄膜11a以及第二導電薄膜11b之多層薄膜所形成。
作為第一導電薄膜,可使用Al薄膜、諸如鋁鎳(AlNi)薄膜以及鋁釹(AlNd)薄膜之Al合金薄膜。作為第二導電薄膜,可使用添加硼(B)、鋁(Al)、鎵(Ga)、磷(P)或砷(As)之p型或n型雜質的氧化鋅(ZnO)。可提供諸如Ti薄膜之金屬薄膜作為在第一導電薄膜與第二導電薄膜之間的第三導電薄膜。
(5)半導體薄膜
ZnO薄膜用作為半導體薄膜。由於與半導體薄膜接觸的源極電極以及汲極電極具有添加有p型或n型雜質的ZnO薄膜,它們可輕易地與半導體薄膜連接。
(6)絕緣薄膜
諸如鈍化薄膜與平坦化薄膜之絕緣薄膜可形成在半導體薄膜13之上,雖未顯示。可使用氧化矽(SiOx)、氧化氮(SiNx)、氧氮化矽(SiOxNy)(x>y)、氧化氮化矽(SiNxOy)(x>y)、旋塗玻璃(SOG)薄膜、或丙烯醛基的有機樹脂薄膜或上述之多層薄膜。
於底部閘極半導體裝置中,在製程中並未蝕刻閘極絕緣薄膜,並且特性不會變得不穩定。Al用為源極電極以及汲極電極的一部分,藉此降低電線的電阻。
在此描述頂部閘極半導體裝置。
第1B圖為顯示本發明之一實施例的一範例的剖面圖。於第1B圖中,參考符號1代表基底、參考符號20代表絕緣薄膜、參考符號25代表源極電極、參考符號25a代表第一導電薄膜、參考符號25b代表第二導電薄膜、參考符號26代表汲極電極、參考符號26a代表第一導電薄膜、參考符號26b代表第二導電薄膜以及參考符號27代表半導體薄膜、參考符號28代表閘極絕緣薄膜以及參考符號29代表閘極電極。
絕緣薄膜20形成於基底1上,以及源極電極25與汲極電極26形成在絕緣薄膜20之上。源極電極25係由具有第一導電薄膜25a以及第二導電薄膜25b的多層薄膜形成,以及汲極電極26係由具有第一導電薄膜26a以及第二導電薄膜26b的多層薄膜形成。第三導電薄膜可形成於第一導電薄膜25a以及第二導電薄膜25b之間,或在第一導電薄膜26a以及第二導電薄膜26b之間。半導體薄膜27形成於在絕緣薄膜20之上的源極電極25以及汲極電極26上、閘極絕緣薄膜28形成於半導體薄膜27上以及閘極電極29形成於閘極絕緣薄膜28之上。可形成閘極電極29以與隔著閘極絕緣薄膜28以及半導體薄膜27之源極電極以及汲極電極部分重疊。
在此描述各結構。
針對基底、源極電極、汲極電極、半導體薄膜以及閘極電極,可使用描述於實施例1中的相同者。
(1)於基底上之絕緣薄膜
氧化矽或氧氮化矽係形成為絕緣薄膜20,以防止雜質或類似者從基底1上的基底側擴散出去。此外,絕緣薄膜可為單層或多層薄膜。
(2)閘極絕緣薄膜
可使用含有矽作為主要構件之絕緣薄膜(如氧化矽薄膜、氮氧化矽薄膜、氧化氮化矽薄膜以及氮化矽薄膜)形成閘極絕緣薄膜28。此外,它可為單一層或多層薄膜。
(3)於閘極電極上之絕緣薄膜
諸如鈍化薄膜與平坦化薄膜之層間絕緣薄膜可形成在閘極電極29之上,雖未顯示。可使用SiOx、SiON薄膜、SiNO薄膜、旋塗玻璃(SOG)薄膜、或丙烯醛基的有機樹脂薄膜或上述之多層薄膜。
於頂部閘極半導體裝置中,使用氧化矽薄膜或氮氧化矽薄膜形成的基底或底部薄膜並未受到蝕刻,使諸如鈉之雜質不會從基底據散到半導體薄膜中,並且不會使特性惡化。Al用為源極電極以及汲極電極的一部分,藉此降低電線之電阻。
描述一種製造底部閘極半導體裝置的方法,其中形成氧化矽薄膜或氮氧化矽薄膜作為在閘極電極上的閘極絕緣薄膜、形成Al薄膜或Al合金薄膜作為第一導電薄膜以及形成添加n型或p型雜質的znO薄膜作為第二導電薄膜,並且接著,藉由第一蝕刻蝕刻第二導電薄膜,使其具有島狀的形狀,而藉由第二蝕刻蝕刻第一導電薄膜,使其具有島狀的形狀,以形成源極以及汲極電極,並形成znO半導體薄膜。
如第2A圖中所示,形成閘極電極。於基底1上之閘極電極的厚度可為10至200nm。可用實施例1中所示的材料形成基底1。在此使用玻璃基底。
藉由CVD或噴濺形成具有10至200nm的厚度之含有氧化矽(SiOx)、氧化氮(SiNx)、氧氮化矽(SiOxNy)(x>y)、氧化氮化矽(SiNxOy)(x>y)或類似者之絕緣薄膜2,以防止雜質或類似者從基底側擴散(第2B圖)。
可藉由使用高密度電漿處理基底1的表面而形成絕緣薄膜2。例如,可使用2.45GHz的微波產生高密度電漿,並且電子密度僅需要在從1×1011
至1×1013
/cm3
的範圍內,以及電子溫度為2eV或更小。此種高密度電漿具有活性種類之低動能,並且可形成具有較少缺陷的薄膜,其中該電漿比傳統的電漿處理導致較少破壞。
可在氮化環境中透過高密度電漿處理而將基底1的表面氮化,其中該氮化環境例如為含有氮與鈍氣之環境、含有氮、氧以及鈍氣之環境以及含有氨以及鈍氣之環境。於使用玻璃基底作為受到高密度電漿的氮化處理之基底1之情況中,氮化薄膜形成於之基底1的表面上時,可形成含有氮化矽為主要構件之絕緣薄膜2。可使用複數層來形成絕緣薄膜2,其中透過電漿CVD在氮化薄膜之上形成氧化矽薄膜或氮氧化矽薄膜。
此外,可類似地以高密度電漿在絕緣薄膜2的表面上氮化而形成氮化薄膜。
藉由以高密度電漿氮化之氮化薄膜可抑制雜質從基底1擴散。
可使用實施例1中所示的材料形成閘極電極3。於此,透過使用噴濺A1Nd目標並且處理成島狀形狀而形成鋁釹(AlNd)薄膜。使用光微影方法將薄膜處理成島狀形狀,並使用乾蝕刻或濕蝕刻。
在清理閘極電極3的表面以及基底1或絕緣薄膜2的表面之後,使用已知的CVD或噴濺將具有厚度10至200nm的閘極絕緣薄膜5形成於閘極電極3之上(第2A與2B圖)。可連續地執行表面清理步驟以及閘極絕緣薄膜5的形成步驟而不曝露至空氣。在使用Al薄膜作為閘極電極3的情況中,當在高溫下形成閘極絕緣薄膜5時,有時候會產生突起物。因此較佳以低溫,較佳為350℃或更低,形成薄膜。
可使用實施例1中所示的材料形成閘極絕緣薄膜5。在此,形成氧化矽薄膜。注意到在下列圖中省略絕緣薄膜2。
在閘極絕緣薄膜5上形成具有10至200nm的厚度之源極以及汲極電極之第一導電薄膜6。可使用實施例1中所示之材料形成第一導電薄膜6。在此,可使用AlNi(鋁鎳)薄膜或AlNd薄膜。可藉由噴濺AlNi目標或AlNd目標形成第一導電薄膜6。在形成閘極絕緣薄膜5之後,可連續地形成第一導電薄膜6而不暴露於空氣。
形成具有10至200nm的厚度之第二導電薄膜7於第一導電薄膜6之上(第2C圖)。可使用實施例1中所示之材料形成第二導電薄膜7。在此,使用添加Al或Ga之雜質的Zno(氧化鋅)。因此,可容易地在第二導電薄膜7以及於後形成之ZnO薄膜之間建立歐母接觸。可藉由噴濺形成第二導電薄膜7。例如,下列方法可用於添加Al或Ga:使用添加有1至10重量百分比的Al或Ga之ZnO目標噴濺;或在200℃至300℃噴濺具有Al或Ga片裝設於其上之ZnO目標。
在形成第一導電薄膜6之後,可連續地形成第二導電薄膜7而不暴露於空氣。因此,閘極絕緣薄膜5至第二導電薄膜7之形成可連續地執行而不暴露於空氣。
可在第一導電薄膜6以及第二導電薄膜7之間形成具有厚度為10至200nm的第三導電薄膜8(第2D圖)。有時第一導電薄膜6與第二導電薄膜7之間的接觸電阻會隨著製程中之熱處理溫度增加。然而,可藉由形成第三導電薄膜8來降低此接觸電阻。可藉由使用諸如Ti薄膜之金屬薄膜來形成第三導電薄膜8,該金屬薄膜係由噴濺或類似者所形成。
形成光阻遮罩9於第二導電薄膜7上,並且蝕刻第二導電薄膜7(第3A與3B圖)。於使用濕蝕刻的情況中,緩衝的氟酸(其中混合了氫氟酸(HF)以及氟化氨(NH4
F)),例如,使用具有HF:NH4
F(重量比)=l:100至1:10比例之溶液。
於使用乾蝕刻的情況中,可使用利用CH4
氣體之非等向性電漿蝕刻。
在第二導電薄膜7之下係形成有第一導電薄膜6。因此,第一導電薄膜6作為當蝕刻第二導電薄膜7之止蝕刻件。因此,可於蝕刻中形成源極與汲極電極而不會破壞閘極絕緣薄膜5。
當蝕刻第二導電薄膜7時可蝕刻第一導電薄膜6的一部分。然而,必須注意不全部蝕刻掉第一導電薄膜6,因為若完全蝕刻第一導電薄膜6會破壞閘極絕緣薄膜。
接著,藉由使用光阻遮罩9蝕刻第一導電薄膜6而形成源極電極10與汲極電極11(第3C圖)。於本發明中,使用由氫氧化四甲基銨(TMAH)代表之有機鹼性溶液蝕刻第一導電薄膜6,該有機鹼性溶液為光阻的顯影劑。
在使用AlNi薄膜作為第一導電薄膜6以及TMAH作為蝕刻溶液的情況中,在30℃蝕刻比例約為300nm/min。另一方面,不用TMAH蝕刻使用上述材料之第二導電薄膜7或閘極絕緣薄膜5。因此,可形成源極電極10與汲極電極11而不會破壞閘極絕緣薄膜5。此外,島狀的第二導電薄膜10b與11b的大小並未減少。於本發明中,可使用當形成光阻遮罩時使用的顯影劑來蝕刻第一導電薄膜6,而不使用特別的蝕刻溶液。因此,節省成本並增加效率。
在形成源極電極10與汲極電極11之後移除光阻遮罩9。
可在源極電極10、汲極電極11以及閘極絕緣薄膜5之上噴濺而形成具有20至200nm之厚度的ZnO薄膜作為半導體薄膜12(第3D圖)。例如,可透過在200至300℃使用具有在30至20之氧/氬的流速之ZnO目標來形成該薄膜。
藉由光微影方法蝕刻半導體薄膜12以形成島狀形狀的半導體薄膜13(第4A圖)。可使用利用緩衝的氟酸之濕蝕刻方法或利用CH4
氣體之乾蝕刻方法。
znO常用於半導體薄膜12以及第二導電薄膜10b與11b之中,並且難以達到足夠的蝕刻選擇性。然而,因為需要在與半導體薄膜12接觸的部分形成第二導電薄膜7,可蝕刻第二導電薄膜7之與半導體薄膜12沒有接觸到之部分,例如,電線部分。於上述蝕刻方法中,可蝕刻第二導電薄膜100與11b,但不蝕刻第一導電薄膜10a與11a。因此,第一導電薄膜10a與11a作為電線,並且確保與半導體裝置之電性連結。
形成具有厚度為50nm至1μm之絕緣薄膜14於半導體薄膜13上。含有矽作為主要構件的絕緣薄膜可形成為絕緣薄膜14。可將有機樹脂薄膜或類似者堆疊在含有矽的絕緣薄膜之上。絕緣薄膜14作為鈍化薄膜或平坦化薄膜。由於Al係包含於源極電極10以及汲極電極11之中,當在高溫下形成絕緣薄膜14時有時會產生突起物。因此,較佳在低溫形成,500℃或更低,較佳在350℃或更低。
可在絕緣薄膜14中形成接觸孔,並且若有需要可設置與閘極電極3、源極電極10以及汲極電極11接觸的導電薄膜。
根據本發明,可形成半導體裝置而不會破壞閘極絕緣薄膜。如AlNi薄膜之Al合金薄膜用作第一導電薄膜,藉此降低電線之電阻。
於此描述一種製造頂部閘極半導體裝置的方法,其中於氧化矽薄膜或氮氧化矽薄膜之上形成Al薄膜或Al合金薄膜作為第一導電薄膜,並且形成添加有n型或p型雜質的ZnO作為第二導電薄膜,並且接著,藉由第一蝕刻形成具有島狀形狀之第二導電薄膜,藉由第二蝕刻形成具有島狀形狀之第一導電薄膜以形成源極與汲極電極,形成ZnO半導體薄膜,形成閘極絕緣薄膜以及形成閘極電極。注意到當然在實施例1至3中描述的製造方法與材料適用於本實施例所用者。
如第5A圖中所示,於基底1上藉由CVD或噴濺形成具有厚度為10至200nm之氧化矽薄膜(SiOx)作為絕緣薄膜20。絕緣薄膜20防止雜質或類似者從基底1之側擴散。
藉由噴濺或蒸發於絕緣薄膜20上形成源極與汲極電極之具有厚度為10至200nm之第一導電薄膜21。諸如顯示於實施例1中之鋁鎳(AlNi)薄膜的Al合金薄膜可用作第一導電薄膜21。在形成絕緣薄膜20之後,可連續地形成第一導電薄膜21而不暴露於空氣。
藉由噴濺於第一導電薄膜21上形成具有厚度為10至200nm之第二導電薄膜22(第5A圖)。作為第二導電薄膜22,可使用添加硼(B)、鋁(Al)、鎵(Ga)、磷(P)或砷(As)之p型或n型雜質的氧化鋅(ZnO)。在形成第一導電薄膜21之後,可連續地形成第二導電薄膜22而不暴露於空氣。因此,可連續執行第一導電薄膜21與第二導電薄膜22之形成步驟而不暴露於空氣。
可藉由噴濺於第一導電薄膜21與第二導電薄膜22之間形成具有厚度為10至200nm之諸如Ti薄膜的金屬薄膜作為第三導電薄膜23,以降低第一導電薄膜21與第二導電薄膜22之間的接觸電阻(第5B圖)。
光阻遮罩24形成於第二導電薄膜22之上,並且蝕刻第二導電薄膜22(第5C圖)。可使用利用緩衝的氟酸之濕蝕刻或利用CH4
氣體之乾蝕刻作為蝕刻方法。
第一導電薄膜21係形成於第二導電薄膜22之下。因此,第一導電薄膜21作為當蝕刻第二導電薄膜22時之止蝕刻件。因此,可形成源極與汲極電極而不會透過蝕刻絕緣薄膜20而暴露出基底1。
當蝕刻第二導電薄膜22時,可蝕刻第一導電薄膜21的一部分。注意到若蝕刻第一導電薄膜21全部,則會蝕刻絕緣薄膜20並且暴露出基底1,其會造成包含在基底1中之雜質的擴散。
蝕刻第一導電薄膜以形成源極電極25以及汲極電極26(第5D圖)。使用利用TMAH作為光阻的顯影劑之濕蝕刻作為蝕刻方法。因此,可形成源極電極25以及汲極電極26而不蝕刻絕緣薄膜20。此外,島狀形狀的第二導電薄膜25b與26b的大小不會減少,因為ZnO薄膜沒有被TMAH蝕刻。可利用在形成光阻遮罩時使用的顯影劑執行蝕刻,而無須第一導電薄膜21之特別的蝕刻溶液,這因而降低成本並增加效率。
在形成源極電極25與汲極電極26之後移除光阻遮罩24。
可在源極電極25、汲極電極26以及絕緣薄膜20之上噴濺而形成具有20至200nm之厚度的ZnO薄膜作為半導體薄膜27(第6A圖)。
藉由光微影方法蝕刻半導體薄膜27以形成島狀形狀的半導體薄膜27。可使用利用緩衝的氟酸之濕蝕刻或利用CH4
氣體之乾蝕刻作為蝕刻方法。
ZnO常用於半導體薄膜27以及第二導電薄膜25b與25b之中,並且難以達到足夠的蝕刻選擇性。然而,可蝕刻第二導電薄膜之與半導體薄膜27沒有接觸到之部分,特別為電線部分,因為第二導電薄膜22可形成於源極與汲極電極部分中,如同實施例3。
藉由CVD或噴濺在半導體薄膜27之上形成具有厚度為10至200nm之閘極絕緣薄膜28(第6B圖)。半導體薄膜27可受到上述實施例中所示的高密度電漿以形成閘極絕緣薄膜。可在氮化環境中透過高密度電漿處理而將半導體薄膜27的表面氮化,其中該氮化環境例如為含有氮與鈍氣之環境、含有氮、氧以及鈍氣之環境以及含有氨以及鈍氣之環境。
可使用含有矽作為主要構件的絕緣薄膜來形成閘極絕緣薄膜28,例如,氧化矽薄膜、氮氧化矽薄膜、氮化矽薄膜以及氧化氮化矽薄膜。此外,它可為單層或多層的薄膜。
閘極電極29形成於閘極絕緣薄膜28之上(第6B圖)。可使用上述實施例中所示的材料來形成閘極電極29,並且可為單層或包含兩或更多層之多層薄膜。可利用已知的CVD噴濺、蒸發或類似者作為薄膜形成之方法。可使用乾蝕刻或濕蝕刻方法以光微影方法來將閘極電極29處理成島狀形狀。
在閘極電極29與閘極絕緣薄膜28之上藉由CVD或噴濺形成具有厚度為50nm至1μm之絕緣薄膜30(第6C圖)。可使用含有矽之絕緣薄膜形成絕緣薄膜30。可將有機樹脂薄膜或類似者堆疊在含有矽的絕緣薄膜之上。絕緣薄膜30作為鈍化薄膜或平坦化薄膜。由於Al係包含於源極電極25以及汲極電極26之中,當在高溫下形成閘極絕緣薄膜28、閘極電極29以及絕緣薄膜30時有時會產生突起物。因此,較佳在低溫形成,500℃或更低,較佳在350℃或更低。
如上述,本發明防止雜質由於基底1之暴露而擴散。如AlNi薄膜之Al合金薄膜用作為第一導電薄膜,藉此降低電線之電阻。
在此,參照第8A、8B、9A以及9B說明使用實施例1與3中所示的底部閘極半導體裝置製造液晶顯示裝置之方法。注意到當然亦可應用實施例2與4中所示的頂部閘極半導體裝置。第8A以及9A圖顯示沿著第8B圖中之線X-Y之剖面圖。
於玻璃基底或塑膠基底1之上形成閘極電線40以及輔助電容器電線41。藉由噴濺,然後,藉由光微影方法與蝕刻形成形成AlNd薄膜。
藉由CVD或噴濺使用氧化矽或氮氧化矽形成閘極絕緣薄膜42。
藉由在閘極絕緣薄膜42之上噴濺形成AlNi薄膜作為第一導電薄膜。第一導電薄膜稍後形成源極電極45a、汲極電極46a以及源極電線47。
在第一導電薄膜上透過噴濺形成添加有Al之氧化鋅(ZnO)薄膜作為第二導電薄膜。第二導電薄膜形成源極電極45b、汲極電極46b以及源極電線47。
光阻遮罩形成在第二導電薄膜之上將會成為源極電極部分、汲極電極部分以及源極電線部分的區域之中(未顯示於該圖中)。接著,蝕刻第二導電薄膜。在此,使用緩衝的氟酸以及HF:NH4F=1:100(重量比例)之溶液執行蝕刻。
接著,使用TMAH溶液蝕刻第一導電薄膜以形成源極電極45a、汲極電極46a以及源極電線47。之後,移除光阻遮罩。接著可形成源極電極45、汲極電極46以及源極電線47而不會破壞閘極絕緣薄膜42。此外,因為ZnO沒有被TMAH蝕刻,島狀形狀之第二導電薄膜的大小不會減少。此外,由於使用AlNi薄膜作為第一導電薄膜,可以降低源極電線之電阻。
接著,形成半導體薄膜48。藉由噴濺形成ZnO薄膜,並且接著,藉由光微影方法與蝕刻自該ZnO薄膜形成半導體薄膜48。使用利用緩衝的氟酸之濕蝕刻作為蝕刻。沒有與半導體薄膜48接觸之第二導電薄膜的部分可在此部分移除,因為第一導電薄膜形成於將成為電線的部分中。
藉由噴濺、塗覆或類似者在半導體薄膜48之上形成絕緣薄膜49。可使用由具有含有矽、有機樹脂薄膜或類似者的多層薄膜來形成絕緣薄膜49。絕緣薄膜49可為使表面之不平坦變得平坦之薄膜。
使用光微影方法以及蝕刻方法在絕緣薄膜49中形成至汲極電極46的接觸孔以及輔助電容器之接觸孔。
藉由噴濺形成透明導電薄膜,接著使用光微影方法與蝕刻形成畫素電極50。例如,可使用氧化銦錫(ITO)、含氧化矽之氧化銦錫(ITSO)或氧化銦鋅(IZO)。
在反射液晶顯示裝置的情況中,形成如銀(Ag)、金(Au)、銅(Cu)、鎢(W)、鋁(Al)之光反射金屬材料,而非透明電極。
畫素電極50與輔助電容器電線41重疊的部分形成輔助電容器100,其由畫素電極50、閘極絕緣薄膜42以及輔助電容器電線41所形成(第8A與8B圖)。
彎曲部分或其中寬度改變之部分的角落可在電線或電極中平滑化或圓滑化。可使用利用光遮罩的圖案製造之光遮罩圖案實現去角的(chamfered)角落之形狀。這具有下列的優點。當執行使用電漿的乾蝕刻時,藉由將突出的部分去角化而得以抑制因為不正常的放電而造成的細微粒子的產生。即使產生的細微粒子,清理時可防止細微粒子累積在角落,並且藉由將凹部去角化而得以沖走這些細微的粒子。因此,可解決製造程序中之細微粒子或灰塵的問題並增進產率。
形成對準薄膜51以覆蓋畫素電極50。藉由液滴釋放方法、印刷或類似者形成對準薄膜51。在形成對準薄膜之後,進行磨擦。
藉由使用彩色層以及遮光層(黑色矩陣)形成濾色器55,並且在相對的基底56之上形成保護絕緣薄膜54。形成透明電極57,並且於保護絕緣薄膜54上形成對準薄膜53(第9A圖)。對準薄膜係受到磨擦程序。
接著,藉由液滴釋放方法形成密封劑的封閉圖案75(第9B圖)。由密封劑所圍繞的區域以液晶成分52填補(第9A圖)。
在將液晶成分52滴入密封圖案75中,相對的基底56以及其中形成有半導體裝置之基底1係互相連接在一起。當填補液晶成分52時,可採用下列的替代方案:在基板1上提供具有開口部之密封圖案;相對的基底56以及基底1互相連接;接著,使用毛細管作用將液晶注入。
作為液晶成分52之對準模式,可使用TN模式、FLC模式、IPS模式或類似者,TN模式中液晶分子的對準係從光入射側至光發射側扭轉90°。注意到電極圖案與第8B圖中所示者不同,並且在IPS模式的情況中為蜂巢狀。
將起偏板連接至相對基底56以及其中形成有半導體裝置之基底1之兩者。此外,若有需要可連接光學薄膜。
可藉由散佈球形間隔體或形成由樹脂形成的柱狀間隔體或藉由混合填補物於密封劑中,維持相對的基底56以及其上形成有半導體裝置之基底1之間的距離。上述的柱狀間隔體係由含有丙烯醛基、聚醯亞胺、聚醯亞胺醯胺或環氧的至少一者作為主要構件之有機樹脂材料,或具有氧化矽、氮化矽以及含氮的氧化矽之一的無機材料,或上述之多層薄膜形成。
接著,使用已知的技術將軟性印刷電路(FPC)連接至基底1,並且在這兩者之間插設有非等向性導電層。
於基底上形成週邊驅動器電路。一平面的範例圖顯示於第9B圖中。
於基底61上形成由玻璃或類似者形成的閘極電線驅動器電路62、源極電線驅動器電路63以及主動矩陣部64。位移暫存器62a以及緩衝器62b構成閘極電線驅動器電路62。至少一位移暫存器63a、緩衝器63b以及類比切換器69構成源極電線驅動器電路63,該類比切換器取樣透過視訊線68傳送之視訊信號。從閘極電線驅動器電路62延伸之複數條閘極電線72於主動矩陣部64中互相平行地配置。從源極電線驅動器電路63延伸之複數條源極電線71係與閘極電線72呈直角地配置。此外,輔助電容器電線73與閘極電線72平行配置。此外,半導體裝置65、液晶部66以及輔助電容器67設置於由閘極電線72、源極電線71以及輔助電容器電線73所圍繞的區域中。
提供與半導體裝置65相同方式製造的半導體裝置給閘極電線驅動器電路62、源極電線驅動器電路63以及類比切換器69,以具有類似的結構。
於半導體裝置65中,閘極電極連接至閘極電線72,以及源極電極連接至源極電線71。藉由引進將密封在連接至半導體裝置65的汲極電極之畫素電極與相對基底上之相對電極之間的液晶,形成液晶部66。輔助電容器電線73連接至具有與該相對電極相同電位的電極。
於上述的液晶顯示裝置中,並未蝕刻閘極絕緣薄膜,並且特性不會變得不穩定,因此可實現高可靠性。於使用頂部閘極半導體裝置的情況中,並未蝕刻藉由使用氧化矽薄膜或氮氧化矽薄膜而形成的玻璃基底或底部薄膜,因此例如鈉之雜質不會自基底擴散至半導體薄膜中,並且不會使特性惡化,因此可實現高可靠性。
使用Al作為源極電極與汲極電極的一部分,藉此降低電線之電阻。
在此,參照第10A、10B、11A以及11B說明使用實施例1與3中所示的底部閘極半導體裝置來製造發光裝置的方法。注意到當然亦可應用實施例2與4之半導體裝置。
根據上述實施例的說明製造半導體裝置,並且執行至第10A圖中所示的階段的形成。注意到與上述實施例相同的部件係以相同的參考符號表示。
於EL顯示裝置中,畫素電極50作為陽極或陰極。作為畫素電極50之材料,可使用下列者:諸如鋁(Al)、銀(Ag)、金(Au)、鉑(Pt)、鎳(Ni)、鎢(W)、(Cr)、鉬(Mo)、鐵(Fe)、鈷(Co)、銅(Cu)、鈀(Pd)、鋰(Li)、銫(Cs)、鎂(Mg)、鈣(Ca)、鍶(Sr)或鈦(Ti)之導電金屬;諸如鋁矽(Al-Si)、鋁-鈦(Al-Ti)或鋁-矽-銅(Al-Si-Cu)之合金;諸如ITO、含矽之ITO或IZO之金屬化合物。
擷取自EL層發射之光線的電極僅需藉由使用發光導電薄膜來形成,並且可使用諸如Al或Ag之非常薄的金屬薄膜或者諸如ITO、含矽之ITO或IZO之金屬化合物。
當從與畫素電極50相對之電極擷取發射之光線時,可使用高度反射性材料(Al、Ag或類似者)作為畫素電極50。於此實施例中,ITSO,其代表含矽之ITO,用為畫素電極50(第10A圖)。
接著,形成由有機材料或無機材料形成的絕緣薄膜,以覆蓋絕緣薄膜49與畫素電極50。接著,處理該絕緣薄膜以部分暴露畫素電極50,藉此形成分隔牆81。作為分隔牆81,較佳為感光性有機材料(如丙烯醛基或聚醯亞胺)。替代地,亦可使用非感光有機材料或無機材料。此外,藉由將分隔牆81上色成黑色可將分隔牆81用為黑色矩陣,該上色方式可為使用擴散劑將諸如鈦黑色之黑色素或染料或氮化碳擴散至分隔牆81的材料內。較佳分隔牆81具有錐形,並且朝畫素電極的那些末端表面81a具有持續改變的曲率。
接下來,形成包含發光物質的層82,並且形成覆蓋包含發光物質的層82之相對電極83。之後,可製造具有介於畫素電極50以及相對電極83之間的包含發光物質的層82之發光元件,並且可施加電壓於相對電極83以及畫素電極50之間而獲得發光。
作為形成相對電極83之電極材料,可使用與畫素電極所用之類似的材料。於此實施例中,使用鋁作為第二電極。
藉由蒸發、噴墨、旋塗、浸泡覆佈、成卷式方法(roll-to-roll)、噴濺或類似者形成包含發光物質的層82。
在有機電致發光顯示裝置的情況中,包含發光物質的層82可為有分別具有電洞傳輸、電洞注入、電子傳輸、電子注入或發光之功能的層之多層薄膜,或為有發光層之單層。作為包含發光物質的層,可使用單層或多層的有機化合物。
電洞注入層設置於陽極以及電洞傳輸層之間。作為電洞注入層,可使用有機化合物與金屬氧化物之混合的層。這防止因為形成在畫素電極50的表面上之不平坦或流在電極表面上的異物而造成畫素電極50以及相對電極83之間的短路。混合層之厚度較佳為60nm或更多,更佳為120nm或更多。由於薄膜厚度的增加不會造成驅動電壓的增加,可選擇足以應付不平坦或異物的影響之薄膜的厚度。因此,不會產生黑點,並且不會增加由本發明製造之發光裝置中之驅動電壓或耗電量。
過渡金屬之氧化物或氮化物較佳為金屬氧化物,具體而言,氧化鋯、氧化鉿、氧化釩、氧化鈮、氧化鉭、氧化鉻、氧化鉬、氧化鎢、氧化鈦、氧化鎂以及氧化錸。
作為有機化合物,可使用下列者:具有芳氨基族之有機材料,如4,4’-bis[N-(1-napthyl)-N-phenylamino]biphenyl(NPB)、4,4’-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl(TPD)、4,4’,4”-tris(N,N-diphenylamino)triphenylamine(TDATA)、4,4’,4”-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine(MTDATA)、4,4’-bis{N-[4-(N,N-di-m-tolylamino)phenyl]-N-phenlamino}biphenyl(DNTPD)、1,3,5-tris[N,N-di(m-tolyl)amino]benzene(m-MTDAB)以及4,4’,4”-tris(N-carbazolyl)triphenlamine(TCTA);酞花青(phthalocyanine;H2
Pc);銅酞花青(CuPc);釩氧酞花青(vanadyl phthalocyanine;VOPc)或類似者。
電洞傳輸層設置於陽極與發光層之間,或當有電洞注入層時於電洞注入層與發光層之間。藉由使用具有傳輸電洞之優異性能的層來形成電洞傳輸層,例如,藉由使用芳香胺之化合物(亦即具有苯環-氮鍵),如NPT、TPD、TDATA、MTDATA以及BSPB。在此提及之物質主要具有1×10-6
至10cm2
/Vs之電洞遷移率。注意到可使用具有比電子更高之電洞傳輸性質之物質作為材料。注意到可不僅由單層形成電洞傳輸層,亦可由多層薄膜所形成,該多層薄膜有從上述物質堆疊而形成之兩個或更多層。
發光層設置於陽極與陰極之間,或當有電洞傳輸層與電子傳輸層時在電洞傳輸層與電子傳輸層之間。不特別限制發光層,然而,作為發光層之層大槪會有兩種模式。一種為主-客型的層,其包含在由具有比發光物質(摻雜材料)之能帶隙更大的能帶隙之材料(主材料)所形成的層中之分散的發光物質,該發光物質變成發光中心,而另一種為其中發光層僅由發光物質製成的層。作為發光中心之發光物質,可使用下列者:4-dicyanomethylene-2-methyl-6-(1,1,7,7-tetramethyljulolidyl-9-enyl)-4H-pyran(DCJT)、4-dicyanomethylene-2-t-butyl-6-(1,1,7,7-tetramethyljulolidine-9-enyl)-4H-pyran(DCJT)、periflanthene、2,5-dicyano-1,4-bis(10-methoxy-1,1,7,7-tetramethyljulolidine-9-enyl)benzene;N,N’-dimethylquinacridone(DMQd)、coumarin 6、coumarin 545T、tris(8-quinolinolato)aluminium(Alq3
)、9,9’-bianthryl、9,10-diphenylanthracene(DPA)、9,10-bis(2-naphthyl)anthracene(DNA)、2,5,8,11-tetra-t-butylperylene(TBP)、PtOEP、Ir(ppy)3
、Btp2
Ir(acac)、FIrpic或類似者。在形成其中擴散發光物質之層的情況中,作為主材料之基底材料,可使用下列者:如9,10-di(2-naphtyl)-2-tert-butylanthracene(t-BuDNA)之蔥(anthracene)衍生物、4,4’-bis(N-carbazolyl)biphenyl(CBP)之咔唑(carbazole)衍生物或諸如tris(8-quinolinolato)aluminium(Alq3
)、tris(4-methyl-8-quinolinolato)aluminium(Almq3
)、bis(10-hydroxybenzo[h]-quinolinato)beryllium(BeBq2
)、bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum(BAlq)、bis[2-(2-hydroxyphenyl)pyridinato]zinc(Znpp2
)或bis[2-(2-hydroxyphenyl)benzoxazolate]zinc(ZnBOX)之金屬複合物。作為構成僅具有發光物質之發光層的材料,可使用tris(8-quinolinolato)aluminium(Alq3
)、9,10-bis(2-naphtyl)anthracene(DNA)、bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum(BAlq)或類似者。
電子傳輸層設置於發光層與陰極之間,或當有電洞注入層時於發光層與電洞注入層之間。電子傳輸層為具有優異之電子傳輸性能的層,並且例如,使用金屬複合物形成的層,該金屬複合物具有喹啉(quinoline)骨架或苯並喹啉(benzoquinoline)骨架,如tris(8-quinolinolato)aluminium(Alq3
)、tris(4-methyl-8-quinolinolato)aluminium(Almq3
)、bis(10-hydroxybenzo[h]-quinolinato)beryllium(BeBq2
)以及bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum(BAlq)。此外,可使用具有唑(oxazole)配位基或酛唑(thiazole)之配位基金屬複合物,如bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc(Zn(BOX)2
)、bis[2-(2-hydroxyphenyl)-benzthiazolato]zinc(Zn(BTZ)2
)或類似者。除了金屬複合物之外,可使用2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole(PBD)、1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazole-2-yl]benzene(OXD-7)、3-(4-tert-butylphenyl)-4-phenyl-5-(4-biphenylyl)-1,2,4-triazole(TAZ)、3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole)(p-EtTAZ)、bathophenanthroline(BPhen)、bathocuproine(BCP)或類似者。在此提及之這些物質主要具有1×10-6
至10cm2
/Vs的電子遷移率。注意到可使用其他物質作為電子傳輸層,只要其具有比電洞傳輸特性更高之電子傳輸特性。此外,可不僅由單層形成電子傳輸層,亦可由多層薄膜所形成,該多層薄膜有從上述物質堆疊而形成之兩個或更多層。
電子注入層設置於陰極與電子傳輸層之間。作為電子注入層,可使用鹼金屬化合物或鹼土金屬,如氟化鋰(LiF)、氟化銫(CsF)或氟化鈣(CaF2
)。除此之外,可使用由使用含有鹼金屬或鹼土金屬之電子傳輸層所形成的層,例如含鎂(Mg)之Alq3
或類似者。
在無機電致發光裝置的情況中,可使用其中螢光物質粒子擴散於包含發光物質之層82用之擴散劑中者。
可使用其中ZnS中的銅(Cu)與諸如氯(Cl)、碘(I)或鋁(Al)一起添加之施體的螢光物質。
作為擴散劑,可使用下列者:具有相對高介電質常數之聚合物,如以氰乙基纖維素為基礎之樹脂、以聚乙烯為基礎之樹脂、以聚丙烯為基礎之樹脂、以聚苯乙烯為基礎之樹脂、矽膠樹脂、環氧樹脂、氯化氯乙烯樹脂或類似者。可藉由混合樹脂以及諸如鈦酸鋇(BaTiO3
)或鈦酸鍶(SrTiO3
)之具有高介電質常數之微小粒子來調整介電質常數。作為擴散機制,可使用超音波擴散機或類似者。
介電質層設置於包含發光物質之層82與電極之一之間。作為介電質層,可利用具有高介電質崩潰電壓之高度介電與絕緣之材料。可選自例如TiO2
、BaTiO3
、SrTiO3
、PbTiO3
、KaNbO3
、PbNbO3
、Ta2
O3
、BaTa2
O6
、LiTaO3
、Y2
O3
、Al2
O3
、zrO2
、AlON、ZnS或類似者之金屬氧化物或氮化物之一。
在無機電致發光顯示裝置的情況中,可利用其中發光層介於絕緣層之間的雙絕緣結構。可藉由使用諸如錳(Mn)或含有稀土元素之硫化鋅(ZnO)的II-VI化合物形成發光層,並且可藉由使用諸如Si3
N4
、SiO2
、Al2
O3
或TiO2
形成絕緣層。
藉由電漿CVD於相對電極83上形成含氮之氧化矽薄膜作為鈍化層(未圖示)。於使用含氮之氧化矽薄膜的情況中,使用下列者:藉由電漿CVD使用SiH4
、N2
O以及NH3
形成之氮氧化矽、使用SiH4
以及N2
O形成之氮氧化矽或使用其中以Ar稀釋SiH4
與N2
O之氣體形成的氮氧化矽。
可使用從SiH4
、N2
O以及NH3
製造出來的氫化氮化氧化矽作為鈍化薄膜。注意到鈍化薄膜不限於上述之物質。亦可使用另一含矽之絕緣薄膜作為主構件。此外,可使用多層薄膜結構亦或單層結構。另外,可使用氮化碳薄膜與氮化矽薄膜之多層薄膜或苯乙烯聚合物之多層薄膜。可形成氮化矽薄膜或類鑽碳薄膜。
接著,密封顯示部以保護發光元件不受到會惡化品質之材料(如水)的影響。在使用相對基底作為密封之情況中,藉由絕緣密封劑連接相對基底,以暴露出外部連結部。可用諸如乾的氮之鈍氣填補相對基底與元件基底之間的空間,或藉由以密封劑塗敷整個畫素部而連接相對基底。較佳用紫外線硬化樹脂或類似者作為密封劑。可將用於維持基底間之固定間隔的乾燥劑或粒子混進密封劑中。然後,藉由連接軟性線路板至外部連結部而完成發光裝置。
如上述般製造的發光裝置的結構之一範例顯示於第11A與11B圖中。注意到具有相同功能之部件有時會以相同的參考符號表示,即使它們有不同形狀,並且時常省略解釋。
第11A圖顯示一結構,其中使用光傳送導電薄膜形成畫素電極50,並且於包含發光物質之層82中產生的光係朝基底1發射。此外,參考符號86代表相對基底。在形成發光元件之後,使用密封劑或類似者將此相對基底固接至基底1。以具有光傳送特性之樹脂85或類似者填補相對基底86與元件之間的空隙,以密封發光元件。因此,可防止濕氣或類似者惡化發光元件。較佳地,樹脂85具有吸濕特性。更佳者,在樹脂85中擴散具有高光傳送特性之乾燥劑84以防止濕氣的不利影響。
第11B圖顯示一結構,其中皆使用具有高光傳送特性之導電薄膜形成畫素電極50以及相對基底86。因此,光可朝基底1以及相對基底86兩者發射,如虛線的箭頭所示。於此結構中,藉由在基底1以及相對基底86之外設置起偏板88,可防止遮幕呈現透明,藉此增進能見度。保護薄膜87較佳設置在起偏板88之外。
具有顯示功能的本發明之發光裝置可利用類比視訊信號或數位視訊信號。若使用數位視訊信號,視訊信號可使用電壓或電流。
當發光元件發光時,欲輸入至畫素之視訊信號可具有固定電壓或固定電流。當視訊信號具有固定電壓時,固定電壓施加至發光元件或固定電流流經發光元件。
並且,當視訊信號具有固定電流時,固定電壓施加至發光元件或固定電流流經發光元件。施加固定電壓至發光元件的驅動方法稱為固定電壓驅動。同時,固定電流流經發光元件之驅動方法稱為固定電流驅動。於固定電流驅動中,無論發光元件的電阻如何改變,流動固定電流。根據本發明之發光顯示裝置以及其之驅動方法可使用上述方法之任一者。
於發光裝置中,並未蝕刻閘極絕緣薄膜,並且發光元件的特性不會不穩定,因此其可靠度很高。於使用頂部閘極半導體裝置之情況中,由於藉由使用未被蝕刻之氧化矽薄膜或氮氧化矽薄膜形成之玻璃基底或基部薄膜,會惡化特性之雜質不會從基底擴散至半導體薄膜,進而可獲得高可靠度。
使用Al作為源極電極與汲極電極的一部分,藉此降低電線之電阻。
包含於面板與模組中之畫素電路以及保護電路以及其之操作顯示於第12A至12F以及13圖或類似者中。第10A以及10B以及11A以及11B圖各顯示半導體裝置之驅動TFT 1403之剖面圖。可與驅動TFT 1403同時製造切換TFT 1401、電流控制TFT 1404以及抹除器TFT 1406,並且可與驅動TFT 1403具有相同的結構。
第12A圖中所示的畫素包含配置於行方向中之信號線1410以及電源來源線1411與1412,以及配置於列方向中之掃描線1414。該畫素進一步包含切換TFT 1401、驅動TFT 1403、電流控制TFT 1404、輔助電容器1402以及發光元件1405。
顯示於第12C圖中之畫素具有與第12A圖中者相同的結構,除了驅動TFT 1403之閘極電極連接至設置於列方向中的電源來源線1412。換言之,顯示於第12A與12C圖中之畫素具有相同的等效電路圖。然而,在配置於行方向中之電源來源線1412的情況中(第12A圖)所形成的電源來源線係使用在一層中之導電層形成,該層與在配置列方向中之電源來源線1412的情況中(第12C圖)於其中使用導電層形成電源來源線之層不同。在此,注意到與驅動TFT 1403的閘極電極連接之電線,並且該結構獨立顯示於第12A與12C圖中,以顯示用不同層製造這些電線
作為顯示於第12A與12C圖中之特徵,驅動TFT 1403以及電流控制TFT 1404在畫素中串聯連接,並且較佳設定驅動TFT 1403之通道長度L(1403)以及通道寬度W(1403),以及電流控制TFT 1404之通道長度L(1404)以及通道寬度W(1404),以滿足L(1403)/W(1403):L(1404)/W(1404)=5至6000:1。
驅動TFT 1403在飽和區域中操作並用來控制流入發光元件1405之電流的電流值。電流控制TFT 1404在線性區域中操作並用來控制供應至發光元件1405之電流。這兩個TFT皆較佳在製程中具有相同的導電類型,並且於此實施例中,這些TFT為n通道類型之TFT。驅動TFT 1403可為增強模式TFT或空乏模式TFT。由於電流控制TFT 1404在具有上述結構的發光裝置中之線性區域中操作,電流控制TFT 1404之Vgs的微小變動不會影響發光元件1405的電流值。亦即,可由在飽和區域中操作之驅動TFT 1403判斷發光元件1405之電流值。藉由上述結構,可以補救因TFT之變化特性造成之發光元件的亮度之變化,藉此提供增進的影像品質之發光裝置。
於顯示在第12A至12D圖中的各畫素中,切換TFT 1402控制到畫素之視訊信號的輸入,並且當切換TFT 1401啟通時,視訊信號輸入至畫素中。接著,視訊信號的電壓保留在輔助電容器1402中。雖然第12A與12C圖顯示有設置輔助電容器,本發明不限於此。當閘極電容與類似者可作為保留視訊信號之電容器時,並不一定要設置輔助電容器1402。
顯示於第12B圖中之畫素具有與第12A圖中者相同的畫素結構,除了添加TFT 1406以及掃描線1415。依照同樣的方式,第12D圖中所示的畫素具有與第12C圖中者相同的畫素結構,除了添加TFT 1406以及掃描線1415。
TFT 1406之啟通與關閉由額外添加的掃描線1415所控制。當TFT 1406啟通時,會使輔助電容器1402中保留的電荷放電,藉此關閉電流控制TFT 1404。換言之,藉由提供TFT 1406,可強迫產生電流不會流入發光元件1405的狀態。因此,TFT 1406可稱為抹除器TFT。故,於第12B與12D圖中所示的結構中,可在信號寫入所有的畫素之前的寫入週期的開始的同時或隨後馬上開始發光週期;因此可增加工作比。
於第12E圖中顯示的畫素中,信號線1410以及電源來源線1411配置於行方向中,以及掃描線1414配置於列方向中。另外,畫素包含切換TFT 1401、驅動TFT 1403、輔助電容器1402以及發光元件1405。於第12F圖中顯示的畫素具有與第12E圖相同的畫素結構,除了添加TFT 1406以及掃描線1415。於第12F圖中所示的結構中,亦可藉由設置TFT 1406而增加工作比。
當畫素密度增加時,可在低電壓驅動此種主動矩陣發光裝置,因為設置TFT在個別的畫素中。因此,主動矩陣發光裝置可視為有利者。
雖然此實施例描述其中個別的TFT設置於個別的畫素中之主動矩陣發光裝置,亦可形成被動矩陣發光裝置。因為在被動矩陣發光裝置中沒有於個別的畫素中設置TFT,可獲得高孔徑比。在其中光線發射至光發射堆疊的兩側之發光裝置的情況中,會增加被動矩陣發光裝置之透射率。
因此,使用第12E圖中所示之等效電路描述設置二極體作為掃描線與信號線上之保護電路的情形。
於第13圖中,切換TFT 1401、驅動TFT 1403、輔助電容器1402以及發光元件1405係設置於畫素區域1500中。二極體1561與1562設置於信號線1410上。依照與切換TFT 1401以及驅動TFT 1403類似的方式,根據上述的實施例製造二極體1561與1562,並且具有閘極電極、半導體層、源極電極、汲極電極以及類似者。藉由將閘極電極與汲極電極或源極電極連接而將二極體1561與1562操作成二極體。
藉由使用與閘極電極相同的層來形成連接至二極體1561與1562之共同電位線1554與1555。因此,為了將共同電位線1554與1555連接至二極體的源極電極或汲極電極,需要在閘極絕緣層中形成接觸孔。
設置在掃描線1414上之二極體1563與1564具有類似的結構。此外,共同電位線1565與1566具有類似的結構。
按照此方式,根據本發明可同時在輸入級形成保護二極體。另外,保護二極體之位置並不限於此,並且它們可設置在驅動器電路與畫素之間。
在使用顯示於第12E圖中之等效電路的情形中之畫素部的上視圖係描述於第14A圖中。此外,與第12E圖中之相同的等效電路顯示於第14B圖中。顯示於第10A、10B、11A以及11B圖中之各半導體裝置對應至各驅動TFT 1403。第10A、10B、11A以及11B圖顯示沿著第14A與14B圖中之線X-Y取得之剖面圖。使用第一導電薄膜形成電源來源線1411、信號線1410以及切換TFT 1401之源極電極與汲極電極,以及使用第二導電薄膜形成驅動TFT 1403之源極電極與汲極電極。
用與驅動TFT 1403相同方式製造切換TFT 1401。切換TFT 1401之汲極電極以及驅動TFT 1403的閘極電極40經由形成在與閘極絕緣薄膜42相同的層中之絕緣薄膜中的接觸孔互相電性連接。
藉由使用驅動TFT 1403之閘極電極延伸的部分、電源來源線1411以及在與閘極絕緣薄膜42相同的層中的絕緣薄膜而形成輔助電容器1402。
發光區域1420係形成於分隔牆81的開口部之中。雖未圖示,分隔牆81形成在發光區域1420的附近。可使發光區域1420的角落變圓滑。藉由使分隔牆81的開口部之角落部變圓滑,可使發光區域1420的角落變圓滑。當執行使用電漿之乾蝕刻來處理分隔牆81時,可藉由將角落部變圓滑而抑制因不正常的放電而導致之微小粒子的產生。
此實施例可恰當地結合上述實施例的適當結構。
作為具有安裝有上述實施例中例示性顯示之模組的根據本發明之半導體裝置的電子裝置,可提出諸如錄影機或數位相機之相機、護目鏡式的顯示器(安裝於頭部之顯示器)、導航系統、音頻再生裝置(如汽車音響構件)、電腦、遊戲機、可攜式資訊終端機(如行動電腦、行動電話、行動遊戲機、電子書或類似者)、備有紀錄媒體之影像再生裝置(特別為能夠再生如多功能數位碟片(DVD)的紀錄媒體之內容的裝置,並且其具有顯示儲存於其中之影像的顯示器)以及類似者。這些電子用品之特定的範例係顯示於第15A至15E圖以及第16圖中。
第15A圖顯示電視接收器或個人電腦之監視器,或類似者,其包含殼體3001、顯示區域3003、揚聲器3004以及類似者。主動矩陣顯示裝置係設置在顯示區域3003之中。顯示區域3003的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之電視。
第15B圖顯示行動電話,其包含主體3101、殼體3102、顯示區域3103、音頻輸入部3104、音頻輸出部3105、操作鍵3106、天線3108以及類似者。主動矩陣顯示裝置係設置在顯示區域3103之中。顯示區域3103的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之行動電話。
第15C圖顯示電腦,其包含主體3201、殼體3202、顯示區域3203、鍵盤3204、外部連結部3205、指示滑鼠3206以及類似者。主動矩陣顯示裝置係設置在顯示區域3203之中。顯示區域3203的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之電腦。
第15D圖顯示行動電腦,其包含主體3301、顯示區域3302、開關3303、操作鍵3304、紅外線埠3305以及類似者。主動矩陣顯示裝置係設置在顯示區域3302之中。顯示區域3302的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之行動電腦。
第15E圖顯示行動遊戲機,其包含殼體3401、顯示區域3402、揚聲器3403、操作鍵3404、紀錄媒體插入部3405以及類似者。主動矩陣顯示裝置係設置在顯示區域3402之中。顯示區域3402的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之行動遊戲機。
第16圖顯示軟性顯示器,其包含主體3110、畫素區域3111、驅動器IC 3112、接收裝置3113、薄膜電池3114以及類似者。接收裝置可接收來自上述行動手機之紅外線通訊埠3107的信號。主動矩陣顯示裝置係設置在畫素區域3111之中。畫素區域3111的各畫素包含根據本發明製造之半導體裝置。藉由與此結構一起使用本發明的半導體裝置,可獲得較少特性惡化之軟性顯示器。
如前述,本發明之應用範圍極為廣泛,並且本發明可應用至所有領域中的電子裝置。
本申請書係根據於2005年11月15日在日本專利局中申請之日本專利申請案2005-329806號,其全部內容以參考方式包含於此。
1...基底
2...絕緣薄膜
3...閘極電極
5...閘極絕緣薄膜
6...第一導電薄膜
7...第二導電薄膜
8...第三導電薄膜
9...光阻遮罩
10...源極電極
10a...源極電極,第一導電薄膜
10b...源極電極,第二導電薄膜
11...汲極電極
11a...汲極電極,第一導電薄膜
11b...汲極電極,第二導電薄膜
12...半導體薄膜
13...島狀形狀之半導體薄膜
14...絕緣薄膜
20...絕緣薄膜
21...第一導電薄膜
22...第二導電薄膜
23...第三導電薄膜
24...光阻遮罩
25...源極電極
25a...源極電極,第一導電薄膜
25b...源極電極,第二導電薄膜
26...汲極電極
26a...汲極電極,第一導電薄膜
26b...汲極電極,第二導電薄膜
27...半導體薄膜
28...閘極絕緣薄膜
29...閘極電極
30...絕緣薄膜
40...閘極電線,閘極電線
41...輔助電容器電線
42...閘極絕緣薄膜
45a、45b...源極電極
46a、46b...汲極電極
47...源極電線
48...半導體薄膜
49...絕緣薄膜
50...畫素電極
51...對準電線
52...液晶成分
53...對準薄膜
54...保護絕緣薄膜
55...濾色器
56...相對基底
61...基底
62...閘極電線驅動器電路
62a、63a...位移暫存器
62b、63b...緩衝器
63...源極電線驅動器電路
64...主動矩陣部
65...半導體裝置
66...液晶部
67...輔助電容器
68...視訊線
69...類比切換器
71...源極電線
72...閘極電線
73...輔助電容器電線
75...密封劑
81...分隔牆
81a...末端表面
82...包含發光物質之層
83...相對電極
84...乾燥劑
85...樹脂
86...相對基底
87...保護薄膜
88...起偏板
100...輔助電容器
1000...基底
1001...源極電極
1002...汲極電極
1003...半導體薄膜
1004...閘極絕緣層
1005...閘極電極
1006...底部薄膜
1401...切換TFT
1402...輔助電容器
1403...驅動TFT
1404...電流控制TFT
1405...發光元件
1406...TFT
1410...信號線
1411、1412...電源來源線
1414、1415...掃描線
1420...發光區域
1500...畫素部
1561、1562、1563、1564...二極體
1554、1555、1565、1566...共同電位線
3001...殼體
3003...顯示區域
3004...揚聲器
3101...主體
3102...殼體
3103...顯示區域
3104...音頻輸入部
3105...音頻輸出部
3106...操作鍵
3107...紅外線通訊埠
3108...天線
3110...主體
3111...畫素部
3112...驅動器IC
3113...接收裝置
3114...薄膜電池
3201...主體
3202...殼體
3203...顯示區域
3204...鍵盤
3205...外部連結部
3206...指示滑鼠
3301...主體
3302...顯示區域
3303...開關
3304...操作鍵
3305...紅外線埠
3401...殼體
3402...顯示區域
3403...揚聲器
3404...操作鍵
3405...紀錄媒體插入部
於附圖中:
第1A與1B圖顯示本發明之半導體裝置;
第2A至2D圖顯示本發明之半導體裝置的製造步驟;
第3A至3D圖顯示本發明之半導體裝置的製造步驟;
第4A與4B圖顯示本發明之半導體裝置的製造步驟;
第5A至5D圖顯示本發明之半導體裝置的製造步驟;
第6A至6C圖顯示本發明之半導體裝置的製造步驟;
第7A與7B圖顯示傳統的範例;
第8A與8B圖顯示液晶顯示裝置的製造步驟;
第9A與9B圖顯示液晶顯示裝置的製造步驟;
第10A與10B圖顯示發光裝置的製造步驟;
第11A與11B圖顯示發光裝置的製造步驟;
第12A至12F圖各顯示發光裝置的等效電路;
第13圖顯示發光裝置的等效電路;
第14A圖描繪畫素部之上視圖以及第14B圖描繪發光裝置的等效電路;
第15A至15E各顯示應用本發明之電子設備的一範例;以及
第16圖顯示應用本發明之電子設備的一範例。
本發明之實施例於上參照附圖描述。注意到本發明不限於上述之實施方式,並且熟悉該項技藝者很容易了解可以各種方式變更在此揭露的實施例與細節,而不背離本發明的目的與範疇。因此,本發明不應解釋為受限於上述實施方式的說明。
1...基底
3...閘極電極
5...閘極絕緣薄膜
10...源極電極
10a...源極電極,第一導電薄膜
10b...源極電極,第二導電薄膜
11...汲極電極
11a...汲極電極,第一導電薄膜
11b...汲極電極,第二導電薄膜
13...島狀形狀之半導體薄膜
Claims (32)
- 一種裝置,包含:二極體,其包含:半導體薄膜,包括基底上方之通道形成區域,該半導體薄膜包含氧化鋅;閘極電極,與該半導體薄膜相鄰,且具有閘極絕緣薄膜插設於其間;及源極電極與汲極電極,與該半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該閘極電極之相同層所形成的導電層,其中,該閘極電極係電性連接至該源極電極與該汲極電極的其中一者,並且其中,該二極體之該源極電極與該汲極電極的該其中一者經由該二極體之該閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第1項之二極體,其中,該閘極電極係位在該通道形成區域下方。
- 如申請專利範圍第1項之二極體,其中,該閘極電極係位在該通道形成區域上方。
- 如申請專利範圍第1項之二極體,其中,該半導體薄膜係位在該源極電極與該汲極電極上方。
- 如申請專利範圍第1項之二極體,另包含在該半導體薄膜與該源極電極和該汲極電極之間的一對導電層,該 對導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一半導體薄膜,包含基底上方之氧化鋅,該第一半導體薄膜包括第一通道形成區域;第一閘極電極,與該第一半導體薄膜相鄰,且具有第一閘極絕緣薄膜插設於其間;及第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;畫素電極,係形成於該基底上方,該畫素電極係電性連接至該薄膜電晶體;信號線,係形成於該基底上方,其中,該第一源極電極與該第一汲極電極的其中一者係電性連接至該信號線;二極體,係電性連接至該信號線,該二極體包含:第二半導體薄膜,包括該基底上方之第二通道形成區域,該第二半導體薄膜包含氧化鋅;第二閘極電極,與該第二半導體薄膜相鄰,具有第二閘極絕緣薄膜插設於其間;及第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該二極體之該第二源極電極與該第二汲極電極的其中者一,並且 其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第6項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第6項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該信號線。
- 如申請專利範圍第6項之主動矩陣顯示裝置,其中,該第一半導體薄膜係位在該第一源極電極與該第一汲極電極上方,且該第二半導體薄膜係位在該第二源極電極與該第二汲極電極上方。
- 如申請專利範圍第6項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一閘極電極,於基底上方;第一閘極絕緣薄膜,於該第一閘極電極上方; 第一半導體薄膜,包含該第一閘極電極上方之氧化鋅,且具有該第一閘極絕緣薄膜插設於其間,該第一半導體薄膜包括通道形成區域;第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;絕緣薄膜,係形成於該薄膜電晶體上方;畫素電極,係形成於該絕緣薄膜上方,該畫素電極係電性連接至該薄膜電晶體;信號線,係形成於該基底上方,其中,該第一源極電極與該第一汲極電極的其中一者係電性連接至該信號線;二極體,係電性連接至該信號線,該二極體包含:第二閘極電極,於該基底上方;第二閘極絕緣薄膜,於該第二閘極電極上方;第二半導體薄膜,包含於該第二閘極電極上方之氧化鋅,且具有該第二閘極絕緣薄膜插設於其間;第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該第二源極電極與該第二汲極電極的其中一者,並且其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共 同電位線。
- 如申請專利範圍第11項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第11項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該信號線。
- 如申請專利範圍第11項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一半導體薄膜,包含基底上方之氧化鋅,該第一半導體薄膜包括第一通道形成區域;閘極電極,於該第一半導體薄膜上方,具有第一閘極絕緣薄膜插設於其間;及第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;畫素電極,係形成於該基底上方,該畫素電極係電性連接至該薄膜電晶體; 信號線,係形成於該基底上方,其中,該第一源極電極與該第一汲極電極的其中一者係電性連接至該信號線;二極體,係電性連接至該信號線,該二極體包含:第二半導體薄膜,包括該基底上方之第二通道形成區域,該第二半導體薄膜包含氧化鋅;第二閘極電極,於該第二半導體薄膜上方,具有第二閘極絕緣薄膜插設於其間;及第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該第二源極電極與該第二汲極電極的其中一者,並且其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第15項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第15項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該信號線。
- 如申請專利範圍第15項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極 電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一半導體薄膜,包含基底上方之氧化鋅,該第一半導體薄膜包括第一通道形成區域;第一閘極電極,與該第一半導體薄膜相鄰,具有第一閘極絕緣薄膜插設於其間;及第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;畫素電極,係形成於該基底上方,該畫素電極係電性連接至該薄膜電晶體;掃描線,係形成於該基底上方,其中,該第一閘極電極係電性連接至該掃描線;二極體,係電性連接至該掃描線,該二極體包含:第二半導體薄膜,包括該基底上方之第二通道形成區域,該第二半導體薄膜包含氧化鋅;第二閘極電極,與該第二半導體薄膜相鄰,具有第二閘極絕緣薄膜插設於其間;及第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及 共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該第二源極電極與該第二汲極電極的其中一者,並且其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第19項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第19項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該掃描線。
- 如申請專利範圍第19項之主動矩陣顯示裝置,其中,該第一半導體薄膜係位在該第一源極電極與該第一汲極電極上方,且該第二半導體薄膜係位在該第二源極電極與該第二汲極電極上方。
- 如申請專利範圍第19項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一閘極電極,於基底上方;第一閘極絕緣薄膜,於該第一閘極電極上方;第一半導體薄膜,包含該第一閘極電極上方之氧化鋅,具有該第一閘極絕緣薄膜插設於其間,該第一半導體薄膜包括通道形成區域;第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;絕緣薄膜,係形成於該薄膜電晶體上方;畫素電極,係形成於該絕緣薄膜上方,該畫素電極係電性連接至該薄膜電晶體;掃描線,係形成於該基底上方,其中,該第一閘極電極係電性連接至該掃描線;二極體,係電性連接至該掃描線,該二極體包含:第二閘極電極,於該基底上方;第二閘極絕緣薄膜,於該第二閘極電極上方;第二半導體薄膜,包含於該第二閘極電極上方之氧化鋅,具有該第二閘極絕緣薄膜插設於其間;第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該第二源極電極 與該第二汲極電極的其中一者,並且其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第24項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第24項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該掃描線。
- 如申請專利範圍第24項之主動矩陣顯示裝置,其中,該第二閘極電極和該第二源極電極與該第二汲極電極的該其中一者係電性連接至共同電位線。
- 如申請專利範圍第24項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
- 一種主動矩陣顯示裝置,包含:薄膜電晶體,包含:第一半導體薄膜,包含基底上方之氧化鋅,該第一半導體薄膜包括第一通道形成區域; 第一閘極電極,於該第一半導體薄膜上方,具有第一閘極絕緣薄膜插設於其間;及第一源極電極與第一汲極電極,與該第一半導體薄膜相鄰;畫素電極,係形成於該基底上方,該畫素電極係電性連接至該薄膜電晶體;掃描線,係形成於該基底上方,其中,該第一源極電極與該第一汲極電極的其中一者係電性連接至該掃描線;二極體,係電性連接至該掃描線,該二極體包含:第二半導體薄膜,包括該基底上方之第二通道形成區域,該第二半導體薄膜包含氧化鋅;閘極電極,於該第二半導體薄膜上方,具有第二閘極絕緣薄膜插設於其間;及第二源極電極與第二汲極電極,與該第二半導體薄膜相鄰;以及共同電位線,其中,該共同電位線包含由與該第一閘極電極和該第二閘極電極之相同層所形成的導電層,其中,該第二閘極電極係電性連接至該第二源極電極與該第二汲極電極的其中一者,並且其中,該第二源極電極與該第二汲極電極的該其中一者經由該第二閘極絕緣薄膜的接觸孔而被電性連接至該共同電位線。
- 如申請專利範圍第29項之主動矩陣顯示裝置,其中,該主動矩陣顯示裝置為發光裝置。
- 如申請專利範圍第29項之主動矩陣顯示裝置,其中,該第二源極電極與該第二汲極電極的另一者係電性連接至該掃描線。
- 如申請專利範圍第29項之主動矩陣顯示裝置,另包含:在該第一半導體薄膜與該第一源極電極和該第一汲極電極之間的一對第一導電層,該對第一導電層包含氧化鋅;以及在該第二半導體薄膜與該第二源極電極和該第二汲極電極之間的一對第二導電層,該對第二導電層包含氧化鋅。
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TW098110709A TWI423447B (zh) | 2005-11-15 | 2006-11-14 | 半導體裝置及其製造方法 |
TW098110687A TWI427799B (zh) | 2005-11-15 | 2006-11-14 | 半導體裝置及其製造方法 |
TW098132929A TW201005953A (en) | 2005-11-15 | 2006-11-14 | Semiconductor device and manufacturing method thereof |
TW098110673A TWI427708B (zh) | 2005-11-15 | 2006-11-14 | 半導體裝置及其製造方法 |
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US (7) | US8134156B2 (zh) |
JP (5) | JP5089636B2 (zh) |
KR (9) | KR20090130089A (zh) |
CN (8) | CN101577281B (zh) |
TW (8) | TWI429086B (zh) |
WO (1) | WO2007058329A1 (zh) |
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