JP6435124B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP6435124B2 JP6435124B2 JP2014136434A JP2014136434A JP6435124B2 JP 6435124 B2 JP6435124 B2 JP 6435124B2 JP 2014136434 A JP2014136434 A JP 2014136434A JP 2014136434 A JP2014136434 A JP 2014136434A JP 6435124 B2 JP6435124 B2 JP 6435124B2
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
本実施の形態では、半導体層と電荷捕獲層とゲート電極とを有する半導体装置の構成および動作原理について説明する。図1(A)は、半導体層101と電荷捕獲層102とゲート電極103とを有する半導体装置である。電荷捕獲層102はゲート絶縁層を兼ねることができる。
本実施の形態では、本発明の一態様の半導体装置について図面を用いて説明する。
本実施の形態では、実施の形態2で説明した図5に示すトランジスタ450の作製方法について、図9および図10を用いて説明する。
本実施の形態では、実施の形態2で説明したトランジスタとは異なるプレナー構造のトランジスタについて説明する。
本実施の形態では、実施の形態4で説明した図11に示すトランジスタ550の作製方法について、図14および図15を用いて説明する。
本実施の形態では、本発明の一態様のトランジスタを利用した回路の一例について、図面を参照して説明する。
本実施の形態では、本発明の一態様であるトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を、図面を用いて説明する。
本実施の形態では、少なくとも先の実施の形態で説明したトランジスタを用いることができ、先の実施の形態で説明した記憶装置を含むCPUについて説明する。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図21に示す。
102 電荷捕獲層
102a 第1の絶縁膜
102b 窒素とシリコンを含む絶縁膜
102c 第2の絶縁膜
103 ゲート電極
104 電子捕獲準位
105 電子
106 曲線
107 曲線
108 トランジスタ
109 容量素子
111 ホール捕獲準位
400 基板
402 下地絶縁膜
403c 酸化物半導体膜
404 多層膜
404a 酸化物半導体膜
404b 酸化物半導体膜
404c 酸化物半導体膜
406a ソース電極
406b ドレイン電極
407 ゲート絶縁膜
407a 第1の絶縁膜
407b トラップ膜
408a 第1の絶縁膜
408b トラップ膜
408c 第2の絶縁膜
409 導電膜
410 ゲート電極
412 酸化物絶縁膜
450 トランジスタ
470 トランジスタ
501 筐体
502 筐体
503 表示部
504 表示部
505 マイクロフォン
506 スピーカー
507 操作キー
508 スタイラス
511 筐体
512 筐体
513 表示部
514 表示部
515 接続部
516 操作キー
521 筐体
522 表示部
523 キーボード
524 ポインティングデバイス
531 筐体
532 冷蔵室用扉
533 冷凍室用扉
541 筐体
542 筐体
543 表示部
544 操作キー
545 レンズ
546 接続部
550 トランジスタ
551 車体
552 車輪
553 ダッシュボード
554 ライト
570 トランジスタ
602 フォトダイオード
640 トランジスタ
656 トランジスタ
658 フォトダイオードリセット信号線
659 ゲート信号線
672 フォトセンサ基準信号線
700 記憶素子
701 回路
702 回路
703 スイッチ
704 スイッチ
706 論理素子
707 容量素子
708 容量素子
709 トランジスタ
710 トランジスタ
713 トランジスタ
714 トランジスタ
720 回路
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
2200 トランジスタ
2201 絶縁膜
2202 配線
2203 プラグ
2204 絶縁膜
2205 配線
2206 配線
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3200 トランジスタ
3300 トランジスタ
3400 容量素子
Claims (2)
- 半導体膜と、
第1及び第2の絶縁膜の積層構造を有するゲート絶縁膜と、
前記ゲート絶縁膜を介して前記半導体膜と重なる領域を有するゲート電極と、
前記半導体膜と電気的に接続し、ソース電極又はドレイン電極としての機能を有する導電層と、を形成する半導体装置の作製方法であって、
前記第1の絶縁膜は、前記半導体膜と接する領域を有し、
前記第1の絶縁膜は、前記第2の絶縁膜と接する領域を有し、
前記第2の絶縁膜は、前記ゲート電極と接する領域を有し、
前記ゲート電極と前記導電層との間に電位差を有する状態において、前記半導体装置の加熱処理を行うことを特徴とする半導体装置の作製方法。 - 半導体膜と、
第1及び第2の絶縁膜の積層構造を有するゲート絶縁膜と、
前記ゲート絶縁膜を介して前記半導体膜と重なる領域を有するゲート電極と、
前記半導体膜と電気的に接続し、ソース電極又はドレイン電極としての機能を有する導電層と、を形成する半導体装置の作製方法であって、
前記第1の絶縁膜は、前記半導体膜と接する領域を有し、
前記第1の絶縁膜は、前記第2の絶縁膜と接する領域を有し、
前記第2の絶縁膜は、前記ゲート電極と接する領域を有し、
前記第2の絶縁膜は、窒素とシリコンを有し、
前記ゲート電極と前記導電層との間に電位差を有する状態において、前記半導体装置に、125℃以上450℃以下の加熱処理を行い、前記第1の絶縁膜と前記第2の絶縁膜との界面又は前記第2の絶縁膜内部に電荷を捕獲することを特徴とする半導体装置の作製方法。
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