CN110890428B - 氧化物半导体场效晶体管及其形成方法 - Google Patents

氧化物半导体场效晶体管及其形成方法 Download PDF

Info

Publication number
CN110890428B
CN110890428B CN201811041792.1A CN201811041792A CN110890428B CN 110890428 B CN110890428 B CN 110890428B CN 201811041792 A CN201811041792 A CN 201811041792A CN 110890428 B CN110890428 B CN 110890428B
Authority
CN
China
Prior art keywords
layer
oxide semiconductor
insulating layer
drain
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811041792.1A
Other languages
English (en)
Other versions
CN110890428A (zh
Inventor
赖建铭
陈彦臻
黄仁柏
黄圣尧
陈慧玲
邢庆刚
陈鼎龙
丁莉莉
刘耀鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201811041792.1A priority Critical patent/CN110890428B/zh
Priority to US16/154,644 priority patent/US11088285B2/en
Publication of CN110890428A publication Critical patent/CN110890428A/zh
Priority to US17/140,114 priority patent/US11342465B2/en
Priority to US17/367,637 priority patent/US11631771B2/en
Priority to US18/103,505 priority patent/US12027629B2/en
Application granted granted Critical
Publication of CN110890428B publication Critical patent/CN110890428B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开一种氧化物半导体场效晶体管,包含有一第一绝缘层、一源极、一漏极、一U形通道层以及一金属栅极。第一绝缘层设置于一基底上。源极以及漏极设置于第一绝缘层中。U形通道层夹置于源极以及漏极之间。金属栅极设置于U形通道层上,其中U形通道层包含至少一氧化物半导体层。本发明更提供一种形成此氧化物半导体场效晶体管的方法。

Description

氧化物半导体场效晶体管及其形成方法
技术领域
本发明涉及一种氧化物半导体场效晶体管及其形成方法,且特别是涉及一种具有U形通道层的氧化物半导体场效晶体管及其形成方法。
背景技术
在集成电路中及液晶显示装置中常见使用非晶硅、多晶硅等来形成晶体管,其位于具有绝缘表面的基底或者玻璃基底上。使用非晶硅制造的晶体管较容易形成在较大的玻璃基底上。然而,使用非晶硅制造的晶体管具有低场效迁移率的缺点。虽然使用多晶硅制造的晶体管具有高场效迁移率,但是其具有不适合于较大玻璃基底的缺点。
与具有上述缺点的使用硅制造的晶体管相比,使用氧化物半导体来制造晶体管的技术已受到注目,并将此晶体管应用于电子设备或光学装置。例如,使用包含铟(In)、锌(Zn)、镓(Ga)、锡(Sn)等的氧化物作为氧化物半导体来制造晶体管或者用作显示装置的像素中的开关元件等。
发明内容
本发明提出一种氧化物半导体场效晶体管及其形成方法,其仅在源极以及漏极之间形成U形通道层而不再另外形成其他通道层,因而能简化制作工艺,并改善背电极的可靠度及对于通道层与临界电压的调变能力。
本发明提供一种氧化物半导体场效晶体管,包含有一第一绝缘层、一源极、一漏极、一U形通道层以及一金属栅极。第一绝缘层设置于一基底上。源极以及漏极设置于第一绝缘层中。U形通道层夹置于源极以及漏极之间。金属栅极设置于U形通道层上,其中U形通道层包含至少一氧化物半导体层。
本发明提供一种形成氧化物半导体场效晶体管的方法包含有下述步骤。首先,形成一背电极于一绝缘层中。接着,形成一背电极绝缘层于绝缘层上。接续,形成一源/漏极层于背电极绝缘层上。续之,形成一第一绝缘层覆盖源/漏极层以及背电极绝缘层。之后,图案化第一绝缘层以及源/漏极层,因而形成一源极以及一漏极,以及一凹槽位于第一绝缘层中,凹槽分隔源极以及漏极,并暴露出背电极绝缘层。而后,形成一U形通道层以及一金属栅极于凹槽中,其中U形通道层包含至少一氧化物半导体层。
基于上述,本发明提出一种氧化物半导体场效晶体管及其形成方法,其直接形成一源极以及一漏极于背电极绝缘层上,且形成包含至少一氧化物半导体层的一U形通道层夹置于源极以及漏极之间,一金属栅极则形成于U形通道层上。本发明不再另外形成其他通道层,如此可简化结构、限制仅有U形通道层为载流子来源,进而增进背电极的可靠度及对于通道层的控制能力,使背电极调变临界电压更有效率。
附图说明
图1为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图2为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图3为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图及俯视图;
图4为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图5为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图6为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图7为本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图8为本发明另一优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图9为本发明另一优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图;
图10为本发明另一优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图。
主要元件符号说明
100:氧化物半导体场效晶体管
110:基底
120:绝缘层
122:背电极
124:背电极通孔
130:背电极绝缘层
140a、140b:源/漏极层
142、242:源极
144、244:漏极
152、152’、252:盖层
154、154’、254:第一绝缘层
162:U形通道层
162’、262:通道层
164、264:金属栅极
164’:金属栅极层
164a、164a’、264a:栅极氧化层
164ab:复合层
164b、164b’、264b:金属层
164c、164c’、264c:低电阻率金属
270:栅极盖层
R、R1:凹槽
T1、T2、T3、T4:顶面
具体实施方式
图1-图2、图4-图7绘示本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图。图3绘示本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图及俯视图。如图1所示,提供一基底110。基底110例如是一硅基底、一含硅基底(例如SiC)、一三五族基底(例如GaN)、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)、一硅覆绝缘(silicon-on-insulator,SOI)基底或一含外延层的基底等半导体基底。形成一绝缘层120于基底110上。绝缘层120可例如为一层间介电层,其可例如为一氧化层,但本发明不以此为限。
接着,形成一背电极122于绝缘层120中。背电极122可例如包含一阻障层(未绘示)、一晶种层(未绘示)以及一导电材料(未绘示)。形成背电极122的方法可例如先形成一凹槽(未绘示)于绝缘层120中,一阻障层(未绘示)以及一晶种层(未绘示)顺应覆盖凹槽,再以一导电材料(未绘示)填满凹槽,之后移除(或者平坦化)凹槽外的导电材料、晶种层以及阻障层至暴露出绝缘层120,因而形成背电极122。阻障层可包含钽(tantalum,Ta)、钛(titanium,Ti)、氮化钽(tantalum nitride,TaN)、氮化钛(titanium nitride,TiN)、氮化钨(tungsten nitride,WN)或此些材料的组合。晶种层的材料较佳与导电材料相同,其可包含铝(aluminum,Al)、钛(titanium,Ti)、钽(tantalum,Ta)、钨(tungsten,W)、铜(copper,Cu)、钼(molybdenum,Mo)、铌(niobium,Nb)等。另外,背电极122又可例如接触下方的一背电极通孔124以连接其他元件,其中背电极122及背电极通孔124可例如以双镶嵌制作工艺形成,但本发明不以此为限。接着,形成一背电极绝缘层130于绝缘层120上。背电极绝缘层130可例如为一氧化层,但本发明不以此为限。
如图2所示,形成一源/漏极层140a于背电极绝缘层130上。源/漏极层140a的材料可包含铝(aluminum,Al)、铬(chromium,Cr)、铜(copper,Cu)、钽(tantalum,Ta)、钛(titanium,Ti)、钨(tungsten,W)等金属或此些金属的合金,但本发明不限于此。接着,如图3所示,图案化源/漏极层140a以定义欲形成一氧化物半导体场效晶体管的图案,因而形成一源/漏极层140b,其中图3的a部分绘示本发明优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图,而图3的b部分绘示本发明优选实施例中形成氧化物半导体场效晶体管的方法的俯视图。例如,图3的b部分的源/漏极层140b的俯视图案可为两端宽中间窄的哑铃形,但本发明不以此为限。在此强调,如图3的a部分所示,本发明直接将源/漏极层140b形成于背电极绝缘层130上,而源/漏极层140b及背电极绝缘层130之间不再形成其他材料层,特别是不再形成氧化物半导体层等通道层,因而本发明可简化制作工艺、并增进背电极的稳定性及调变能力。
如图4所示,选择性形成一盖层152’顺应覆盖源/漏极层140b以及背电极绝缘层130,再形成一第一绝缘层154’覆盖源/漏极层140b以及背电极绝缘层130(覆盖盖层152’)。盖层152’可例如为一氮化层,而第一绝缘层154’可例如为一氧化层,但本发明不限于此。
接续,图案化第一绝缘层154’以及源/漏极层140b,因而形成一源极142以及一漏极144,以及一凹槽R位于一盖层152以及一第一绝缘层154中,其中凹槽R分隔源极142以及漏极144,并直接暴露出背电极绝缘层130,如图5所示。
如图6所示,依序形成一通道层162’顺应覆盖凹槽R以及第一绝缘层154,以及形成一金属栅极层164’顺应覆盖于通道层162’上。本发明的通道层162’必然包含至少一氧化物半导体层。在一实施例中,通道层162’可例如包含多个氧化物半导体层,而此些氧化物半导体层可具有不同材料或者应用不同制作工艺或者额外制作工艺形成。例如,在本实施例中,通道层162’为三层具有不同材料的氧化物半导体层,以作为载流子来源,其中上层的氧化物半导体层可经由氧化下层的氧化物半导体层而形成,但本发明不限于此。氧化物半导体层的材料可例如为氧化铟镓锌(indium gallium zinc oxide,IGZO)、氧化铟镓(indiumgallium oxide,IGO)、氧化铟铝锌(indium alluminum zinc oxide,IAlZO)、氧化铟镓铝锌(indium gallium alluminum zinc oxide,IGAlZO)、氧化铟锌(indium zinc oxide,IZO)、氧化铟锌锡(indium tin zinc oxide,IZTO)、氧化铟锌锡铝(indium tin alluminum zincoxide,IZTAlO)、氧化铟锌铪铝(indium hafnium alluminum zinc oxide,IZHfAlO)、氧化锌锡(zinc tin oxide,ZTO)等,但本发明不以此为限。金属栅极层164’则可包含一栅极氧化层164a’、一金属层164b’以及一低电阻率金属164c’,其中栅极氧化层164a’可例如包含氧化硅;金属层164b’可例如为单层结构或复合层结构,其可包含氮化钛(titaniumnitride,TiN)、碳化钛(titanium carbide,TiC)、氮化钽(tantalum nitride,TaN)、碳化钽(tantalum carbide,TaC)、碳化钨(tungsten carbide,WC)、铝化钛(titanium aluminide,TiAl)或氮化铝钛(aluminum titanium nitride,TiAlN);低电阻率金属164c’可包含铝(aluminum,Al)、钛(titanium,Ti)、钽(tantalum,Ta)、钨(tungsten,W)、铜(copper,Cu)、钼(molybdenum,Mo)、铌(niobium,Nb)等金属。在本实施例中,栅极氧化层164a’为一氧化硅层,而金属层164b’为一氮化钛层,但本发明不以此为限。
而后,移除超出凹槽R的金属栅极层164’以及通道层162’,因而形成一U形通道层162以及一金属栅极164,而金属栅极164包含一栅极氧化层164a、一金属层164b以及一低电阻率金属164c,如图7所示。由于本发明先形成源/漏极层140b、盖层152’以及第一绝缘层154’,再图案化第一绝缘层154’、盖层152’以及源/漏极层140b而形成源极142以及漏极144并形成凹槽R于盖层152以及第一绝缘层154中,最后才填入U形通道层162以及金属栅极164,因此本发明的栅极氧化层164a以及金属层164b也具有U形剖面结构,且U形通道层162以及金属栅极164夹置于源极142以及漏极144之间。
再者,U形通道层162的一顶面T1高于源极142以及漏极144的顶面T2;金属栅极164的一顶面T3高于源极142以及漏极144的顶面T2;U形通道层162的顶面T1与第一绝缘层154的一顶面T4共平面。在一优选实施例中,本发明的一氧化物半导体场效晶体管100的背栅极122设置于U形通道层162正下方,且全部的U形通道层162垂直重叠背栅极122;在一更佳的实施例中,背栅极122突出于U形通道层162,因而能增进背电极122的稳定性及对于U形通道层162的调变能力。
承上,由于源极142以及漏极144直接位于背电极绝缘层130上,而U形通道层162夹置于源极142以及漏极144之间,且源极142/漏极144与背电极绝缘层130之间不再形成例如氧化物半导体层等通道层,因而本发明可简化氧化物半导体场效晶体管100的结构、限制载流子来源仅有U形通道层162,进而能增进背电极的可靠度及对于U形通道层162的控制能力,使背电极调变临界电压等更有效率。更进一步而言,当例如图6的栅极氧化层164a’为一氧化硅层,而金属层164b’为一氮化钛层时、栅极氧化层164a以及金属层164b之间可形成一复合层164ab,俾能降低临界电压,如图8所示。
另外,本发明再提出一实施例,其先形成通道层才全面覆盖第一绝缘层。图9-图10绘示本发明另一优选实施例中形成氧化物半导体场效晶体管的方法的剖面示意图。如图9所示,在如图3所示图案化源/漏极层140a以定义欲形成一氧化物半导体场效晶体管的图案,因而形成源/漏极层140b之后,改为先选择性形成一盖层(未绘示)顺应覆盖源/漏极层140b以及背电极绝缘层130,并图案化盖层以及源/漏极层140b,因而形成一盖层252覆盖一源极242以及一漏极244,以及一凹槽R1分隔源极242以及漏极244,并直接暴露出背电极绝缘层130。盖层252可例如为一氮化层,但本发明不限于此。
接着,如图10所示,可依序形成一通道层(未绘示)、一栅极氧化层(未绘示)、一金属层(未绘示)以及一低电阻率金属(未绘示)顺应覆盖背电极绝缘层130、源极242、漏极244以及凹槽R1;图案化低电阻率金属(未绘示)以及金属层(未绘示);顺应覆盖一栅极盖层(未绘示);再一并图案化栅极盖层(未绘示)、栅极氧化层(未绘示)以及通道层(未绘示),而形成一通道层262、一金属栅极264以及一栅极盖层270。本发明的通道层262必然包含至少一氧化物半导体层。在一实施例中,通道层262可例如包含多个氧化物半导体层,而此些氧化物半导体层可具有不同材料或者应用不同制作工艺或者额外制作工艺形成。例如,在本实施例中,通道层262为三层具有不同材料的氧化物半导体层,以作为载流子来源,其中上层的氧化物半导体层可经由氧化下层的氧化物半导体层而形成,但本发明不限于此。氧化物半导体层的材料可例如为氧化铟镓锌(indium gallium zinc oxide,IGZO)、氧化铟镓(indium gallium oxide,IGO)、氧化铟铝锌(indium alluminum zinc oxide,IAlZO)、氧化铟镓铝锌(indium gallium alluminum zinc oxide,IGAlZO)、氧化铟锌(indium zincoxide,IZO)、氧化铟锌锡(indium tin zinc oxide,IZTO)、氧化铟锌锡铝(indium tinalluminum zinc oxide,IZTAlO)、氧化铟锌铪铝(indium hafnium alluminum zincoxide,IZHfAlO)、氧化锌锡(zinc tin oxide,ZTO)等,但本发明不以此为限。金属栅极264则可包含一栅极氧化层264a、一金属层264b以及一低电阻率金属264c,其中栅极氧化层264a可例如包含氧化硅;金属层264b可例如为单层结构或复合层结构,其可包含氮化钛(titanium nitride,TiN)、碳化钛(titanium carbide,TiC)、氮化钽(tantalum nitride,TaN)、碳化钽(tantalum carbide,TaC)、碳化钨(tungsten carbide,WC)、铝化钛(titaniumaluminide,TiAl)或氮化铝钛(aluminum titanium nitride,TiAlN);低电阻率金属264c可包含铝(aluminum,Al)、钛(titanium,Ti)、钽(tantalum,Ta)、钨(tungsten,W)、铜(copper,Cu)、钼(molybdenum,Mo)、铌(niobium,Nb)等金属。栅极盖层270可例如为一氮化层。之后,才全面覆盖并平坦化形成一第一绝缘层254。第一绝缘层254可例如为一氧化层,但本发明不以此为限。本实施例较先前的实施例则具有不同剖面结构的通道层262以及金属栅极264,视实际需要而定。
综上所述,本发明提出一种氧化物半导体场效晶体管及其形成方法,其直接形成一源极以及一漏极于背电极绝缘层上,且形成包含至少一氧化物半导体层的一U形通道层夹置于源极以及漏极之间,一金属栅极则形成于U形通道层上。本发明不再另外形成其他通道层,如此可简化结构、限制仅有U形通道层为载流子来源,进而能改善背电极对于U形通道层的控制能力。特别是,本发明不再形成例如氧化物半导体层等通道层于源极/漏极与下方的背电极绝缘层之间,因而能增进背电极的稳定性及控制能力,使背电极调变临界电压更有效率。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (18)

1.一种氧化物半导体场效晶体管,其特征在于,包含有:
第一绝缘层,设置于一基底上;
源极以及漏极,设置于该第一绝缘层中;
仅U形通道层,夹置于该源极以及该漏极之间,在该源极以及该漏极下方不具有任何通道层;
金属栅极,设置于该U形通道层上,其中该金属栅极包含栅极氧化层和金属层,且该U形通道层包含多个氧化物半导体层;以及
复合层,位于该栅极氧化层以及该金属层之间。
2.如权利要求1所述的氧化物半导体场效晶体管,其中该金属栅极包含低电阻率金属。
3.如权利要求2所述的氧化物半导体场效晶体管,其中该栅极氧化层以及该金属层具有U形剖面结构。
4.如权利要求1所述的氧化物半导体场效晶体管,其中该金属栅极的一顶面高于该源极以及该漏极的顶面。
5.如权利要求1所述的氧化物半导体场效晶体管,其中该U形通道层的一顶面高于该源极以及该漏极的顶面。
6.如权利要求1所述的氧化物半导体场效晶体管,还包含:
绝缘层,设置于该第一绝缘层以及该基底之间。
7.如权利要求6所述的氧化物半导体场效晶体管,还包含:
背电极绝缘层,设置于该第一绝缘层以及该绝缘层之间。
8.如权利要求6所述的氧化物半导体场效晶体管,还包含:
背栅极,设置于该U形通道层正下方以及该绝缘层中。
9.如权利要求8所述的氧化物半导体场效晶体管,其中全部的该U形通道层垂直重叠该背栅极。
10.如权利要求9所述的氧化物半导体场效晶体管,其中该背栅极突出于该U形通道层。
11.如权利要求1所述的氧化物半导体场效晶体管,还包含:
盖层,顺应覆盖该源极以及该漏极,且该第一绝缘层全面覆盖该盖层。
12.一种形成氧化物半导体场效晶体管的方法,包含有:
形成一背电极于一绝缘层中;
形成一背电极绝缘层于该绝缘层上;
形成一源/漏极层于该背电极绝缘层上;
形成一第一绝缘层覆盖该源/漏极层以及该背电极绝缘层;
图案化该第一绝缘层以及该源/漏极层,因而形成一源极以及一漏极,以及一凹槽位于该第一绝缘层中,该凹槽分隔该源极以及该漏极,并暴露出该背电极绝缘层;以及
形成一U形通道层以及一金属栅极于该凹槽中,其中该U形通道层包含至少一氧化物半导体层。
13.如权利要求12所述的形成氧化物半导体场效晶体管的方法,其中该金属栅极包含一栅极氧化层、一金属层以及一低电阻率金属。
14.如权利要求13所述的形成氧化物半导体场效晶体管的方法,还包含:
复合层,位于该栅极氧化层以及该金属层之间。
15.如权利要求13所述的形成氧化物半导体场效晶体管的方法,其中该栅极氧化层以及该金属层具有U形剖面结构。
16.如权利要求12所述的形成氧化物半导体场效晶体管的方法,其中该U形通道层的一顶面高于该源极以及该漏极的顶面。
17.如权利要求12所述的形成氧化物半导体场效晶体管的方法,其中该U形通道层的一顶面与该第一绝缘层的一顶面共平面。
18.如权利要求12所述的形成氧化物半导体场效晶体管的方法,其中形成该U形通道层以及该金属栅极于该凹槽中的步骤,包含:
依序形成一通道层顺应覆盖该凹槽以及该第一绝缘层,以及一金属栅极层于该通道层上;以及
移除超出该凹槽的该金属栅极层以及该通道层。
CN201811041792.1A 2018-09-07 2018-09-07 氧化物半导体场效晶体管及其形成方法 Active CN110890428B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201811041792.1A CN110890428B (zh) 2018-09-07 2018-09-07 氧化物半导体场效晶体管及其形成方法
US16/154,644 US11088285B2 (en) 2018-09-07 2018-10-08 Oxide semiconductor field effect transistor and forming method thereof
US17/140,114 US11342465B2 (en) 2018-09-07 2021-01-03 Method of forming oxide semiconductor field effect transistor
US17/367,637 US11631771B2 (en) 2018-09-07 2021-07-06 Oxide semiconductor field effect transistor
US18/103,505 US12027629B2 (en) 2018-09-07 2023-01-31 Oxide semiconductor field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811041792.1A CN110890428B (zh) 2018-09-07 2018-09-07 氧化物半导体场效晶体管及其形成方法

Publications (2)

Publication Number Publication Date
CN110890428A CN110890428A (zh) 2020-03-17
CN110890428B true CN110890428B (zh) 2023-03-24

Family

ID=69720070

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811041792.1A Active CN110890428B (zh) 2018-09-07 2018-09-07 氧化物半导体场效晶体管及其形成方法

Country Status (2)

Country Link
US (4) US11088285B2 (zh)
CN (1) CN110890428B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890428B (zh) * 2018-09-07 2023-03-24 联华电子股份有限公司 氧化物半导体场效晶体管及其形成方法
CN111063683B (zh) * 2019-12-06 2022-08-30 中国科学院微电子研究所 具有u形沟道的半导体装置及包括其的电子设备
TW202130846A (zh) * 2020-02-03 2021-08-16 荷蘭商Asm Ip私人控股有限公司 形成包括釩或銦層的結構之方法
EP4195273A4 (en) * 2020-08-24 2024-01-31 Changxin Memory Technologies, Inc. SEMICONDUCTOR STRUCTURE AND ITS MANUFACTURING METHOD
CN117276326A (zh) * 2022-06-10 2023-12-22 中国科学院微电子研究所 一种晶体管器件及存储器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101283444A (zh) * 2005-11-15 2008-10-08 株式会社半导体能源研究所 半导体器件及其制造方法
CN103579361A (zh) * 2013-10-23 2014-02-12 昆山龙腾光电有限公司 金属氧化物半导体薄膜晶体管及其制造方法
CN103633147A (zh) * 2013-09-13 2014-03-12 友达光电股份有限公司 薄膜晶体管及其制造方法
US8981367B2 (en) * 2011-12-01 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7282782B2 (en) * 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
KR20070101595A (ko) * 2006-04-11 2007-10-17 삼성전자주식회사 ZnO TFT
US7804130B1 (en) * 2008-08-26 2010-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned V-channel MOSFET
US8187919B2 (en) 2008-10-08 2012-05-29 Lg Display Co. Ltd. Oxide thin film transistor and method of fabricating the same
EP2202802B1 (en) * 2008-12-24 2012-09-26 Semiconductor Energy Laboratory Co., Ltd. Driver circuit and semiconductor device
TWI529942B (zh) 2009-03-27 2016-04-11 半導體能源研究所股份有限公司 半導體裝置
WO2012102183A1 (en) 2011-01-26 2012-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
TWI453805B (zh) 2011-02-11 2014-09-21 Au Optronics Corp 顯示器及其製作方法
US8946812B2 (en) 2011-07-21 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8841665B2 (en) 2012-04-06 2014-09-23 Electronics And Telecommunications Research Institute Method for manufacturing oxide thin film transistor
TWI605593B (zh) 2012-11-15 2017-11-11 半導體能源研究所股份有限公司 半導體裝置
US8981374B2 (en) 2013-01-30 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9007092B2 (en) 2013-03-22 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN107210227B (zh) * 2015-02-06 2021-03-16 株式会社半导体能源研究所 半导体装置及其制造方法
US9349728B1 (en) 2015-03-27 2016-05-24 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN106206461A (zh) 2015-04-30 2016-12-07 联华电子股份有限公司 半导体结构
CN106409847B (zh) 2015-07-29 2020-05-12 联华电子股份有限公司 影像感测器像素结构
US9627549B1 (en) 2015-10-05 2017-04-18 United Microelectronics Corp. Semiconductor transistor device and method for fabricating the same
US9564217B1 (en) 2015-10-19 2017-02-07 United Microelectronics Corp. Semiconductor memory device having integrated DOSRAM and NOSRAM
US9991266B2 (en) * 2016-06-13 2018-06-05 United Microelectronics Corp. Semiconductor memory device and semiconductor memory array comprising the same
US9847428B1 (en) * 2016-08-08 2017-12-19 United Microelectronics Corp. Oxide semiconductor device
US10313611B2 (en) 2017-06-03 2019-06-04 United Microelectronics Corp. Image sensor with pixel binning device
US20190027576A1 (en) * 2017-07-21 2019-01-24 Qualcomm Incorporated Composite channel metal-oxide-semiconductor field effect transistor (mosfet)
CN110890428B (zh) * 2018-09-07 2023-03-24 联华电子股份有限公司 氧化物半导体场效晶体管及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101283444A (zh) * 2005-11-15 2008-10-08 株式会社半导体能源研究所 半导体器件及其制造方法
US8981367B2 (en) * 2011-12-01 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN103633147A (zh) * 2013-09-13 2014-03-12 友达光电股份有限公司 薄膜晶体管及其制造方法
CN103579361A (zh) * 2013-10-23 2014-02-12 昆山龙腾光电有限公司 金属氧化物半导体薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
CN110890428A (zh) 2020-03-17
US11342465B2 (en) 2022-05-24
US11631771B2 (en) 2023-04-18
US20230178657A1 (en) 2023-06-08
US20210336059A1 (en) 2021-10-28
US11088285B2 (en) 2021-08-10
US20210126131A1 (en) 2021-04-29
US20200083380A1 (en) 2020-03-12
US12027629B2 (en) 2024-07-02

Similar Documents

Publication Publication Date Title
CN110890428B (zh) 氧化物半导体场效晶体管及其形成方法
US10522532B2 (en) Through via extending through a group III-V layer
US9196698B2 (en) Semiconductor device having a gate dielectric film which is thinner below a source or drain electrode than below a channel region
CN108257871A (zh) 半导体器件及其制造方法
US11211497B2 (en) Semiconductor device
CN105684134A (zh) 具有用于产生附加构件的多晶硅层的氮化镓晶体管
US11411089B2 (en) Semiconductor device and manufacturing method thereof
US9831350B2 (en) Thin film transistor and method of manufacturing the same
US12009415B2 (en) High electron mobility transistor and method for fabricating the same
US9847428B1 (en) Oxide semiconductor device
CN112750700B (zh) 高电子迁移率晶体管及其制作方法
CN116995076A (zh) 半导体器件
US9349728B1 (en) Semiconductor device and method for fabricating the same
CN111081773B (zh) 氧化物半导体装置以及其制作方法
CN112928161A (zh) 高电子迁移率晶体管及其制作方法
US11004937B1 (en) Semiconductor device and manufacturing method thereof
CN113823676B (zh) 半导体装置以及其制作方法
KR20150019137A (ko) 고 이동도 박막 트랜지스터 및 그 제조방법과 고 이동도 박막 트랜지스터를 포함하는 디스플레이
US20120217623A1 (en) Inter-level dielectric layer, semiconductor device having said inter-level dielectric layer and method for manufacturing the same
CN107046063A (zh) 薄膜晶体管及薄膜晶体管的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant