CN106206461A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN106206461A
CN106206461A CN201510216493.7A CN201510216493A CN106206461A CN 106206461 A CN106206461 A CN 106206461A CN 201510216493 A CN201510216493 A CN 201510216493A CN 106206461 A CN106206461 A CN 106206461A
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substrate
semiconductor
semiconductor structure
dielectric layer
igzo
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周志飚
吴少慧
古其发
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201510216493.7A priority Critical patent/CN106206461A/zh
Priority to US14/724,799 priority patent/US9627547B2/en
Publication of CN106206461A publication Critical patent/CN106206461A/zh
Priority to US15/447,081 priority patent/US10103273B2/en
Priority to US16/131,014 priority patent/US10644166B2/en
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Abstract

本发明提供一种半导体结构，包含有基底，第一元件，位于该基底中，并且该第一元件沿着第一方向排列，其中该第一元件由氧化半导体材质所形成，介电层覆盖于该第一元件上，以及第二元件，位于该介电层上，并且沿着该第一方向排列，其中该第二元件则作为晶体管结构的栅极使用。

Description

半导体结构
技术领域
本发明涉及一种半导体结构，尤其是一种整合氧化半导体材质，例如整合铟镓锌氧化物(In-Ga-Zn氧化物，IGZO)的晶体管结构。
背景技术
近期将半导体薄膜设于具有绝缘表面的基底上以形成晶体管的技术普遍受到注目，其中该晶体管可应用于例如集成电路或影像显示元件等各种电子元件中。目前广泛用来制作半导体薄膜的材料通常包含以硅为基础的半导体材料，而其中又以氧化物半导体更受到各界注目。
一般而言，包含前述氧化物半导体薄膜的晶体管在电路呈现关闭状态(off state)时具有非常低的漏电流。然而，现今在整合具有氧化物半导体层的晶体管与一般具有金属栅极的金氧半导体晶体管时仍遇到许多瓶颈，例如因制作流程过于复杂并造成成本增加等问题。因此如何改良现有包含氧化物半导体薄膜的晶体管元件的制程即为现今一个重要课题。
发明内容
本发明提供一种半导体结构，包含有基底，第一元件，位于该基底中，并且该第一元件沿着第一方向排列，其中该第一元件由氧化半导体材质所形成，介电层覆盖于该第一元件上，以及第二元件，位于该介电层上，并且沿着该第一方向排列，其中该第二元件则作为该晶体管结构的栅极使用。
本发明还提供一种半导体结构，包含有基底，基底内包含有绝缘区域，第一元件，位于该绝缘区域中，并且该第一元件沿着第一方向排列，其中该第一元件由氧化半导体材质所形成，介电层覆盖于该第一元件上，以及第二元件，位于该介电层上，并且沿着第二方向排列，其中该第二元件则作为该晶体管结构的栅极使用。
本发明所提供的晶体管结构均与氧化半导体材质整合，尤其是铟镓锌氧化物(IGZO)或是沿C轴结晶铟镓锌氧化物(CAAC-IGZO)，由于IGZO或是CAAC-IGZO比起熟知的常用于制作晶体管的半导体材质(例如硅)，具有较高的电子移动速率(mobility)。再者，使用IGZO制造的晶体管在晶体管元件处于关闭状态时，漏电流极少。IGZO材质的另外一项优势为低耗电量。因此，本发明以IGZO或是CAAC-IGZO材质取代部分晶体管的通道区域，可有效提升晶体管的效能。
附图说明
图1至图6为本发明优选实施方案制作半导体元件的方法示意图。
图6A绘示图6中第一区域A、第二区域B以及部分第三区域C的上视图。
图7A绘示本发明另一实施方案中第一区域A的上视图。
具体实施方式
请参照图1至图6，图1至图6为本发明优选实施方案制作半导体元件的方法示意图。如图1所示，首先提供基底12，基底12例如是硅基底、磊晶硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator，SOI)基底等的半导体基底，但不以此为限。在本发明中，基底12上优选定义有第一区域A、第二区域B与第三区域C，其中第一区域A优选于后续制程中形成本发明晶体管的第一实施方案，第二区域B则优选用来形成本发明晶体管的第二实施方案，第三区域C则可用来形成熟知的晶体管结构，以用于与第一区域A或是第二区域B内的晶体管结构互相比较。
值得注意的是，上述段落中，虽然将第一区域A、第二区域与第三区域C都同时定义在基底上，但是本发明不需要同时包含有第一区域A、第二区域B与第三区域C。换句话说，若基底上仅包含有第一区域A内所表示的晶体管结构，或是仅包含有第二区域B内所表示的晶体管结构，也都属于本发明所涵盖的范围内。以下不再另外赘述。
依据本发明的一个实施方案，基底12中可选择性形成多个掺杂井(未绘示)，或多个作为电性隔离之用的绝缘区域14，例如为浅沟槽隔离(shallowtrench isolation，STI)，绝缘区域14位于基底12中。
此外，基底12上优选形成有介电层，上述介电层可能为单层或多层结构，以本实施方案为例，介电层包含氧化层16与氮化层18，但不以此为限，介电层材质还可依照实际需求而调整。此外，介电层可包含为制作绝缘区域14时的遮罩与停止层。
另外本实施方案虽以平面型晶体管为例，但在其他变化实施方案中，本发明的半导体制程也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于基底上的鳍状结构。此时上述介电层可为制作鳍状结构时的遮罩与制作绝缘区域14时的停止层。
接着如图2所示，在第一区域A内的基底12中，以及第二区域B内的绝缘区域14中形成至少一个凹槽20。各凹槽20例如通过蚀刻步骤所形成，但不限于此。
如图3所示，在第一区域A以及第二区域B内的凹槽20内填入氧化半导体材料22，填入氧化半导体材料22后的凹槽20形成第一元件24。其中上述氧化半导体材料例如为铟镓锌氧化物(In-Ga-Zn氧化物，IGZO)或是沿C轴结晶IGZO(c-axis aligned crystal IGZO，CAAC-IGZO)。接着，进行平坦化步骤，例如化学机械抛光(CMP)，移除位于介电层(例如氮化层18)表面多余的氧化半导体材料22，并形成平坦表面。
如图4～5所示，以回蚀刻步骤E1，去除氧化层16与氮化层18。并优选曝露出基底12的表面，此时各第一元件24的顶端高于基底12的表面。接着如图5所示，沉积氧化层26于基底12上，并且覆盖住各第一元件24。氧化层26例如为氧化铝(Al2O3)、氧化镓(Ga2O3)、二氧化铪(HfO2)等，但不限于此。氧化层26可达到保护底下第一元件24的功用，避免其在后续的步骤中被破坏。此外，氧化层26还可作为晶体管元件中的栅极介电层使用，也就是分隔晶体管元件中的栅极区域以及通道区域的介电层。
如图6所示，在第一区域A、第二区域B以及第三区域C内，形成多个第二元件28。更详细说明，第二元件28作为晶体管元件中的栅极使用，覆盖于氧化层26上，材质可包括多晶硅或是金属等。另外，可依据制程需求以先栅极(gate first)制程、后栅极(gate last)制程之先栅极介电层(high-k first)制程以及后栅极制程之后栅极介电层(high-k last)制程等方式制作完成，在此不另外赘述。
此外，图6A绘示图6中第一区域A、第二区域B以及部分第三区域C的上视图。如图6A所示，在第一区域A内，第一元件24与第二元件28(栅极)均沿着第一方向排列(例如为Y轴)，且优选地，其面积大于第一元件24的面积，因此从上视图来看，第二元件28完全覆盖了第一元件24。而第二元件28两侧的基底12中，形成源极(S)/漏极(D)及/或磊晶层(图中未示出)。值得注意的是，从前面的剖面图来看(例如图1～6)，绝缘区域形成于第二区域B内，而第一区域A内剖面图未表示绝缘区域14的位置，但从图6A来看，绝缘区域14环绕在源/漏极S/D外的基底中。
本发明中，请参考图6以及图6A，第一区域A与第二区域B分别形成两种不同型态的晶体管结构，两者皆与IGZO材质整合，换句话说，两者皆包含有由IGZO材质或是CAAC-IGZO材质构成的第一元件24，且第一元件24至少位于晶体管的通道区域，也就是位于源极与漏极之间。以第一区域A内的晶体管结构第一实施方案说明，第二元件28作为栅极使用，位于氧化层26上，而位于第二元件28两侧的基底12可植入离子后，作为晶体管的源/漏极使用。而第一元件24埋于基底12中，直接接触基底12，并位于源极S与漏极D之间，作为晶体管的通道区使用。由于IGZO(或是CAAC-IGZO)相对硅基底具有更快的电子移动速率，因此可以进一步提升晶体管的效能。而后续本实施方案可与其他相关半导体制程整合，例如形成层间介电层(interlayer dielectric，ILD)、进行硅化金属步骤、形成接触结构等，上述制程属于本领域常见技术，而在此不另外赘述。
此外，图7A绘示本发明另外一个实施方案中第一区域A的上视图。主要与图6A所示的晶体管差别在于，由于本发明第一元件24仅需要位于源极S与漏极D之间，而不一定需要延伸至外围的绝缘区域14中，因此本实施方案中，第一元件24的范围仅位于两侧的源极S以及漏极D之间，并不会延伸至绝缘区域14内，上述结构也属于本发明涵盖范围内，其他的材料特征如前所述，在此不另外赘述。
再参考第二区域B内的晶体管结构，也就是本发明的晶体管结构的第二实施方案，与第一实施方案不同的是，本实施方案中，基底12内进一步包含有绝缘区域14，而第一元件24埋于绝缘区域14内，且沿着第一方向排列(例如为Y轴)，第二元件28横跨于第一元件24上，沿着第二方向(例如为X轴)排列，优选而言，第二元件28与第一元件24的排列方向互相垂直。此外从剖面图来看(图6)，绝缘区域14的顶端与第一元件24的顶端切齐，而第一元件24的顶端又高于基底12的表面。而本实施方案中，第二元件28同样位于氧化层26上，作为栅极使用，而位于第二元件28两侧的第一元件24则在掺杂离子之后形成源极S/漏极D。此外位于第二元件28正下方的第一元件24，也就是第二元件28与第一元件24的交叉处，则作为晶体管结构中的通道区域。
相比于熟知的晶体管结构，例如第三区域C内所形成的晶体管结构，本发明所提供的晶体管结构均与氧化半导体材质整合，尤其是铟镓锌氧化物(IGZO)或是沿C轴结晶铟镓锌氧化物(CAAC-IGZO)，由于IGZO或是CAAC-IGZO比起熟知的常用于制作晶体管的半导体材质(例如硅)，具有较高的电子移动速率(mobility)。再者，使用IGZO制造的晶体管在晶体管元件处于关闭状态时，漏电流极少。IGZO材质的另外一项优势为低耗电量。因此，本发明以IGZO或是CAAC-IGZO材质取代部分晶体管的通道区域，可有效提升晶体管的效能。
以上所述仅为本发明的优选实施方案，所有依本发明权利要求书所做的各种变化与修饰，均应属于本发明的涵盖范围。
主要元件符号说明
12 基底
14 绝缘区域
16 氧化层
18 氮化层
20 凹槽
22 氧化半导体材料
24 第一元件
26 氧化层
28 第二元件
A 第一区域
B 第二区域
C 第三区域
E1 回蚀刻步骤
S 源极
D 漏极

Claims (19)

1.一种半导体结构，包含有：
基底；
第一元件，位于该基底中，并且该第一元件沿着第一方向排列，其中该第一元件由氧化半导体材质所形成；
介电层覆盖于该第一元件上；以及
第二元件，位于该介电层上，并且沿着该第一方向排列，其中该第二元件则作为晶体管结构的栅极使用。
2.根据权利要求1的半导体结构，其中构成该第一元件的该氧化半导体材质为铟镓锌氧化物。
3.根据权利要求2的半导体结构，其中该IGZO进一步包含沿C轴结晶IGZO。
4.根据权利要求1的半导体结构，其中该第二元件的材质包含多晶硅。
5.根据权利要求1的半导体结构，其中该第一元件与该基底直接接触。
6.根据权利要求1的半导体结构，其中该第一元件的顶面高于该基底的顶面。
7.根据权利要求1的半导体结构，其中该介电层的材质包含氧化铝以及氧化镓。
8.根据权利要求1的半导体结构，其中该第二元件完整覆盖该第一元件的范围。
9.根据权利要求1的半导体结构，其中该基底包含硅基底。
10.根据权利要求1的半导体结构，其中部分的该第一元件位于该半导体结构的源极与漏极之间。
11.一种半导体结构，包含有：
基底，基底内包含有绝缘区域；
第一元件，位于该绝缘区域中，并且该第一元件沿着第一方向排列，其中该第一元件由氧化半导体材质所形成；
介电层覆盖于该第一元件上；以及
第二元件，位于该介电层上，并且沿着第二方向排列，其中该第二元件则作为晶体管结构的栅极使用。
12.根据权利要求11的半导体结构，其中构成该第一元件的该氧化半导体材质为铟镓锌氧化物。
13.根据权利要求12的半导体结构，其中该IGZO进一步包含沿C轴结晶IGZO。
14.根据权利要求11的半导体结构，其中该第二元件的材质包含多晶硅。
15.根据权利要求11的半导体结构，其中该第一元件的顶面高于该基底的顶面。
16.根据权利要求11的半导体结构，其中该介电层的材质包含氧化铝以及氧化镓。
17.根据权利要求11的半导体结构，其中该第二方向与该第一方向垂直。
18.根据权利要求11的半导体结构，其中该绝缘区域的顶面与该第一元件的顶面切齐。
19.根据权利要求11的半导体结构，其中部分该第一元件位于该半导体结构的源极与漏极之间。
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