CN100440540C - 晶体管结构及其制造方法和操作该晶体管的方法 - Google Patents

晶体管结构及其制造方法和操作该晶体管的方法 Download PDF

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CN100440540C
CN100440540C CNB038116782A CN03811678A CN100440540C CN 100440540 C CN100440540 C CN 100440540C CN B038116782 A CNB038116782 A CN B038116782A CN 03811678 A CN03811678 A CN 03811678A CN 100440540 C CN100440540 C CN 100440540C
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约翰·F·沃格三世
兰迪·L·霍夫曼
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Abstract

增强型场效应晶体管，其中至少一部分晶体管结构可以是基本透明的。该晶体管的一个变型包括沟道层，其包括选自ZnO、SnO2或者In2O3中的基本绝缘的、基本透明的材料。包括基本透明材料的栅绝缘层位于与沟道层相邻，由此限定了沟道层/栅绝缘层界面。该晶体管的第二变型包括沟道层，其包括选自基本绝缘的ZnO、SnO2或In2O3的基本透明的材料，该基本绝缘的ZnO、SnO2或In2O3是通过退火工艺产生的。还公开了包括该晶体管的器件和用于制造该晶体管的方法。

Description

晶体管结构及其制造方法和操作该晶体管的方法
优先权要求
本申请要求在2003年1月24日提交的美国专利申请No.10/350,819的优先权，其是在2002年11月27日提交的美国专利申请No.10/307,162的部分继续申请，而该申请要求在2002年5月21日提交的美国临时申请60/382,696的优先权。
技术领域
本发明涉及晶体管结构，诸如例如，透明晶体管。
背景技术
微电子业界和研究团体正在致力于制造在肉眼可见的电磁频谱部分是透明的电子器件(例如，二极管和晶体管)。由该器件构成的电路将提供用于革新或者改善消费者电子系统、汽车电子系统和军用电子系统的独特机遇。
例如，在膝上型电脑或者其他信息显示产品中广泛地使用了有源矩阵液晶显示器(AMLCD)。AMLCD显示器的操作需要每个图像或者显示元素(像素)具有与之相关的相应的薄膜晶体管(TFT)，用于选择或者寻址将要打开或关闭的像素。当前，AMLCD显示器使用的是可以淀积在玻璃衬底上的并且是不透明的(通常地，非晶硅、多晶硅或者连续晶粒硅是用于在玻璃上制造TFT的材料)晶体管材料。这样，由寻址电子器件占用的显示器玻璃部分不能被用于使光透射过显示器。因此，用于AMLCD寻址的透明晶体管的应用将通过允许更多的光透射过显示器来改善显示器的性能。
附图简述
将通过参考下列附图更加详细地描述某些实施例：
图1是此处公开的晶体管结构的第一实施例的剖面图；
图2是此处公开的晶体管结构的第二实施例的剖面图；
图3是此处公开的晶体管结构的第三实施例的剖面图；
图4是示出了图1所示晶体管结构的漏源电流(IDS)相对漏源电压(VDS)的曲线图，其是栅源电压(VGS)的函数(栅源电压从+40V(曲线顶)到+2V以2V的步长进行变化)；
图5示出了图1所示晶体管结构在三个多种漏源电压处的IDS-VGS特性曲线；
图6示出了图1所示晶体管结构使用透明薄膜电阻负载(R＝70MΩ)和VDD＝40V的供电电压时的反相传输特性曲线；
图7示出了通过图1所示晶体管结构的源极或漏极部分的光透射特性的图；
图8是此处公开的晶体管结构的第四实施例的剖面图；
图9是此处公开的晶体管结构的第五实施例的剖面图；
图10是此处公开的晶体管结构的第六实施例的剖面图；
图11是包括此处公开的晶体管结构的AMLCD的单元电路示例的示意图；
图12是包括此处公开的晶体管结构的动态随机存取存储器(DRAM)单元电路示例的示意图；
图13是包括此处公开的晶体管结构的逻辑反相器示例的示意图；
图14是包括此处公开的晶体管结构的反向放大器电路示例的示意图。
几个实施例的详细描述
为便于理解，下文详细描述了此处使用的术语：
“增强型晶体管”表示在零栅压时在源极和漏极之间存在相对于导通电流是可忽略的截止电流的晶体管。换言之，该晶体管器件是“常截止的”。相反地，耗尽型晶体管是“常导通的”，表示在零栅压时在源极和漏极之间流动的电流比大于基本可忽略的电流。
“栅极”通常指用于晶体管电路配置环境中的三端FET的绝缘栅端。
“基本绝缘”可以包括绝缘材料(例如，具有大于约1010Ω-cm的电阻率的材料)和半绝缘材料(例如，具有约103Ω-cm至1010Ω-cm的电阻率的材料)。
“基本透明”通常指在电磁频谱的可见光部分(和/或在某些变型中的红外光部分)中不吸收大量光的材料或者结构。
“垂直”指基本上与衬底的表面垂直。
前面的术语描述是仅是为帮助读者而提供的，而不应被解释为具有小于本领域的普通技术人员所理解的范围，或者其不应限制附属权利要求的范围。
此处公开的是增强型的场效应晶体管，其中晶体管结构的至少一部分是基本透明的。还公开了包括该晶体管的器件和用于制造该晶体管的方法。
该晶体管的一个变型包括沟道层，其包括选自ZnO、SnO2或者In2O3中的基本绝缘的、基本透明的材料。包括基本透明材料的栅绝缘层位于与沟道层相邻的位置上，由此限定了沟道层/栅绝缘层界面。该晶体管还包括能够将电子注入到沟道层中使之积累在沟道层/栅绝缘层界面的源极，以及能够从沟道层中抽取电子的漏极。
该晶体管的第二变型包括沟道层，其包括选自基本绝缘的ZnO、基本绝缘的SnO2或者基本绝缘的In2O3中的基本透明的材料，该基本绝缘的ZnO、基本绝缘的SnO2或者基本绝缘的In2O3是通过退火工艺生产的。栅绝缘层位于与沟道层相邻的位置上，并且包括基本透明的材料。该晶体管还包括源极、漏极和栅电极。
用于制造该晶体管的方法包括：提供栅绝缘层，将ZnO、SnO2或者In2O3淀积在栅绝缘层的至少部分表面上，和使ZnO、SnO2或者In2O3在氧化环境中在约300至约1000℃的温度下退火约1分钟至2小时。
该晶体管可以作为联接到至少一个显示元件的开关包括在光电显示器件中。另一公开的器件是基本透明的动态随机存取存储单元，其包括联接到该晶体管的基本透明的电容器。该晶体管的另一应用是在基本透明的反相器中，其中该晶体管联接到负载器件。
通常，晶体管结构包括衬底、栅电极、栅绝缘层、沟道层、源极和漏极。沟道层可以位于与栅绝缘层相邻的位置，由此沟道层的表面与栅绝缘层的表面相接近。沟道层表面和栅绝缘层表面的接触区域在此处被称为沟道层/栅绝缘层界面。在示例性的构造中，沟道层的绝缘材料与栅绝缘层的材料不同，并且沟道层/栅绝缘层界面限定了离散的材料边界。
该晶体管结构的实施例的特征是，沟道层/栅绝缘层界面限定了导电沟道，用于使电子从源极流向漏极。换言之，该晶体管可被归类为“表面沟道”或者“界面沟道”器件。施加的栅电压促使电子在沟道层/栅绝缘层界面区域积累。此外，施加的电压增强了从源极到沟道层/栅绝缘层界面的电子注入，并且增强了由漏极对其进行的电子抽取。
该晶体管结构的另一特征是，该沟道层和栅绝缘层的构造或者组合的所选实施例在电磁频谱的可见光部分上(和/或在某些变型中的红外光部分)呈现出至少约90％的光透射率，更特别地，具有至少约95％的透射率。取决于所需的晶体管最终应用，该结构的每一个额外部件(即，衬底、栅电极、源/漏端)可被选择为不透明的或者基本透明的。在某些实施例中，该晶体管结构整体可以在电磁频谱的可见光部分上(和/或在某些变型中的红外光部分)呈现出至少约50％的光透射率，更特别地是至少约70％的光透射率，而最特别的是至少约90％的光透射率。
此处公开的FET的进一步的特征是，其可以容易地作为薄膜晶体管(TFT)而被制造。例如，可以使用相对低的工艺温度(例如，不超过约800℃)，并且不需要离子注入工艺来设置沟道阈值电压和在该FET结构的某些变型中限定源极和漏极接触。该TFT典型地在结合光电器件使用时是非常有用的，如下文所详细描述的。
沟道层典型地由基本绝缘的材料制成，其也是基本透明的。由于沟道层由基本绝缘的材料制成，因此可用在沟道层的体块部分中固有的电子量是可忽略的。此外，基本绝缘的沟道层可以提供固有的电绝缘，用于多个器件共享连续的沟道层膜(具有限定每个器件的被构图的栅电极、源电极和漏电极)。该固有的器件绝缘意味着，由于呈现出来的沟道层/栅绝缘层处的电导率仅低于被构图的栅电极，因此沟道层膜的构图不是必需的。
用于该沟道层的说明性材料包括ZnO、SnO2和In2O3。绝缘的ZnO、SnO2和In2O3可以通过退火工艺生产，特定地是快速热退火(RTA)工艺制造。该绝缘的ZnO、SnO2和In2O3典型地呈现出具有小于约5eV的能带间隙。
例如，可以淀积ZnO层(例如通过溅射、化学气相淀积、旋涂、物理气相淀积、气相外延、分子束外延等等)并且随后使其在基本氧化的环境中在约300至约1000℃的温度下(特别是约700至约800℃)经历约1分钟至约2小时(更特别的是约1分钟至约1小时，在某些情况中是约1分钟至约5分钟)的退火工艺。尽管不受任何理论的约束，但是可以相信，该工艺将导致在ZnO层中并入更多的氧，由此降低了氧缺位浓度或者氧缺乏程度。ZnO中的氧缺位或者氧缺乏可以致使其是n型的并且是可导电的。在诸如氩的惰性气体环境中的高温(即，至少约700℃)退火也可以产生绝缘ZnO。尽管不受任何理论的约束，但是该较高温度的退火可以改善ZnO的结晶度，由此改善了电子输运特性。可以掺杂该绝缘ZnO，也可以不进行掺杂。如果进行了掺杂，则可以通过使用受主掺杂剂的置换掺杂来增加ZnO的电阻率，该受主掺杂剂诸如例如，N、Cu、Li、Na、K、Rb、P、As及其混合物。
相似地，可以淀积SnO2层(例如通过溅射、化学气相淀积、旋涂、物理气相淀积、气相外延、分子束外延等等)并且随后使其在基本氧化的环境中在约300至约1000℃的温度下(特别是约700至约900℃的温度下)经历约1分钟至约2小时(更特别的是约1分钟至约1小时，在某些情况中是约1分钟至约5分钟)的退火工艺。尽管不受任何理论的约束，但是可以相信，该工艺将导致在SnO2层中并入更多的氧，由此降低了氧缺位浓度或者氧缺乏程度。SnO2中的氧缺位或者氧缺乏可以致使其是n型的并且是可导电的。诸如氩的惰性气体环境中的高温(即，大于约700℃)退火也可以产生绝缘SnO2。尽管不受任何理论的约束，但是该较高温度的退火可以改善SnO2的结晶度，由此改善了电子输运特性。可以通过使用受主掺杂剂的置换掺杂来增加SnO2的电阻率，该受主掺杂剂诸如例如，Al、In、Ga、Bi、B、La、Sc、Y、Lu、Er、Ho、N、P、As及其混合物。
同样相似地，可以淀积In2O3层(例如通过溅射、化学气相淀积、旋涂、物理气相淀积、气相外延、分子束外延等等)并且随后使其在基本氧化的环境中在约300至约1000℃的温度下(特别是约700至约900℃的温度下)经历约1分钟至约2小时(更特别的是约1分钟至约1小时，在某些情况中是约1分钟至约5分钟)的退火工艺。尽管不受任何理论的约束，但是可以相信，该工艺将导致在In2O3层中并入更多的氧，由此降低了氧缺位浓度或者氧缺乏程度。In2O3中的氧缺位或者氧缺乏可以致使其是n型的并且是可导电的。诸如氩的惰性气体环境中的高温(即，大于约700℃)退火也可以产生绝缘In2O3。尽管不受任何理论的约束，但是该较高温度的退火可以改善In2O3的结晶度，由此改善了电子输运特性。可以通过使用受主掺杂剂的置换掺杂来增加In2O3的电阻率，该受主掺杂剂诸如例如，Be、Mg、Ca、Sr、Ba、N、P、As、Zn、Cd及其混合物。
根据特定的实施例，ZnO、SnO2或者In2O3层可以在包括至少一种溅射气体和至少一种膜调整气体的环境中通过溅射进行淀积。该膜调整气体可以是任何能够通过在原子或者亚原子水平上并入到膜中来增加膜电阻率的气体。例如，膜调整气体可以是其自身分子、原子或者离子并入到膜中使得如上文所述占据了膜中的氧缺位或者缺陷的氧化气体。另一种膜调整气体可以是其自身分子、原子或者离子并入到膜中使得其增加了膜电阻率的掺杂剂气体。说明性的溅射气体包括Ar、Ne及其混合物。说明性的氧化气体包括O2、N2O及其混合物。说明性的掺杂剂气体包括N2、NH3和其他包括上文列出的掺杂剂类型的气体。在溅射环境中的气体浓度可以取决于所需的膜特性而进行变化。例如，氧化气体的浓度可以在约0至约50的体积百分比的范围内变化。掺杂剂气体的浓度可以在约0至约50的体积百分比的范围内变化。溅射气体的浓度可以在约0至约100的体积百分比的范围内变化。溅射条件也可以取决于所需的膜特性而进行变化。例如，温度可以从约室温至600℃的范围内变化，并且压力可以在约1mTorr至约50mTorr的范围中变化。在特定的示例中，可以在包括80体积百分比的Ar、10体积百分比的N2和10体积百分比的O2的环境中，通过溅射来淀积未掺杂的ZnO靶。
沟道层的厚度可以变化，并且可以根据特定的示例，在约10至约500nm的范围中变化。沟道长度也可以变化，并且可以根据特定的示例，在约1,000至约100,000nm的范围中变化。
栅绝缘层可以由任何呈现出栅绝缘体所需的绝缘特性的材料制成，特别是基本透明的材料。栅绝缘体材料典型地呈现出大于约5eV的能带间隙。说明性的材料包括基本透明的材料，诸如铝钛氧化物(Al2O3/TiO2)、Al2O3、MgO、SiO2、氮化硅和氮氧化硅。基本透明材料的一个特殊的示例是通过原子层淀积生长的铝钛氧化物。栅绝缘层的厚度可以变化，并且可以根据特定的示例，在约10至约300nm的范围中变化。可以通过诸如化学气相淀积、溅射、原子层淀积或者蒸发的技术将栅绝缘层引入到该结构中。
源/漏端是指FET的极端，在电场的影响下在该极端之间出现传导。设计者通常基于FET在电路中操作时施加到极端的电压来将特定的源/漏端指定为“源极”或者“漏极”。源极和漏极可以由任何适当的导电材料制成，诸如n型材料。源极和漏极材料可被选择为不透明的材料或者基本透明的材料。说明性的材料包括透明的n型导体，诸如氧化铟锡(ITO)、ZnO、SnO2或者In2O3，或者包括不透明的材料，诸如Al、Cu、Au、Pt、W、Ni或者Ti。对于源极和漏极特别有用的材料是那些能够向沟道层绝缘材料注入(和抽取)电子的材料。该电子注入材料的实例包括氧化铟锡、LaB6和ZnO:Al。
可以通过诸如化学气相淀积、溅射、蒸发和/或通过扩散或离子注入掺杂沟道层材料的技术，将源极和漏极引入到该结构中。可以制造源极和漏极使得它们在几何上是几何对称的或者是不对称的。
栅电极可以由任何适当的传导材料制成。栅电极材料可被选择为不透明的材料或者基本透明的材料。说明性的栅电极材料包括透明的n型导体，诸如氧化铟锡(ITO)、ZnO、SnO2或者In2O3，或者包括不透明的材料，诸如Al、Cu、Au、Pt、W、Ni或者Ti。栅电极的厚度可以变化，并且可以根据特定的示例，在约50至约1000nm的范围中变化。可以通过诸如化学气相淀积、溅射、蒸发和/或掺杂的技术将栅电极引入到该结构中。
如此处所使用的，“衬底”是指作为基础工件的物理物体，其通过多种工艺操作被转化为所需的微电子构造。衬底还可以指晶片。晶片可以由半导体材料、非半导体材料或者半导体材料和非半导体材料的组合制成。衬底可以由任何适当的材料制成。衬底材料可被选择为不透明的材料或者基本透明的材料。说明性的衬底材料包括玻璃和硅。衬底的厚度可以变化，并且可以根据特定的示例，在约100μm至约1cm的范围中变化。
可以以任何方式提供对栅电极、源极、漏极和衬底的电接触。例如，可以使用金属线、迹线、导线、互连、导体、信号路径和信号传播介质来提供所需的电气连接。上文列出的项通常是可互换的，并且按照从特殊到一般的顺序排列。通常是铝(Al)、铜(Cu)、或者Al和Cu的合金的金属线是提供用于联接或者互连电路的信号路径的导体。还可以使用除了金属以外的导体。
说明性的n沟道晶体管的操作涉及，向栅电极施加正电压，将源极接地，和向漏极施加正电压。例如，在操作期间向栅电极和漏极施加约5至约40V的电压。阈值电压可以在约1至约20V的范围中变化。电子从源极沿在沟道层/栅绝缘层界面处产生的导电沟道通过漏极流出晶体管。电子在界面处的有效迁移率可以取决于特定的结构而变化，但是可以在一定的范围中变化，例如约0.05至约20cm2V-1s-1。由于该晶体管是增强型晶体管，因此简单地移除施加在栅电极上的正电压可以使晶体管截止。
此处公开的晶体管结构可被用于制造芯片、集成电路、单片器件，半导体器件和微电子器件。一个微电子器件的示例是光电器件。说明性的光电器件是有源矩阵液晶显示器(AMLCD)。
一个示例器件是光电显示器件，其包括具有电极和淀积在电极之间的光电材料的元件。透明晶体管的连接电极可以连接到显示元件的电极，而开关元件的显示元件至少在一部分上相互重叠。这里，光电显示元件被理解为其光学特性在电气量(诸如电流和电压)的作用下发生改变的显示元件，诸如例如，通常被称为液晶显示器(LCD)的元件。此处详细描述的透明晶体管作为以高频来开关显示元件来说是足够快的，使得可以使用透明晶体管作为液晶显示器中的开关元件。该显示元件在电气方面可以被当成电容器，其通过伴随的透明晶体管而进行充电和放电。光电显示器件可以包括许多显示元件，每一个显示元件都具有其自己的透明晶体管(例如，排列在矩阵中)。可以如，例如，Kim，“Thin-Film-Transistor Device Design”，Information Display2/02，p.26(2002)中所描述的，为LCD器件排列该透明晶体管。
在图11中示出了AMLCD单元电路的一个特定示例。该AMLCD单元电路包括如此处描述的晶体管60和与之电气联接的LCD像素61。晶体管60和LCD像素61一起形成了晶体管/像素单元62。在所示配置中，晶体管60通过漏电极电气联接到LCD像素61。晶体管60的栅电极电气联接到接收用于晶体管60的开/关输入的行或者控制线63。晶体管60的源电极电气联接到接收用于控制LCD像素61的信号的列或者数据线64。
可以使用此处示出的晶体管结构的微电子器件的其他示例包括反相器、模拟放大器和单管动态随机存取存储(DRAM)单元以及相似的器件。
例如，透明的增强型晶体管，在其源极连接至透明电容器的一个极端，而电容器的另一极端接地时，构成了透明的单管动态随机存取存储(DRAM)单元。在该DRAM单元中，信息作为电容器上的电荷存储，该增强型晶体管用作存取晶体管，其控制电容器的电荷状态。通常在该DRAM单元中，可忽略的电容器电荷量和伴随的小的电容器电压表示逻辑“0”。相反地，通过对电容器充电，由此增加电容器电压直到其达到供电电压，获得了逻辑“1”。
此处描述的完整的DRAM单元或者其一部分是透明的。可以使用多种技术来完成制造透明电容器并且将其连接至透明晶体管以实现DRAM单元。特定地，通过将使用诸如Al2O3或者SiO2材料将透明绝缘层夹在两个使用诸如氧化铟锡、ZnO或者SnO2材料的透明导体之间，可以构建透明电容器。
在图12中示出了DRAM单元电路的一个特定的示例。该DRAM单元电路包括如此处描述的晶体管70和与之电气联接的存储电容器71。晶体管70和存储电容器71一起形成了晶体管/电容器单元72。在所示配置中，晶体管70通过漏电极电气联接到存储电容器71。晶体管70的栅电极电气联接到接收用于晶体管70的开/关输入的行或者写入线73。晶体管70的源电极电气联接到接收用于控制存储电容器71所存储信息的信号的列或者数据线74。
图1至3和图8至10中示出了特定的晶体管结构的说明性示例。下文特定的示例是用于说明性的目的，并且不应被理解为限制附属权利要求的范围。在图1至3和图8至10中，除非特别说明，相似的参考数字表示相似的元件。
图1
示出了TFT结构1，其被制造在1英寸×1英寸厚的复合衬底上。该平台包括200nm厚的玻璃衬底2、涂布在衬底2上的氧化铟锡(ITO)栅电极3和200nm厚的铝钛氧化物绝缘层4。
ZnO沟道和ITO源/漏电极膜通过在10-4Torr的Ar/O2(80％/20％)中的离子束溅射进行淀积；衬底在淀积过程中未加热。使用阴影掩模来限定ZnO沟道层5(100nm厚)、ITO源电极6(300nm厚)和ITO漏电极7(300nm厚)。得到的结构限定了沟道层/栅绝缘层界面8。紧接在用于去除从暴露表面吸收杂质的ZnO和ITO淀积之前，在Ar中的300℃快速热退火(RTA)获得了膜质量的明显改善(特别用于ITO膜)。在淀积ZnO层之后，使用RTA(典型地在O2或者Ar中，600至800℃)增加ZnO沟道的电阻率并且改善沟道层/栅绝缘层界面8的电气质量。在ITO源/漏电极淀积之后，使用O2中300℃的RTA增加ITO层的透明度。在晶体管结构1中，将源/漏电极6和7安置在沟道层5的顶表面(在垂直视角上)，并且将栅电极5和沟道层5分布安置在栅绝缘层4的相对表面上。因此，结构1允许在ITO源/漏电极6和7的淀积和处理之前，进行ZnO沟道层5的高温处理。如下文所述评估了TFT结构1的某些电气和物理特性，并且在图4至7中进行了说明。
通过参考图4，获得了n沟道增强型行为，这是基于这一事实而声明的，即需要超过约～15V(阈值)的正栅压来获得可测量的漏源电流。该IDS-VDS曲线呈现出了原型FET的特征；特别重要的是，这些曲线在大的漏电压处是平坦的(即，它们呈现“硬”饱和)。所使用的漏电压和栅电压相比于传统的FET是相当大的；通过简单地减小栅绝缘体的厚度，可以将栅电压和漏电压减小到典型FET操作所期望的范围(即～5至10V)。在TFT结构1中，由于被优化的用于电致发光显示应用，绝缘体厚度是～200nm；如果将另外的相同绝缘体重新调节为20nm的厚度，则栅电压和漏电压将以近似10的系数比例减小。
结构1当前的IDS相当小(即图4中IDS(max)是约6μA)。在许多应用中更大的IDS可能是需要的。IDS的幅度由两个因素决定。一个是沟道电子的有效迁移率μeff(对于TFT结构1为约0.05至0.2cm2V- 1s-1)。工艺/器件优化将导致μeff以系数比例约2至100进行增长，这将导致相应的IDS的增加。第二个因素是纵横比。TFT结构1的纵横比(栅极的物理宽度Z除以栅极的长度L)是约2(其中Z＝2L＝6000μm)。较大的纵横比将导致较大的电流IDS。
图5示出了TFT结构1在三个不同漏电压下的IDS-VGS特性。该图示出了在晶体管用作开关时，在“导通”和“截止”电流之间存在系数为105至106的差异。
图6示出了TFT结构1在用作反相器时的传输特性。ZnO透明薄膜电阻(R＝70MΩ)用作反相器无源负载，其中供电电压VDD＝40V。从该曲线可以清楚地证明在15和30V之间有约15V的逻辑摆幅。这表明此处描述的透明TFT可以用作透明反相器。在其最简单的实现方案中，逻辑反相器包括两个组成部分；联接到负载器件的晶体管。该负载器件可以是电阻器，如本示例中所使用的。可替换地，耗尽型或者增强型晶体管也可以用作负载器件，典型地提供更好的性能。逻辑反相器的基本特性是它执行逻辑非运算，其中逻辑0(1)输入产生逻辑1(0)输出。由于反相器是用于实现透明数字电子电路的最基本的构成模块，所以如此处所述，成功的实现透明逻辑反相器是意义重大的。通过减小绝缘体厚度、减小物理尺寸和增加电流驱动能力(增加纵横比和有效迁移率)而进行的透明薄膜晶体管的优化将导致用于反相器操作的供电电压的明显降低。
在图13中示出了逻辑反相器电路的一个特定示例。该逻辑反相器电路包括如此处描述的晶体管80。晶体管80的栅电极电气联接到电压输入端(Vin)，晶体管80的源电极电气联接到地，并且晶体管80的漏电极电气联接到负载81和电源(VDD)。负载81可以是透明薄膜电阻或者透明薄膜晶体管。通过Vin使晶体管80导通或者截止来控制电路的电压输出(Vout)。
透明晶体管还可以用于放大器应用中。例如，上文所述的反相器结构还可以用作简单的模拟反向放大器。通过在输入端施加适当的DC偏置，小的输入信号(叠加在DC偏置上)由反相器的传输特性进行放大。除了该简单的放大器配置，这些晶体管可以直接应用到任意的放大器配置中，但是由于这些器件低的迁移率，其最大操作频率极限相对要低。
在图14中示出了反向放大器电路的一个特定示例。该反向放大器电路包括如此处描述的晶体管90。晶体管90的栅电极电气联接到电压输入信号(Vin)和DC偏置(Vbias)。晶体管90的源电极电气联接到地，并且晶体管90的漏电极电气联接到负载91和电源(VDD)。负载91可以是透明薄膜电阻或者透明薄膜晶体管。
图7示出了TFT结构1通过源极6或者漏极7的光透射率(这里未示出的通过沟道的光透射率高于通过源极或者漏极的光透射率)。在电磁频谱的可见光部分(450-700nm)的平均透射率是约90％(通过沟道是约95％)。在视觉上，该透明TFT结构基本上是看不见的；在靠近观察时，玻璃衬底的略微染色是明显的。
图2
在图2所示的另一透明TFT结构10的版本中，通过选择性地在ZnO沟道层13(100nm厚)的末端掺杂In(或者任何适当的n型掺杂剂)，制造了源电极11(100nm厚)和漏电极12(100nm厚)。通过在淀积ZnO沟道膜之前，使用源/漏极阴影掩模由离子束溅射来淀积薄(约5nm)的ITO层，完成了这一操作。执行随后的高温(～600至800℃)退火步骤，用以扩散掺杂ZnO，由此形成了n型掺杂的源/漏区域11和12。扩散掺杂RTA还可用作用于ZnO的氧化RTA。ITO接触可以安置在源和漏区域上，用以提供更好的电气接触。衬底2、栅电极3、栅绝缘层4和沟道层/栅绝缘层界面8与图1中的相同。
图3
在TFT结构的第三变型20中，在形成ZnO沟道层23(100nm厚)之前，淀积ITO源电极21(300nm厚)和ITO漏电极22(300nm厚)。随后ZnO沟道层23保形淀积在ITO源/漏电极21和22上。在ZnO的淀积之后，执行700℃的Ar退火，随后执行300℃的氧退火。衬底2、栅电极3、栅绝缘层4和沟道层/栅绝缘层界面8与图1中的相同。
图8
图8示出了TFT结构的第四变型30。该TFT结构30包括玻璃衬底2，在其上安置有源电极35和漏电极36。所提供的沟道结构37包括位于源电极35和漏电极36之间并且与玻璃衬底2相邻的体块部分38。沟道结构37还包括界面部分39，其与体块部分38是一体的，并且分别置于栅绝缘层34同源电极35和漏电极36之间。界面部分39可以与每个源电极35或漏电极36的全部重叠，或者仅与其部分重叠。界面部分39和栅绝缘层34形成沟道层/栅绝缘层界面31，其限定了用于电子从源极流向漏极的导电沟道。栅电极33安置在栅绝缘层34的顶表面上(在垂直视角上)。换言之，栅电极33和沟道结构37提供在栅绝缘层34的相对表面上。
例如，通过淀积和构图限定了源电极35和漏电极36的膜，可以制造该TFT结构30。例如，可以在玻璃衬底2上溅射
Figure C0381167800211
的ITO源/漏电极膜。通过阴影掩蔽或者光刻方法可以完成源极和漏极的构图。可以选择对源/漏电极膜进行退火。然后沟道结构37可以淀积和构图在源电极35、漏电极36和玻璃衬底2上。例如，可以溅射淀积
Figure C0381167800212
的ZnO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对该ZnO膜进行退火。随后，栅绝缘层34可以淀积和构图在沟道结构37上。例如，可以溅射淀积
Figure C0381167800213
的Al2O3膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以形成通过栅绝缘层34的过孔，用以电气连接至源电极35和漏电极36。可以选择对该Al2O3膜进行退火。然后栅电极33可以淀积和构图在栅绝缘层34上。例如，可以溅射淀积的ITO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对该ITO膜进行退火。
图9
图9示出了TFT结构的第五变型40。该TFT结构40包括玻璃衬底2，在其上安置了沟道层41。在与相邻于玻璃衬底2的表面相对的沟道层41的表面上提供有源电极43和漏电极42。栅绝缘层44安置在沟道层41、源电极43和漏电极42上。栅电极45安置在栅绝缘层44的顶表面上(在垂直视角上)。换言之，栅电极45和沟道层41提供在栅绝缘层44的相对表面上。所得到的结构定义限定了沟道层/栅绝缘层界面46。
例如，通过淀积和构图限定了沟道层41的膜，可以制造该TFT结构40。例如，可以溅射淀积
Figure C0381167800221
的ZnO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对ZnO膜进行退火。然后可以淀积和构图源电极43和漏电极42。例如，可以溅射淀积
Figure C0381167800222
的ITO源/漏电极膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对该源/漏电极膜进行退火。随后，栅绝缘层44可以淀积和构图在沟道层41、源电极43和漏电极42上。例如，可以溅射淀积
Figure C0381167800223
的Al2O3膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以形成通过栅绝缘层44的过孔，用以电气连接至源电极43和漏电极42。可以选择对该Al2O3膜进行退火。然后栅电极45可以淀积和构图在栅绝缘层44上。例如，可以溅射淀积
Figure C0381167800224
的ITO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对该ITO膜进行退火。
图10
图10示出了TFT结构的第六变型50。该TFT结构50包括玻璃衬底2，在其上安置了沟道层51、源电极52和漏电极53。在沟道层51、源电极52和漏电极53上淀积了栅绝缘层54。栅电极55安置在栅绝缘层54的顶表面上(在垂直视角上)。换言之，栅电极55和沟道层51提供在栅绝缘层54的相对表面上。所得到的结构限定了沟道层/栅绝缘层界面56。
例如，通过淀积和构图限定了沟道层51的膜，可以制造该TFT结构50。例如，可以溅射淀积
Figure C0381167800231
的ZnO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对ZnO膜进行退火。然后可以通过选择性地在沟道层51的末端掺杂In、Al、Ga或者任何其他适当的n型掺杂剂，制造源电极52和漏电极53。随后，栅绝缘层54以淀积和构图在沟道层51、源电极52和漏电极53上。例如，可以溅射淀积
Figure C0381167800232
的Al2O3膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以形成通过栅绝缘层54的过孔，用以电气连接至源电极52和漏电极53。可以选择对该Al2O3膜进行退火。然后栅电极55可以淀积和构图在栅绝缘层54上。例如，可以溅射淀积
Figure C0381167800233
的ITO膜，并且然后通过阴影掩蔽或者光刻方法进行构图。可以选择对该ITO膜进行退火。
通过参考几个实施例，说明和描述了所公开的器件和方法的原理，应当认识到，在不偏离这些原理的前提下，可以在配置和细节上对这些器件和方法进行修改。

Claims (33)

1.一种场效应晶体管，包括：
沟道层，其包括选自ZnO、SnO2或者In2O3中的绝缘的、透明的材料，该ZnO、SnO2或者In2O3是通过退火工艺生产的；
栅绝缘层，其包括透明的材料，并且位于与沟道层相邻，由此限定了沟道层/栅绝缘层界面；
源极，其能够将电子注入到沟道层中，用于在沟道层/栅绝缘层界面处进行积累；和
漏极，其能够从沟道层中抽取电子；
其中该场效应晶体管被配置用于增强型操作。
2.权利要求1的晶体管，进一步包括栅电极和衬底，并且其中源极、漏极、栅电极和衬底中每一个均由透明的材料制成。
3.权利要求1的晶体管，进一步包括栅电极和衬底，并且其中源极、漏极、栅电极和衬底中的至少一个由不透明的材料制成。
4.权利要求1的晶体管，其中栅绝缘层包括Al2O3/TiO2。
5.权利要求2的晶体管，其中栅绝缘层包括Al2O3/TiO2或者Al2O3；源极、漏极和栅电极中每一个均包括氧化铟锡；并且衬底包括玻璃。
6.权利要求1的晶体管，其中场效应晶体管在电磁频谱的可见光部分上呈现出通过该场效应晶体管的至少90％的光透射率。
7.权利要求1的晶体管，其中沟道层不是离子注入的。
8.权利要求1的晶体管，其中包括ZnO的沟道层是气相淀积的。
9.权利要求1的晶体管，其中，所述场效应晶体管整体在电磁频谱的可见光部分上呈现出至少70％的光透射率。
10.一种场效应晶体管，包括：
沟道层，其包括选自绝缘的ZnO、绝缘的SnO2或者绝缘的In2O3中的透明的材料，该绝缘的ZnO、绝缘的SnO2或者绝缘的In2O3是通过退火工艺生产的；
栅绝缘层，其位于与沟道层相邻；
源极；
漏极；和
栅电极；
其中该场效应晶体管被配置用于增强型操作。
11.权利要求10的晶体管，其中沟道层包括绝缘的ZnO，其是通过使ZnO膜在氧化或惰性的环境中在300至1200℃的温度下退火1分钟至2小时而制造的。
12.权利要求10的晶体管，其中沟道层包括未掺杂的ZnO。
13.权利要求10的晶体管，其中经退火的ZnO、SnO2或者In2O3的氧缺位浓度低于未退火的ZnO、SnO2或者In2O3的氧缺位浓度。
14.权利要求10的晶体管，其中，气相淀积ZnO，并且使所得到的ZnO层经历退火。
15.一种用于操作场效应晶体管的方法，包括：
提供场效应晶体管，其包括(i)沟道层，该沟道层包括选自ZnO、SnO2或者In2O3中的绝缘的、透明的材料；(ii)栅绝缘层，该栅绝缘层位于与沟道层相邻，由此限定了沟道层/栅绝缘层界面；(iii)源极；(iv)漏极；和(v)栅电极，该ZnO、SnO2或者In2O3是通过退火工艺生产的；和
向栅电极施加正电压，用以引发在沟道层/栅绝缘层界面处的电子流动，其中在不施加正电压时不会有电流产生。
16.权利要求15的方法，其中在沟道层/栅绝缘层界面处流动的电子具有0.05cm2V-1s-1至20cm2V-1s-1的有效迁移率。
17.权利要求15的方法，其中5至40V的电压施加到栅电极和漏极。
18.一种用于制造增强型的场效应晶体管的方法，包括：
将ZnO、SnO2或者In2O3淀积在栅绝缘层表面的至少一部分上；和
使ZnO、SnO2或者In2O3在氧化或者惰性环境中在300至1000℃的温度下退火1分钟至2小时。
19.权利要求18的方法，其中淀积ZnO。
20.权利要求19的方法，进一步包括，将受主掺杂剂引入到ZnO中。
21.权利要求19的方法，其中，气相淀积ZnO。
22.权利要求18的方法，其中栅绝缘层包括透明的材料。
23.权利要求18的方法，其中淀积ZnO、SnO2或者In2O3包括，在包括至少一种溅射气体和至少一种能够调整由ZnO、SnO2或者In2O3形成的膜的气体的环境中，溅射淀积ZnO、SnO2或者In2O3。
24.权利要求23的方法，其中膜调整气体包括至少一种选自氧化气体或者掺杂剂气体中的气体。
25.权利要求24的方法，其中氧化气体包括氧，并且掺杂剂气体包括氮。
26.权利要求18的方法，其中，所述场效应晶体管整体在电磁频谱的可见光部分上呈现出至少70％的光透射率。
27.一种用于制造增强型的场效应晶体管的方法，包括：
将ZnO、SnO2或者In2O3淀积在栅绝缘层表面的至少一部分上；和
使所淀积的ZnO、SnO2或者In2O3进行退火，以形成透明的、绝缘的沟道层。
28.权利要求27的方法，进一步包括：
使ZnO、SnO2或者In2O3在氧化或者惰性环境中在300至1000℃的温度下退火1分钟至2小时。
29.一种光电显示器件，包括至少一个联接到开关的显示元件，该开关包括根据权利要求1或11的任何一个的增强型场效应晶体管。
30.一种透明的动态随机存取存储单元，包括透明的电容器，其联接到根据权利要求1或11的任何一个的增强型场效应晶体管。
31.一种透明的逻辑反相器，包括负载器件，其联接到根据权利要求1或10的任何一个的增强型场效应晶体管。
32.一种放大器，包括根据权利要求1或10的任何一个的增强型场效应晶体管。
33.一种微电子结构，包括：
连续的沟道层膜，其包括选自ZnO、SnO2或者In2O3的绝缘的材料，该ZnO、SnO2或者In2O3是通过退火工艺生产的；以及
多个已构图的栅绝缘层、源极和漏极，其被配置成使得每个栅绝缘层、源极和漏极连同连续的沟道层膜一起形成离散的电气器件，其中栅绝缘层位于与连续的沟道层膜相邻，由此限定了沟道层/栅绝缘层界面。
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CN1656618A (zh) 2005-08-17
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US20080108198A1 (en) 2008-05-08
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US7339187B2 (en) 2008-03-04
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