CN104716198B - 薄膜晶体管及其制造方法、显示装置 - Google Patents

薄膜晶体管及其制造方法、显示装置 Download PDF

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CN104716198B
CN104716198B CN201510134375.1A CN201510134375A CN104716198B CN 104716198 B CN104716198 B CN 104716198B CN 201510134375 A CN201510134375 A CN 201510134375A CN 104716198 B CN104716198 B CN 104716198B
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layer
drain electrode
source electrode
tft
thin film
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CN104716198A (zh
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王龙彦
李永谦
曹昆
李全虎
尹静文
张保侠
盖翠丽
吴仲远
王刚
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种薄膜晶体管及其制造方法、显示装置,涉及显示领域,能够解决有源层在源极和漏极的刻蚀工序中易被腐蚀的问题,从而能够采用背沟道刻蚀工艺制备薄膜晶体管器件,减少薄膜晶体管制造的工艺次数,节省制造成本。本发明的薄膜晶体管包括:栅极、有源层、源极和漏极,所述源极和漏极由至少两种材料形成,所述源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且,该刻蚀液对所述有源层不腐蚀。

Description

薄膜晶体管及其制造方法、显示装置
技术领域
本发明涉及显示领域,尤其涉及一种薄膜晶体管及其制造方法、显示装置。
背景技术
以金属氧化物为代表的化合物半导体为有源层材料的薄膜晶体管TFT(Thin FilmTransistor)具有迁移率高、制作工艺简单、大面积均匀性好、制造成本低等优点,被认为是驱动有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode,AMOLED)显示最具潜力的器件。因此近年来化合物半导体TFT备受业界关注,并逐渐应用于AMOLED显示面板当中。
在TFT的制造技术中,背沟道刻蚀(Back Channel Etch,BCE)工艺是非晶硅TFT常见的工艺,只需四次光刻即可形成TFT:第一道光刻工艺形成TFT的栅极,第二道光刻工艺形成TFT的半导体层,第三道光刻工艺形成TFT的源极和漏极,第四道光刻工艺形成TFT的钝化层过孔。因BCE工艺需要掩膜版数目(四块掩膜版)和工艺步骤较少而被现有非晶硅(a-Si)TFT面板生产线广泛采用。以金属氧化物TFT为例,理论上,化合物半导体TFT的制造工艺应该与非晶硅TFT相同,但现有的技术中,无论是干法刻蚀还是湿法刻蚀都会对化学稳定性较脆弱的化合物半导体有源层造成损伤而最终影响器件性能,即BCE工艺在形成源极和漏极的同时会损伤化合物半导体有源层,因此,目前BCE工艺不能直接用于制备化合物半导体薄膜晶体管,需要增加用以保护化合物半导体有源层的刻蚀阻挡层的制备过程,但增加刻蚀阻挡层后,导致制备工艺所需的掩膜版数目增多,工艺变得复杂、成本随之提高。
发明内容
本发明提供一种薄膜晶体管及其制造方法、显示装置,用以实现一种新的背沟道TFT结构,简化基于化合物半导体等材料制作的TFT的制作工艺,降低制造成本。
为达到上述目的,本发明的实施例采用如下技术方案:
一种薄膜晶体管,包括:栅极、有源层、源极和漏极,所述源极和漏极由至少两种材料形成,所述源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且,该刻蚀液对所述有源层不腐蚀。
可选地,所述源极和漏极由两种材料形成,所述源极和漏极包括两种材料形成的复合导电膜层,其中:所述两种材料中的其中一种材料形成的第一膜层,所述两种材料中的另一种材料形成的第二膜层;所述第二膜层覆盖于所述第一膜层之上,所述第二膜层上设置有便于所述刻蚀液渗透的小孔。
可选地,所述两种材料包括铝和氧化铟锡;所述刻蚀液为碱性溶液。
可选地,所述碱性溶液为氢氧化钠溶液,或者氢氧化钾溶液,或者四甲基氢氧化铵溶液。
可选地,所述有源层包括不受所述碱性溶液腐蚀的化合物半导体材料。
可选地,所述化合物半导体材料包括铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。
可选地,设置在所述源极和漏极之上,在后续工序中为所述源极和漏极提供防护的金属层,所述金属层具有与所述源极和漏极相同的图形。
本实施例还提供一种显示装置,包括:上述的任意薄膜晶体管。
本实施例还提供一种薄膜晶体管的制造方法,包括以下步骤:
提供衬底基板;
通过构图工艺形成栅极和栅绝缘层;
形成有源层和源极、漏极,所述源极和漏极包括至少两种材料,所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且所述刻蚀液对所述有源层不腐蚀。
可选地,所述源极和漏极采用两种材料形成的复合导电膜层。
可选地,所述复合导电膜层的制作过程包括:
形成第一材料层;
采用溅射的方法,在所述第一材料层上制备第二材料层。
可选地,所述在栅绝缘层上形成有源层和源极、漏极,包括:形成复合导电膜层;还包括:
利用构图工艺对所述复合导电膜层进行掩膜曝光及刻蚀,其中所述复合导电膜层中的两种材料在对应的刻蚀液中发生电池反应从而被刻蚀。
可选地,所述形成有源层和源极、漏极,包括:
在所述栅绝缘层上沉积化合物半导体薄膜和复合导电膜层;
利用双色调掩膜工艺对所述化合物半导体薄膜和复合导电膜层进行构图,得到化合物半导体有源层和源极、漏极。
可选地,所述至少两种材料包括铝和氧化铟锡;所述刻蚀液为碱性溶液。
可选地,在所述形成复合导电膜层的步骤之后,及在所述利用构图工艺对所述复合导电膜层进行掩膜曝光及刻蚀的步骤之前,还包括:
在所述复合导电膜层上方形成保护层;
利用刻蚀工艺对所述保护层进行构图,使得所述源极和漏极对应区域的保护层被保留。本发明实施例提供的薄膜晶体管及其制造方法、显示装置,对薄膜晶体管的源极和漏极的形成材料及使用的刻蚀液作出限定:源极和漏极采用至少两种材料形成,并且源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且,该刻蚀液对所述有源层不腐蚀。基于本发明实施例提供的方案,能够实现一种新的背沟道TFT结构,尤其适用于以氧化物TFT为例的化合物半导体TFT中,可以解决氧化物薄膜晶体管等TFT结构中的有源层在源极和漏极的刻蚀工序中易被腐蚀的问题,无需增加刻蚀阻挡层,薄膜晶体管可直接采用背沟道刻蚀工艺制备,因而可以减少构图工艺次数,降低制造成本。并且,形成源极和漏极时电池反应可以将两层材料同时去除,不用单独分开刻蚀各层材料,且电池反应刻蚀速度快,节省刻蚀时间。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的源极和漏极的复合膜层结构;
图2为本发明实施例提供的薄膜晶体管的截面结构示意图;
图3(a)~图3(d)为本发明实施例提供的薄膜晶体管的制备过程示意图一;
图4(a)~图4(d)为本发明实施例提供的薄膜晶体管的制备过程示意图二。
附图标记
101-第一膜层,102-第二膜层,20-基板,21-栅极,22-栅绝缘层,23-有源层,241-源极,242-漏极,25-钝化层。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。
实施例
本发明实施例提供一种薄膜晶体管,该薄膜晶体管包括:栅极、有源层、源极和漏极,所述源极和漏极由至少两种材料形成,所述源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且,该刻蚀液对所述有源层不腐蚀。
针对现有TFT的有源层易被源极和漏极形成工序中使用的刻蚀液腐蚀的问题,本实施例采用全新解决思路:将薄膜晶体管中源极和漏极的材料选择为可在某一电解液中发生电池反应的材料,同时将发生电池反应对应的电解液,在源极和漏极的形成工序中当成刻蚀液使用,且电解液作为刻蚀液使用时对薄膜晶体管的有源层不腐蚀。可以理解的是,上述刻蚀液对有源层不腐蚀的说法,在具体实施实施时还包括刻蚀液对有源层腐蚀速度非常慢,近似不腐蚀的情况。
另外,源极和漏极的形成材料一般应至少包括两种,其中一种发生电池正极化学反应,另一种发生电池负极化学反应,还可以包括其它对电池反应具有辅助功能的组分,或其他与电池反应不相干的组分。
需要说明的是,“该刻蚀液对所述有源层不腐蚀”是指有源层在所述刻蚀液中(或者在制作源极和漏极的工况条件下),不会由于与其所处环境介质发生化学或者电化学作用等而引起的变质和破坏,有源层的膜层的物理、化学性质也不会发生改变,或者即便发生改变但这种改变对TFT的影响小到可以忽略,其中的“腐蚀”也包括上述因素与力学因素或者生物因素的共同作用。
上述源极和漏极的形成材料包括至少两种,但具体成膜方式不做限定,可以上述的至少两种材料形成混合材料薄膜;也可以多层膜叠加,每一层膜为一种材料形成。无论如何只要保证在源极和漏极的形成工序中,用以形成源极和漏极的膜层材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且,该刻蚀液对有源层不腐蚀,即可使得原本需要增加刻蚀阻挡层形成工序的薄膜晶体管,可以直接采用背沟道刻蚀工艺制备,不需要增加刻蚀阻挡层,因而可以减少构图工艺次数,降低制造成本。并且,形成源极和漏极时电池反应可以将两层材料同时去除,不用单独分开刻蚀各层材料,且电池反应刻蚀速度快,节省刻蚀时间。
示例性地,薄膜晶体管的源极和漏极由两种可在某种电解液中发生电池反应的材料形成,所述源极和漏极采用后一种成膜方式形成,具体如图1所示包括:所述两种材料中的其中一种材料形成的第一膜层101,所述两种材料中的另一种材料形成的第二膜层102;第二膜层102覆盖于第一膜层101之上,第二膜层102上设置有便于刻蚀液渗透的小孔。这样,第二膜层102、第一膜层101的材料可以同时在刻蚀液(即对应的电解液)中发生电池反应,在不提高刻蚀液浓度的情况下加快刻蚀速率,减少基板在刻蚀液中浸泡的时间,进一步降低有源层被刻蚀液损伤的风险。
示例性地,上述的源极和漏极由两种材料形成,包括铝和氧化铟锡;所述刻蚀液(即这两种材料发生电池反应的电解液)为碱性溶液,例如氢氧化钠溶液,或者氢氧化钾溶液,或者四甲基氢氧化铵溶液。具体刻蚀原理如下:
阳极:Al+4OH-→H2AlO3 -+H2O+3e
阴极:In2O3+3H2O+6e→2In3++6OH- 2H2O+2e→2OH-+H2,此时对应的有源层由不受碱性刻蚀液刻蚀(或刻蚀速度很慢)的化合物半导体形成。
示例性地,化合物半导体包括铟镓锌氧化物、铟钛锌氧化物、铟锡锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。除了前述的化合物半导体之外,本发明实施例中提供的方案还适用于基于黑磷制作有源层的TFT中。
进一步地,所述的薄膜晶体管还包括:设置在源极和漏极之上,在后续工序中为源极和漏极提供防护的金属层(图中未示出),金属层具有与源极和漏极相同的图形。
在形成源极和漏极后还包括清洗、烘干等步骤,之后还需要继续形成其他层的后续工序,清洗液或其他层刻蚀液也多为碱性,会对已形成的源极和漏极造成腐蚀,因此优选地,在源极和漏极之上设置具有与源极和漏极相同图形的金属层,以解决该问题。该金属层可以选择在碱性溶液中较稳定的Mo,并使用酸性刻蚀液去除。
相对应地,本发明实施例还提供一种薄膜晶体管的制造方法,包括以下步骤:
提供衬底基板;
通过涂覆光刻胶、曝光、显影和刻蚀等构图工艺形成栅极和栅绝缘层;
沉积并通过构图工艺形成有源层、源极和漏极,所述源极和漏极包括至少两种材料,所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀,且所述刻蚀液对所述有源层不腐蚀。
针对现有BCE结构中化合物半导体有源层在源极和漏极形成工序中易被刻蚀液损伤的问题,本发明实施例提供的薄膜晶体管制造方法,不需要增加刻蚀阻挡层,可以直接采用背沟道刻蚀工艺制备薄膜晶体管,因而可以减少构图工艺次数,降低制造成本。
需要说明的是,本实施例提供的薄膜晶体管的制造方法,适用于底栅结构的薄膜晶体管,但同时也不排除也适用于顶栅结构的薄膜晶体管。具体实施时,本领域技术人员在本发明揭露的技术范围内,根据实际情况对薄膜晶体管的制造方法的各步骤及顺序进行的简单变化或替换,也应涵盖在本发明的保护范围之内。
为了本领域技术人员更好的理解本发明实施例提供的薄膜晶体管及其制备方法,下面通过具体的实施例对本发明提供的技术方案进行详细说明。
如图2所示,本实施例薄膜晶体管包括:基板20,自下而上设置在基板20上的栅极21、栅绝缘层22、有源层23、源极241、漏极242和钝化层25。有源层23包括:铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO);源极241和漏极242由铝和氧化铟锡两种材料形成,所述源极241和漏极242具体包括:铝形成的第一膜层101,氧化铟锡形成的第二膜层102;第二膜层102覆盖于第一膜层101之上,第二膜层102上设置有便于刻蚀液渗透的小孔。其中第一膜层和第二膜层的材料并不是必须被如此限定,也可以用氧化铟锡形成第一膜层,铝形成第二膜层。
上述有源层材料还可以是不受碱性刻蚀液刻蚀(或刻蚀速度很慢)的其他化合物半导体,如铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种;或者氧化锌ZnO的掺杂体系如HIZO、ITZO、ZTO、AZTO、AZO、GZO等等。以上材料中,有些材料(如IGZO、ITZO、HIZO等)虽然含有铟In元素,理论上也会发生电池反应,但由于G(镓,Ga)、T(锡,Sn)、H(铪,Hf)这些元素对应的化合物三氧化二镓Ga2O3、氧化锡SnO2、二氧化铪HfO2的稳定性高,因此这些材料如IGZO、ITZO、HIZO等作为有源层23的材料时虽含有铟,但也不会参与电池反应或参与电池反应的速率很慢,因此它们都可被认为在碱性刻蚀液中不会被腐蚀。例如上述有源层为IGZO时,因其中含有增加IGZO结构稳定性的材料Ga2O3,在碱性刻蚀液中IGZO有源层几乎不参与电池反应,可认为IGZO也是不受碱性刻蚀液腐蚀。
另外优选地,还可以把将有源层做成两层结构,下层采用IGZO等含有In的材料,而上层采用ZTO、AZTO、GZO等不含In的材料,这样可保证有源层中的In材料完全不会参与电池反应。
需要说明的是,上述有源层可以由上述材料中的一种或几种形成,但具体成膜方式不做限定。如果有源层形成材料为多种时,可以由上述材料中的多种材料形成混合材料薄膜;也可以多层膜叠加,每一层膜为一种材料形成,本实施例不做限定。
上述薄膜晶体管的一种制备工艺实施过程如下:
步骤一、首先,提供基板20并在基板20上沉积栅极金属层,并通过构图工艺形成栅极21。
具体而言,本步骤在基板20上沉积一层高导电薄膜,然后经曝光和刻蚀形成薄膜晶体管的底部栅极(Gate)。其中高导电薄膜的材料可以为金属或者透明高导电化合物薄膜,如图3(a)和图4(a)所示。
步骤二、在进行过前续工序的基板20上,沉积薄膜晶体管的栅绝缘层22、半导体层和复合导电膜层,进行构图工艺形成有源层23和源极241以及漏极242的图形。
本步骤首先依次沉积一层栅绝缘层(Gate Insulator),一层化合物半导体材料层(如IGZO),一组形成源极和漏极的复合导电膜层(如氧化铟锡ITO/铝Al)。其中,所述栅绝缘层(Gate Insulator)为单层或者多层复合结构的绝缘材料,如氧化硅、氮化硅、氧化铝、氧化铪、有机绝缘介质等。源极和漏极材料的复合导电膜层包括由Al形成的第一膜层101,由ITO形成的第二膜层102,ITO在Al之上;还可以Al在ITO之上,即由ITO形成的第一膜层101,由Al形成的第二膜层102,无论哪一种材料层在上,在上的材料层即第二膜层102上均需要具有微小的针孔(Pinhole)以供刻蚀溶液穿过(一般情况下,溅射生长的Al和ITO都有针孔结构),以便下一工序中Al和ITO同时遇到碱性溶液时,发生电池反应。形成第二膜层102的工艺根据形成材料可以从溅射、PECVD以及溶液制程中选择,本实施例中使用的材料为铝和氧化铟锡,所以优选溅射工艺。通过控制溅射工艺的沉积速度(略快于正常沉积速度)可以自然地形成具有便于刻蚀液渗透的小孔的铝膜层或氧化铟锡膜层。因此优选地,本步骤采用溅射的方法,在第一材料层(即第一膜层101)上制备第二材料层(即第二膜层102)。
然后,进行光刻胶涂覆、曝光、显影和刻蚀工艺,其中,刻蚀工艺主要是对形成源极和漏极的复合导电膜层和IGZO半导体层进行。本步骤对IGZO半导体层的刻蚀可按现有技术进行,可以是干法刻蚀也可以是湿法刻蚀或两者的结合;本步骤对形成源极和漏极的复合导电膜层的刻蚀则是采用湿法刻蚀,刻蚀原理即采用本文所述的电池反应进行刻蚀。以本实施例中Al和ITO形成的源极和漏极复合材料层为例,刻蚀溶液穿过第二膜层上的小孔,Al和ITO同时遇到碱性溶液时,发生电池反应:
阳极:Al+4OH-→H2AlO3 -+H2O+3e
阴极:In2O3+3H2O+6e→2In3++6OH- 2H2O+2e→2OH-+H2,本实施例中的刻蚀液为:氢氧化钠溶液,或者氢氧化钾溶液,或者四甲基氢氧化铵溶液。有源层主要为IGZO,IGZO虽然含有In,但由于Ga2O3的存在,刻蚀速度很慢,IGZO近似不能被碱液腐蚀,IGZO有源层不受刻蚀影响。
具体而言,本步骤可先沉积栅绝缘层、化合物半导体层材料层、复合导电膜层,然后对半导体层和复合导电膜层进行第一次掩膜工艺形成有源层的图形,如图3(b)所示;然后对单独对复合导电膜层进行第二次掩膜工艺形成源极和漏极的图形,如图3(c)所示。
或者本步骤也可采用常规做法:先沉积半导体层材料层,然后对半导体层材料层进行第一次掩膜工艺形成有源层的图形;继而形成复合导电膜层,对复合导电膜层进行第二次掩膜工艺形成源极和漏极的图形。
在薄膜晶体管的另一种制备方法中,步骤一与第一种制备方法的步骤一相同。步骤二首先依次沉积一层栅绝缘层,一层化合物半导体材料层,一组形成源极和漏极的复合导电膜层,然后通过双色调掩膜工艺(又称半曝光工艺,Half-Tone或Gray-Tone),对半导体层和复合导电膜层进行一次掩膜工艺,即可形成有源层和源极以及漏极的图形,可以节省一道掩模版。具体如图4(b),涂覆光刻胶,在沟道区域(需要刻蚀至有源层23露出)进行半曝光,保留一定厚度的光刻胶;薄膜晶体管之外的半导体层、复合导电膜层需要全部刻蚀掉,对应区域的光刻胶全曝光;薄膜晶体管的源极和漏极预设位置不进行刻蚀,保留全部厚度的光刻胶,对应区域的光刻胶不曝光,如图4(b)所示。进行第一次刻蚀,将薄膜晶体管之外的半导体层、源极和漏极全部刻蚀掉,形成有源层图形;进行灰化处理减薄剩余的光刻胶,使沟道区域的源极241和漏极242露出;进行第二次刻蚀,将沟道区域刻蚀至有源层23露出,形成源极241和漏极242的图形,如图4(c)所示。
步骤三、沉积钝化层材料,并通过构图工艺形成钝化层25以及钝化层过孔(一般位于漏极上方),如图3(d)和图4(d)所示。
本步骤沉积一层钝化层(Passivation),然后涂覆光刻胶、曝光、显影和刻蚀形成电极的接触孔(即钝化层过孔),并对IGZO的有源层进行钝化保护。其中所述钝化层(Passivation)为单层或者多层复合结构的绝缘材料,如氧化硅、氮化硅、氧化铝、氧化铪、有机绝缘介质等。
图3(a)~图3(d)为第一种制备方法,图4(a)~图4(d)为第二种制备方法,二者区别在于形成源极、漏极有源层时第一种制备方法采用两次掩膜工艺,第二种制备方法采用一次掩膜工艺。
此外,因为工艺过程中的显影液和一些清洗液为碱性,为保证形成源极和漏极的复合导电膜层在这些过程中不被侵蚀,可以在复合导电膜层之上再沉积一层导电材料作为保护层,如钼(Mo)钛(Ti)等,这层材料可以阻挡电池反应的发生,因此,所述源极和漏极的复合层结构还可以为包含一层电导材料在最上层的三明治结构,这层导电材料可以为金属,如钼(Mo)钛(Ti)等。刻蚀上述三明治结构的源极和漏极时,先将最上层的金属层于源极和漏极图案化中所需去除的区域所对应的部分,用酸性刻蚀液刻蚀掉。通过控制酸性刻蚀液的刻蚀速度,在最上层的金属层需要被刻蚀的部分恰好完全去除之后,或者对第二膜层略有过刻时再采用碱性溶液图案化复合导电膜层,形成源极和漏极。该方案可以同时应用于第一种制备方案和第二种制备方案。另外,第二种制备方案的复合导电膜层也可以用溅射工艺形成。
本实施例提供的薄膜晶体管及其制备方法,不需要增加刻蚀阻挡层,可以直接采用背沟道刻蚀工艺制备薄膜晶体管,因而可以减少构图工艺次数,降低制造成本。
在某些电路设计中,例如在OLED(有机发光二极管)的驱动电路中,需要将开关TFT的漏极与驱动TFT的栅极相连,这时制备工艺过程还应考虑如何实现互连,一种具体实现方式可以在沉积形成源极和漏极的复合导电膜层之前,通过涂覆光刻胶、曝光、显影和刻蚀工艺在栅绝缘层上形成过孔,源极或漏极通过该孔直接与栅极连接;另一种具体实现方式在钝化层(Passivation)和栅绝缘层上形成过孔(步骤三)之后,通过另一层高导电材料将源极或漏极和栅极连接在一起。
本实施例还提供一种显示装置,包括:上述的任意一种薄膜晶体管。所述显示装置构图工艺次数少,成本低。所述显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
为了便于清楚说明,在本发明中采用了第一、第二等字样对相似项进行类别区分,该第一、第二字样并不在数量上对本发明进行限制,只是对一种可选的方式的举例说明,本领域技术人员根据本发明公开的内容,想到的显而易见的相似变形或相关扩展均属于本发明的保护范围内。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应该以权利要求的保护范围为准。

Claims (14)

1.一种薄膜晶体管,包括:栅极、有源层、源极和漏极,其特征在于,所述源极和漏极包含由两种材料形成的复合导电膜层,其中:
所述两种材料中的其中一种材料形成第一膜层,所述两种材料中的另一种材料形成第二膜层,所述第二膜层覆盖于所述第一膜层之上,所述第二膜层上设置有便于刻蚀液渗透的小孔;
所述两种材料能在源漏电极层刻蚀工序对应的所述刻蚀液中,发生电池反应从而被刻蚀;且,所述刻蚀液对所述有源层不腐蚀。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述两种材料包括铝和氧化铟锡;所述刻蚀液为碱性溶液。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述碱性溶液为氢氧化钠溶液,或者氢氧化钾溶液,或者四甲基氢氧化铵溶液。
4.根据权利要求2所述的薄膜晶体管,其特征在于,
所述有源层包括不受所述碱性溶液腐蚀的化合物半导体材料。
5.根据权利要求4所述的薄膜晶体管,其特征在于,所述化合物半导体材料包括铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。
6.根据权利要求1-5任一项所述的薄膜晶体管,其特征在于,还包括:
设置在所述源极和漏极之上,在后续工序中为所述源极和漏极提供防护的金属层,所述金属层具有与所述源极和漏极相同的图案。
7.一种显示装置,其特征在于,包括:权利要求1-6任一项所述的薄膜晶体管。
8.一种薄膜晶体管的制造方法,其特征在于,包括以下步骤:
提供衬底基板;
通过构图工艺形成栅极和栅绝缘层;
形成有源层和源极、漏极,所述源极和漏极包括至少两种材料,所述至少两种材料在对应的刻蚀液中发生电池反应从而被刻蚀,且所述刻蚀液对所述有源层不腐蚀。
9.根据权利要求8所述的制造方法,其特征在于,所述源极和漏极采用两种材料形成的复合导电膜层。
10.根据权利要求9所述的制造方法,其特征在于,所述复合导电膜层的制作过程包括:形成第一材料层;
采用溅射的方法,在所述第一材料层上制备第二材料层。
11.根据权利要求9或10所述的制造方法,其特征在于,所述形成有源层和源极、漏极,包括:形成复合导电膜层;还包括:
利用构图工艺对所述复合导电膜层进行掩膜曝光及刻蚀,其中所述复合导电膜层中的两种材料在对应的刻蚀液中发生电池反应从而被刻蚀。
12.根据权利要求11所述的制造方法,其特征在于,所述形成有源层和源极、漏极,包括:
在所述栅绝缘层上沉积化合物半导体薄膜和复合导电膜层;
利用双色调掩膜工艺对所述化合物半导体薄膜和复合导电膜层进行构图,得到化合物半导体有源层和源极、漏极。
13.根据权利要求8、9、10任一项所述的制造方法,其特征在于,所述至少两种材料包括铝和氧化铟锡;所述刻蚀液为碱性溶液。
14.根据权利要求11所述的制造方法,其特征在于,在所述形成复合导电膜层的步骤之后,及在所述利用构图工艺对所述复合导电膜层进行掩膜曝光及刻蚀的步骤之前,还包括:
在所述复合导电膜层上方形成金属层;
利用刻蚀工艺对所述金属层进行构图,使得所述源极和漏极对应区域的金属层被保留。
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Publication number Priority date Publication date Assignee Title
WO2016141429A1 (en) * 2015-03-09 2016-09-15 Rasheed Nizar Augmented reality memorial
CN104716198B (zh) * 2015-03-25 2018-03-27 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示装置
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板
CN105655389B (zh) * 2016-01-15 2018-05-11 京东方科技集团股份有限公司 有源层、薄膜晶体管、阵列基板、显示装置及制备方法
KR101941923B1 (ko) * 2016-12-19 2019-01-25 한국표준과학연구원 수평 p-n 접합 흑린박막 및 이의 제조방법
US10424670B2 (en) 2016-12-30 2019-09-24 Intel Corporation Display panel with reduced power consumption
CN108461403A (zh) * 2018-03-26 2018-08-28 京东方科技集团股份有限公司 显示面板、阵列基板、薄膜晶体管及其制造方法
CN108682692A (zh) 2018-05-18 2018-10-19 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
KR20200034889A (ko) 2018-09-21 2020-04-01 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
US11038027B2 (en) 2019-03-06 2021-06-15 Micron Technology, Inc. Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material
CN110112073B (zh) * 2019-04-22 2021-09-24 中国科学院微电子研究所 场效应晶体管制备方法及场效应晶体管
US11411026B2 (en) 2019-10-31 2022-08-09 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Method for manufacturing array substrate and array substrate
CN110854069A (zh) * 2019-10-31 2020-02-28 深圳市华星光电半导体显示技术有限公司 阵列基板的制备方法及阵列基板
CN113488390B (zh) * 2021-06-21 2023-09-26 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管的制备方法及薄膜晶体管
CN113808952A (zh) * 2021-08-13 2021-12-17 吉林建筑大学 一种薄膜晶体管及其制备方法
CN114609221A (zh) * 2022-03-09 2022-06-10 中山大学 一种氧化物半导体生物传感器、制作方法及使用方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
US7282782B2 (en) 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
KR101325053B1 (ko) * 2007-04-18 2013-11-05 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
KR20080094300A (ko) * 2007-04-19 2008-10-23 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법과 박막 트랜지스터를포함하는 평판 디스플레이
KR101345376B1 (ko) * 2007-05-29 2013-12-24 삼성전자주식회사 ZnO 계 박막 트랜지스터 및 그 제조방법
TWI570937B (zh) * 2008-07-31 2017-02-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
TWI500160B (zh) * 2008-08-08 2015-09-11 Semiconductor Energy Lab 半導體裝置及其製造方法
CN102655148A (zh) * 2012-03-20 2012-09-05 京东方科技集团股份有限公司 Tft基板及其制备方法、液晶显示装置、及电子纸显示装置
CN102637591B (zh) 2012-05-03 2015-05-27 广州新视界光电科技有限公司 一种氧化物半导体上电极层的刻蚀方法
CN103337462B (zh) * 2013-06-13 2017-03-22 北京大学深圳研究生院 一种薄膜晶体管的制备方法
CN103700665B (zh) * 2013-12-13 2016-03-02 京东方科技集团股份有限公司 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置
CN104716198B (zh) * 2015-03-25 2018-03-27 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示装置

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