FR2938702B1 - Preparation de surface d'un substrat saphir pour la realisation d'heterostructures - Google Patents

Preparation de surface d'un substrat saphir pour la realisation d'heterostructures

Info

Publication number
FR2938702B1
FR2938702B1 FR0857854A FR0857854A FR2938702B1 FR 2938702 B1 FR2938702 B1 FR 2938702B1 FR 0857854 A FR0857854 A FR 0857854A FR 0857854 A FR0857854 A FR 0857854A FR 2938702 B1 FR2938702 B1 FR 2938702B1
Authority
FR
France
Prior art keywords
saphir
heterostructures
substrate
production
surface preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0857854A
Other languages
English (en)
Other versions
FR2938702A1 (fr
Inventor
Gweltaz Gaudin
Mark Kennard
Matteo Piccin
Ionut Radu
Alexandre Vaufredaz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0857854A priority Critical patent/FR2938702B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to EP09749151A priority patent/EP2359391A1/fr
Priority to JP2011536838A priority patent/JP2012509581A/ja
Priority to US13/130,239 priority patent/US20120015497A1/en
Priority to KR1020117010800A priority patent/KR20110086038A/ko
Priority to CN2009801460442A priority patent/CN102217037A/zh
Priority to PCT/EP2009/065202 priority patent/WO2010057842A1/fr
Publication of FR2938702A1 publication Critical patent/FR2938702A1/fr
Application granted granted Critical
Publication of FR2938702B1 publication Critical patent/FR2938702B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Ceramic Products (AREA)
FR0857854A 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures Expired - Fee Related FR2938702B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0857854A FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
JP2011536838A JP2012509581A (ja) 2008-11-19 2009-11-16 ヘテロ構造を作製するためのサファイア基板の表面の前処理
US13/130,239 US20120015497A1 (en) 2008-11-19 2009-11-16 Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures
KR1020117010800A KR20110086038A (ko) 2008-11-19 2009-11-16 헤테로 구조체를 제작하기 위한 사파이어 기판의 표면 준비
EP09749151A EP2359391A1 (fr) 2008-11-19 2009-11-16 Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures
CN2009801460442A CN102217037A (zh) 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面
PCT/EP2009/065202 WO2010057842A1 (fr) 2008-11-19 2009-11-16 Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0857854A FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures

Publications (2)

Publication Number Publication Date
FR2938702A1 FR2938702A1 (fr) 2010-05-21
FR2938702B1 true FR2938702B1 (fr) 2011-03-04

Family

ID=40796247

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0857854A Expired - Fee Related FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures

Country Status (7)

Country Link
US (1) US20120015497A1 (fr)
EP (1) EP2359391A1 (fr)
JP (1) JP2012509581A (fr)
KR (1) KR20110086038A (fr)
CN (1) CN102217037A (fr)
FR (1) FR2938702B1 (fr)
WO (1) WO2010057842A1 (fr)

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Publication number Priority date Publication date Assignee Title
EP2695183A1 (fr) 2011-04-08 2014-02-12 Ev Group E. Thallner GmbH Procédé de liaison permanente de plaquettes de semi-conducteurs
FR2977260B1 (fr) 2011-06-30 2013-07-19 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiale epaisse de nitrure de gallium sur un substrat de silicium ou analogue et couche obtenue par ledit procede
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
SG2014009930A (en) * 2012-07-24 2014-05-29 Ev Group E Thallner Gmbh Method and device for permanent bonding of wafers
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9608433B2 (en) * 2013-03-14 2017-03-28 Hubbell Incorporated GFCI test monitor circuit
WO2014178356A1 (fr) * 2013-05-01 2014-11-06 信越化学工業株式会社 Procédé de production de substrat hybride et substrat hybride
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
FR3034252B1 (fr) * 2015-03-24 2018-01-19 Soitec Procede de reduction de la contamination metallique sur la surface d'un substrat
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components
SG11201805655VA (en) * 2016-02-16 2018-07-30 Ev Group E Thallner Gmbh Method and device for bonding substrates
FR3068508B1 (fr) 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
CN108493321A (zh) * 2018-03-26 2018-09-04 华灿光电（浙江）有限公司 一种发光二极管芯片及其制备方法
CN111041423B (zh) * 2019-12-10 2021-11-19 太原理工大学 蓝宝石表面结构与成分梯度层设计改善其焊接性能的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH05235312A (ja) * 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
JP3250721B2 (ja) * 1995-12-12 2002-01-28 キヤノン株式会社 Ｓｏｉ基板の製造方法
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
US6423613B1 (en) * 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6281146B1 (en) * 1999-09-15 2001-08-28 Taiwan Semiconductor Manufacturing Company Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US6930041B2 (en) * 2000-12-07 2005-08-16 Micron Technology, Inc. Photo-assisted method for semiconductor fabrication
US6576564B2 (en) * 2000-12-07 2003-06-10 Micron Technology, Inc. Photo-assisted remote plasma apparatus and method
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
SE521938C2 (sv) * 2001-12-27 2003-12-23 Cerbio Tech Ab Keramiskt material, förfarande för framställning av keramiskt material och benimplantat, tandfyllnadsimplantat och biocement innefattande det keramiska materialet
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
DE10326578B4 (de) * 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion

Also Published As

Publication number Publication date
EP2359391A1 (fr) 2011-08-24
US20120015497A1 (en) 2012-01-19
CN102217037A (zh) 2011-10-12
FR2938702A1 (fr) 2010-05-21
JP2012509581A (ja) 2012-04-19
KR20110086038A (ko) 2011-07-27
WO2010057842A1 (fr) 2010-05-27

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120907

ST Notification of lapse

Effective date: 20140731