WO2010057842A1 - Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures - Google Patents

Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures Download PDF

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Publication number
WO2010057842A1
WO2010057842A1 PCT/EP2009/065202 EP2009065202W WO2010057842A1 WO 2010057842 A1 WO2010057842 A1 WO 2010057842A1 EP 2009065202 W EP2009065202 W EP 2009065202W WO 2010057842 A1 WO2010057842 A1 WO 2010057842A1
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WIPO (PCT)
Prior art keywords
substrate
bonding
sapphire
stoving
silicon
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PCT/EP2009/065202
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English (en)
Inventor
Gweltaz Gaudin
Mark Kennard
Matteo Piccin
Ionut Radu
Alexandre Vaufredaz
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S.O.I.Tec Silicon On Insulator Technologies
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Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to CN2009801460442A priority Critical patent/CN102217037A/zh
Priority to JP2011536838A priority patent/JP2012509581A/ja
Priority to EP09749151A priority patent/EP2359391A1/fr
Priority to US13/130,239 priority patent/US20120015497A1/en
Publication of WO2010057842A1 publication Critical patent/WO2010057842A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to fabricating heterostructures formed by bonding at least one substrate made of a semiconductor material such as silicon on a substrate made of sapphire (Al 2 O 3 ) .
  • the invention applies in particular to fabricating silicon-on-sapphire (SOS) type structures.
  • Heterostructures comprising a layer of silicon on a sapphire substrate present particular advantages.
  • SOS structures enable high frequency devices to be made that present low energy consumption.
  • the use of sapphire substrates also makes it possible to achieve very good heat dissipation, better than that obtained for example with silicon substrates.
  • SOS structures were initially made by epitaxially growing a layer of silicon on a sapphire substrate. Nevertheless, with that technique, it is difficult to obtain layers or films of silicon that present a low density of crystal defects, given the large difference between the lattice parameters and the coefficients of thermal expansion of the two materials.
  • SOS structures are made by assembling a layer of silicon on a sapphire substrate.
  • molecular bonding also known as "direct wafer bonding” or "fusion bonding” which is a technique that enables two substrates to be bonded together providing they present surfaces that are perfectly plane (“mirror polish"), and without using an intermediate adhesive (glue, solder, etc.).
  • Bonding is typically initiated by local application of a small amount of pressure to the two substrates that have been put into intimate contact. A bonding wave then propagates over the entire extent of the substrate in a few seconds .
  • their bonding faces need to present a very low density of contaminants. These contaminants, which may come from the material itself or from prior treatment such as chemical-mechanical-polishing (CMP) , are essentially of particulate, metallic, and organic origin.
  • the cleaning generally consists in treating the substrate with a chemical cleaning agent of the RCA type.
  • the two substrates as bonded together in this way are subjected to heat treatment known as a bonding reinforcing anneal or as a stabilizing anneal.
  • the anneal is generally performed at high temperatures of about 700 0 C to 800 0 C.
  • anneals for reinforcing the bonding interface can be performed only at temperatures that are relatively low ⁇ 300 0 C) compared with those usually used. This temperature limitation does not enable a high level of bonding energy to be obtained between the silicon substrate and the sapphire substrate.
  • One of the objects of the invention is to remedy the above-mentioned drawbacks by proposing a solution that enables a heterostructure to be obtained by bonding, on a sapphire substrate, another substrate having a coefficient of thermal expansion that is different from that of sapphire, and to do so while obtaining good bonding energy between the substrates and while limiting the appearance of defects after bonding and while limiting treatments after bonding.
  • the present invention proposes a method of fabricating a heterostructure comprising at least a first substrate made of sapphire and a second substrate made of a material having a coefficient of thermal expansion that Is different from that of the first substrate, the method including a step of molecular bonding the second substrate on the first substrate made of sapphire, in which method, prior to bonding the two substrates together, a step is performed of stovlng the first substrate at a temperature lying In the range 100 0 C to 500 0 C. When the stovlng step is performed at a temperature of 100 0 C, the duration of the stoving step is then at least 1 hour (h) .
  • such stoving of the sapphire substrate prior to bonding serves to improve significantly the energy and the quality of the bonding compared with bonding performed without the prior stoving step.
  • the stoving step is performed at a temperature of about 200 0 C for a duration of about 2 h.
  • the quality of the bonding, and in particular the bonding energy may be further improved by activating the bonding surface (s) of one or both substrates by means of plasma treatment.
  • the plasma is used at a mean power density that is preferably less than or equal to 1 watt per square centimeter (W/cm 2 ) .
  • the plasma is also preferably a plasma based on oxygen.
  • the method further includes, prior to bonding the two substrates together, forming an oxide layer on the bonding surface of the second substrate.
  • Molecular bonding between the first and second substrate is preferably performed at ambient temperature.
  • the method may further include a step of performing a bonding stabilizing anneal at a temperature of less than 300 0 C.
  • This limit on the temperature of the stabilizing anneal serves to avoid excessive stresses arising in the structure because of the difference between the coefficients of thermal expansion of the two substrates. In spite of temperature being limited in this way, the stoving step of the invention makes it possible to obtain good bonding energy.
  • the second substrate may in particular be constituted by a layer of silicon or by a silicon-on- insulator (SOI) structure.
  • Figure 1 is a chart showing bonding energy values obtained as a function of how the sapphire substrate surface is prepared and as a function of the stabilization anneal temperature;
  • Figure 2 is a chart showing the different lengths of ring obtained as a function of the mean power density of the plasma used for activating the bonding surface of the sapphire substrate;
  • Figures 3A to 3F are diagrammatic views showing the fabrication of a heterostructure by implementing a method of the invention.
  • Figure 4 is a flow chart of the steps implemented while fabricating the three-dimensional structure shown in Figures 3A to 3F; and • Figure 5A shows an SOS type heterostructure in which the bonding surface of the sapphire support substrate has been prepared in accordance with the prior art, while Figure 5B shows an SOS type heterostructure with the bonding surface of the sapphire support substrate prepared in accordance with an implementation of the method of the invention.
  • the present invention applies in general to molecular bonding between a first substrate made of sapphire and a second substrate made of some other material that presents a different coefficient of thermal expansion, such as in particular: silicon; quartz, germanium; and materials of the IH-V group having a coefficient of thermal expansion greater than that of silicon, such as GaAs or InP.
  • a first substrate made of sapphire and a second substrate made of some other material that presents a different coefficient of thermal expansion
  • silicon quartz, germanium
  • materials of the IH-V group having a coefficient of thermal expansion greater than that of silicon, such as GaAs or InP such as GaAs or InP.
  • the principle of molecular bonding also known as direct bonding, is based on putting two surfaces into direct contact, i.e. without using any specific bonding material (adhesive, wax, solder, etc.).
  • the temperature of the reinforcing or stabilizing anneal must be limited (less than 300 0 C) in order to avoid cracks appearing and developing in the substrate bonded on the sapphire.
  • the bonding surfaces of the two substrates need to be prepared as well as possible for enhancing molecular bonding and obtaining high bonding energy
  • the sapphire substrate is cleaned after its bonding surface has been polished, which is generally performed by CMP, a polishing or planarizing technique that is well known and that makes use of fabric associated with a polishing solution containing both an agent that is suitable for attacking the surface of the layer chemically (e.g. NH 4 OH) and abrasive particles suitable for attacking said surface mechanically (e.g. particles of silica).
  • the bonding surface of the sapphire substrate is usually subjected to RCA type chemical cleaning which may be followed by scrubbing.
  • the Applicant has observed that, even when the sapphire substrate is prepared in that way, the bonding of a silicon substrate on a sapphire substrate can give rise to results that are unsatisfactory, leading in particular to a high density of defects in the silicon, to the formation of a ring (a non-bonded zone at the margins of the wafers) that is wide and irregular, and low bonding energy.
  • Figure 1 shows the bonding energy levels obtained as a function of various different preparations of the bonding surface when fabricating heterostructures of the silicon-on-sapphire (SOS) type.
  • the bonding energy is greater when the sapphire substrate has previously been subjected to stoving at 200 0 C for 2 h prior to cleaning and scrubbing (columns C) , compared with RCA cleaning on its own (columns A) , or with RCA cleaning followed by scrubbing (column B) , and that this applies regardless of the stabilizing anneal temperature (lying in the range ambient temperature to 200 0 C) .
  • the Applicant has also measured the density of defects (for defects of size lying firstly in the range 100 micrometers ( ⁇ m) to 500 ⁇ m, and secondly in the range
  • a first SOS type heterostructure for which fabrication included cleaning and scrubbing the sapphire substrate, bonding a silicon substrate on the sapphire substrate, a stabilizing anneal of the bonding, and thinning of the silicon substrate by mechanical polishing (grinding) and chemical etching (TMAH)
  • TMAH chemical etching
  • the . second heterostructure presented a defect density that was ten or more times smaller than the density presented by the first heterostructure.
  • the second heterostructure presented ring type margin defectuosity (non-transferred peripheral zone as shown in Figure 2) that was divided by two compared with the first heterostructure.
  • the step of stoving the sapphire substrate in accordance with the invention is performed at a temperature lying in the range 100 0 C to 500 0 C.
  • the duration of the stoving is a function of its temperature. It lies between several minutes and several hours depending on the temperature used.
  • stoving is performed for a duration of at least 1 h, and preferably over a duration lying in the range 4 h to 5 h.
  • the duration of the stoving is about 2 h.
  • the duration of the stoving lies in the range a few minutes to one hour. Consequently, the higher the stoving temperature, the shorter its duration.
  • the stoving is performed in air or in an inert gas such as nitrogen or argon at normal pressure (i.e. atmospheric pressure) .
  • the stoving of the invention serves to eliminate contamination of organic origin in a manner that is much more effective than when using chemical cleaning of the RCA type.
  • This stoving step also presents the advantage of not modifying the surface state of the sapphire, i.e. of not creating additional atomic steps ⁇ "miscut"). Contrary to heat treatment performed at high temperature, stoving in accordance with the invention does not modify the local surface of the sapphire wafer. According to another aspect of the invention, the quality of the bonding, and in particular the bonding energy, can be further improved by activating the bonding surface (s) of one or both substrates by means of a plasma treatment .
  • the bonding surface of the sapphire substrate and/or of the other substrate may be exposed to plasma based on oxygen, nitrogen, argon, etc. Nevertheless, for molecular bonding of a sapphire substrate, it is preferable to use a plasma based on oxygen, since that makes it possible to obtain a bonding energy that is greater and with a density of defects that is smaller in comparison with a plasma based on nitrogen, for example.
  • the other parameters or conditions for plasma generation are those generally used by the person skilled in the art.
  • the plasma based on oxygen may be generated in equipment originally provided for performing reactive ion etching (RIE) with capacitive coupling and under the following conditions :
  • ECR electron cyclotron resonance
  • the table below shows the roughness and the contact angle measured at the surfaces of sapphire substrates and of silicon substrates.
  • the sapphire substrate has been treated with a plasma based on oxygen, its surface presents a contact angle of 2°.
  • the contact angle is respectively greater than 20° or equal to 6°.
  • the bonding surfaces need to present a contact angle of less than 5° in order to have good control over the quality of bonding .
  • the oxygen-based plasma treatment of the invention does not significantly increase the roughness of the sapphire surface.
  • fabricating a heterostructure of the invention is not restricted to using hydrophilic bonding.
  • the bonding may equally well be hydrophobic.
  • molecular bonding between the first substrate made of sapphire and the second substrate having a coefficient of thermal expansion different from that of the first substrate is preferably performed at ambient temperature, i.e. at room temperature without using means for heating the substrate during bonding (a temperature generally of about 20 0 C and that can vary ( ⁇ 10 0 C) depending on the temperature of the room) .
  • the initial substrate 110 is constituted by an SOI type structure comprising a silicon layer 111 on a support 113 that is also made of silicon, with a buried oxide layer 112, e.g. made of SiO 2 , being disposed between the layer 111 and the support 113.
  • SOI type structure comprising a silicon layer 111 on a support 113 that is also made of silicon, with a buried oxide layer 112, e.g. made of SiO 2 , being disposed between the layer 111 and the support 113.
  • the first substrate or initial substrate may also be constituted by a simple silicon wafer optionally including an oxide layer on its bonding surface.
  • the support substrate 120 is constituted by a sapphire wafer ( Figure 3A) .
  • the sapphire substrate 120 is subjected to stoving, performed in this example at a temperature of 200 0 C for a period of 2 h (step Sl) .
  • this stoving serves in particular to eliminate contaminants of organic origin present on the bonding surface of the sapphire substrate, thereby enhancing molecular bonding while limiting the appearance of defects .
  • the bonding surface of the sapphire substrate 120 is then subjected to wet chemical cleaning (step S2) .
  • the wet cleaning may be performed in particular by RCA cleaning (i.e. a combination of a bath of SCl (NH 4 OH, H 2 O 2 , H 2 O) suitable for removing particles and hydrocarbons, and a bath of SC2 (HCl, H 2 O 2 , H 2 O) suitable for removing metallic contaminants), cleaning of the
  • the surface 120a of the substrate 120 can be activated by plasma treatment (step S3) .
  • the surface 120a is preferably exposed to an oxygen-based plasma with a mean power density that does not exceed 1 W/cm 2 .
  • the other conditions of the plasma treatment may correspond to those described above.
  • the surface Ilia of the silicon layer 111 of the initial substrate 110 may be covered in a thermal oxide layer 114, e.g. formed by oxidizing the surface of the substrate ( Figure 3C, step S4).
  • the surface Ilia of the initial substrate 110 optionally covered in another oxide layer may also be activated by plasma treatment (step S5) . Since this is a silicon surface, it may be exposed to a standard plasma, i.e. a plasma based on oxygen, nitrogen, argon, etc., with power density that is not limited to 1 W/cm 2 . Activating a silicon bonding surface is well known to the person skilled in the art and is not described in greater detail for reasons of simplification.
  • One or more cleans subsequent to the plasma exposure may be performed, in particular in order to remove the contaminants that were introduced during exposure, such as rinsing in water and/or cleaning in SCl (NH 4 OH, H 2 O 2 , H 2 O), optionally followed by drying by centrifuging.
  • the surfaces Ilia and 120a are put into intimate contact and pressure is applied to one of the two substrates so as to initiate the propagation of a bonding wave between the contacting surfaces (step S6, Figure 3D) .
  • the bonding is then reinforced by performing a bonding reinforcing or stabilizing anneal (step S7) .
  • the stabilizing anneal is performed at a temperature of less than 300 0 C.
  • the stabilizing anneal may be performed at a temperature of
  • the fabrication of the heterostructure is continued by thinning the initial substrate 110 so as to form a transferred layer 115 corresponding to a fraction of the silicon layer 111 (step SS, Figure 3E). Thinning is performed initially by grinding off a major fraction of the support 113 and is then continued by chemical etching, e.g. by means of a solution of tetramethylammonium hydroxide (TMAH) , In an optional step, the structure is edged so as to remove the chamfers and edge roll-off present at the peripheries of the substrates (step S9, Figure 3F) .
  • TMAH tetramethylammonium hydroxide
  • FIG. 5A shows an SOS type heterostructure obtained from an initial SOI substrate bonded on a sapphire support substrate.
  • the bonding surface of the sapphire substrate was prepared using RCA cleaning and scrubbing.
  • the structure was subjected to a stabilizing anneal at 200 0 C for 2 h and it was thinned by grinding and by chemical etching with TMAH.
  • Figure 5B also shows an SOS type heterostructure that was made differently from that of Figure 5A in that prior to the RCA cleaning and the scrubbing, the bonding surface of the sapphire substrate was also prepared by:
  • the stoving step of the invention makes it possible to increase the bonding energy in an SOS type structure.
  • This bonding energy may also be increased by activating the bonding surface of the sapphire substrate by plasma treatment as described above. As shown in Figure 1, it can be seen that the bonding energy is even greater when the surface of the sapphire substrate has been exposed, after stoving, RCA cleaning and scrubbing, to a plasma (column D) as compared with no plasma treatment (column C) .
  • the Invention may also be applied to layer transfer techniques other than that described, e.g. in application of the Smart Cut technology.

Abstract

L'invention porte sur un procédé de fabrication d'une hétérostructure comprenant au moins un premier substrat (120) constitué de saphir et un second substrat (110) constitué d'un matériau ayant un coefficient de dilatation thermique qui est différent de celui du premier substrat, le procédé comprenant une étape (S6) de liaison moléculaire du second substrat (110) sur le premier substrat (120) constitué de saphir. Selon l'invention, le procédé comprend, avant la liaison des deux substrats l'un à l'autre, une étape (S1) d'étuvage du premier substrat (120) à une température s’inscrivant dans la plage allant de 100°C à 500°C.
PCT/EP2009/065202 2008-11-19 2009-11-16 Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures WO2010057842A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2009801460442A CN102217037A (zh) 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面
JP2011536838A JP2012509581A (ja) 2008-11-19 2009-11-16 ヘテロ構造を作製するためのサファイア基板の表面の前処理
EP09749151A EP2359391A1 (fr) 2008-11-19 2009-11-16 Préparation d'une surface d'un substrat en saphir pour la fabrication d'hétérostructures
US13/130,239 US20120015497A1 (en) 2008-11-19 2009-11-16 Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0857854A FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
FR0857854 2008-11-19

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WO2010057842A1 true WO2010057842A1 (fr) 2010-05-27

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US (1) US20120015497A1 (fr)
EP (1) EP2359391A1 (fr)
JP (1) JP2012509581A (fr)
KR (1) KR20110086038A (fr)
CN (1) CN102217037A (fr)
FR (1) FR2938702B1 (fr)
WO (1) WO2010057842A1 (fr)

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EP2359391A1 (fr) 2011-08-24
JP2012509581A (ja) 2012-04-19
FR2938702A1 (fr) 2010-05-21
KR20110086038A (ko) 2011-07-27
FR2938702B1 (fr) 2011-03-04
US20120015497A1 (en) 2012-01-19

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