JP5589030B2 - 非晶質酸化物、及び電界効果型トランジスタ - Google Patents
非晶質酸化物、及び電界効果型トランジスタ Download PDFInfo
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- JP5589030B2 JP5589030B2 JP2012148444A JP2012148444A JP5589030B2 JP 5589030 B2 JP5589030 B2 JP 5589030B2 JP 2012148444 A JP2012148444 A JP 2012148444A JP 2012148444 A JP2012148444 A JP 2012148444A JP 5589030 B2 JP5589030 B2 JP 5589030B2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
非晶質酸化物であって、
前記非晶質酸化物は、微結晶を含み、且つ
電子キャリア濃度が1018/cm3未満である、ことを特徴とする。
前記非晶質酸化物は、微結晶を含み、且つ
電子キャリア濃度が増加すると共に、電子移動度が増加する傾向を示す、
ことを特徴とする。
微結晶を含む非晶質酸化物を有する活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
を具備することを特徴とする。
前記非晶質酸化物は層厚方向に組成が変化しており、且つ、
前記非晶質酸化物は、
電子キャリア濃度が1018/cm3未満である、ことを特徴とする。
層厚方向に組成が変化している非晶質酸化物を含む活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
を具備し、
前記活性層は、第1の領域と該第1の領域よりも前記ゲート絶縁膜に近い第2の領域とを含み、
前記第2の領域の酸素濃度が、前記第1の領域の酸素濃度より高いことを特徴とする。
InあるいはZnの少なくとも一方を有する非晶質酸化物を含む活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
を具備し、
前記活性層は、第1の領域と該第1の領域よりも前記ゲート絶縁膜に近い第2の領域とを含み、
前記第2の領域のIn濃度あるいはZn濃度が、前記第1の領域のIn濃度あるいはZn濃度より高いことを特徴とする。
非晶質酸化物であって、
前記非晶質酸化物は膜厚方向に組成が変化しており、且つ、
前記非晶質酸化物は、
電子キャリア濃度が増加すると共に、電子移動度が増加する傾向を示す、
ことを特徴とする。
電界効果型トランジスタであって、In及びZnを有する非晶質酸化物を含む活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
を具備し、
前記活性層は、第1の領域と該第1の領域よりも前記ゲート絶縁膜に近い第2の領域とを含み、
前記第2の領域のIn濃度が、前記第1の領域のIn濃度より高いか、あるいは前記第2の領域のZn濃度が、前記第1の領域のZn濃度より高いことを特徴とする。
非晶質酸化物であって、
該非晶質酸化物の電子キャリア濃度が1018/cm3未満であり、且つ
Li、Na、Mn、Ni、Pd、Cu、Cd、C、N、P、Ti、Zr、V、Ru、Ge、Sn、Fから選ばれる1種または複数種の元素を含むことを特徴とする。
非晶質酸化物であって、
前記非晶質酸化物は、電子キャリア濃度が増加すると共に、電子移動度が増加する傾向を示し、且つ
Li、Na、Mn、Ni、Pd、Cu、Cd、C、N、P、Ti、Zr、V、Ru、Ge、Sn、Fから選ばれる少なくとも1種の元素を含むことを特徴とする。
電界効果型トランジスタであって、
Li、Na、Mn、Ni、Pd、Cu、Cd、C、N、P、Ti、Zr、V、Ru、Ge、Sn、Fから選ばれる少なくとも1種の元素を含む非晶質酸化物を有する活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
を具備することを特徴とする。
前記非晶質酸化物が、InとZnとSnを含む酸化物、InとZnを含む酸化物、InとSnを含む酸化物、またはInを含む酸化物のいずれかであることが好ましいのものである。
本実施形態に係る発明は、非晶質酸化物に関し、
該非晶質酸化物は微結晶を含むことを特徴とする。
ここで、非晶質酸化物内に微結晶が含有されているか否かは、例えば成膜された非晶質酸化物の膜の断面TEM(透過型電子顕微鏡)写真などから判断される。
上記非晶質酸化物膜とは例えば、具体的には、In−Ga−Zn−Oを含み構成され、結晶状態における組成がInGaO3(ZnO)m(mは6未満の自然数)で表される。
結晶状態における組成がInGaO3(ZnO)m(mは6未満の自然数)で表される透明アモルファス酸化物薄膜は、mの値が6未満の場合は、800℃以上の高温までアモルファス状態が安定に保たれるが、mの値が大きくなるにつれ結晶化しやすくなる。すなわち、InGaO3に対するZnOの比が増大して、ZnO組成に近づくにつれ、結晶化しやすくなる。
本実施形態に係る非晶質酸化物は、
その膜厚方向で組成が変化していることを特徴とする。
該非晶質酸化物に含まれる酸素濃度は、該界面側の領域の方が、該界面より離れた領域よりも高くなるように構成するのである。
また、InあるいはZnの少なくとも一方を有する非晶質酸化物を含む活性層と、該活性層と界面を構成するゲート絶縁膜とを備えるトランジスタにおいて、該非晶質酸化物に含まれるInあるいはZn濃度は、該界面側の領域の方が、該界面より離れた領域よりも高くなるように構成することも好ましい形態である。この場合、電界効果移動度を高めることができる。
結晶状態における組成がInGaO3(ZnO)m(mは6未満の自然数)で表される透明アモルファス酸化物薄膜は、mの値が6未満の場合は、800℃以上の高温までアモルファス状態が安定に保たれるが、mの値が大きくなるにつれ結晶化しやすくなる。すなわち、InGaO3に対するZnOの比が増大して、ZnO組成に近づくにつれ、結晶化しやすくなる。
本実施形態に係る非晶質酸化物は、添加物として、Li、Na、Mn、Ni、Pd、Cu、Cd、C、N、P、Ti、Zr、V、Ru、Ge、Sn、Fから選ばれる1種または複数種の元素を含むことを特徴とする。
本発明に係る非晶質酸化物の電子キャリア濃度は、室温で測定する場合の値である。室温とは、例えば25℃であり、具体的には0℃から40℃程度の範囲から適宜選択されるある温度である。なお、本発明に係るアモルファス酸化物の電子キャリア濃度は、0℃から40℃の範囲全てにおいて、1018/cm3未満を充足する必要はない。例えば、25℃において、キャリア電子密度1018/cm3未満が実現されていればよい。また、電子キャリア濃度を更に下げ、1017/cm3以下、より好ましくは1016/cm3以下にするとノーマリオフのTFTが歩留まり良く得られる。
結晶状態における組成がInGaO3(ZnO)m(mは6未満の自然数)で表される非晶質酸化物薄膜は、mの値が6未満の場合は、800℃以上の高温まで、非晶質状態が安定に保たれるが、mの値が大きくなるにつれ、結晶化しやすくなる。すなわち、InGaO3に対するZnOの比が増大して、ZnO組成に近づくにつれ、結晶化しやすくなる。
図6に、室温下で測定したMISFET素子の電流−電圧特性を示す。ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型半導体であることが分かる。これは、アモルファスIn−Ga−Zn−O系半導体がn型であるという事実と矛盾しない。IDSはVDS=6V程度で飽和(ピンチオフ)する典型的な半導体トランジスタの挙動を示した。利得特性を調べたところ、VDS=4V印加時におけるゲート電圧VGSの閾値は約−0.5Vであった。また、VG=10V時には、IDS=1.0×10−5Aの電流が流れた。これはゲートバイアスにより絶縁体のIn−Ga−Zn−O系アモルファス半導体薄膜内にキャリアを誘起できたことに対応する。
雰囲気ガスとしてアルゴンガスを用いた高周波SP法により、成膜する場合について説明する。
さらに、組成系を拡大して研究を進めた結果、Zn,In及びSnのうち、少なくとも1種類の元素の酸化物からなるアモルファス酸化物で、電子キャリア濃度が小さく、かつ電子移動度が大きいアモルファス酸化物膜を作製できることを見出した。
(a) 室温での電子キャリア濃度が、1018/cm3未満のアモルファス酸化物。
(b) 電子キャリア濃度が増加すると共に、電子移動度が増加することを特徴とするアモルファス酸化物。
(c) 室温での電子移動度が、0.1cm2/V・秒超であることを特徴とする上記(a)又は(b)に記載されるアモルファス酸化物。
(d) 縮退伝導を示す上記(b)から(c)のいずれかに記載されるアモルファス酸化物である。なお、ここでの縮退伝導とは、電気抵抗の温度依存性における熱活性化エネルギーが、30meV以下の状態をいう。
(e) Zn,In及びSnのうち、少なくとも1種類の元素を構成成分として含む上記(a)から(d)のいずれかに記載されるアモルファス酸化物。
(f) 上記(e)に記載のアモルファス酸化物に、Znより原子番号の小さい2族元素M2(M2は、Mg,Ca)、Inより原子番号の小さい3属元素M3(M3は、B,Al、Ga、Y),Snより小さい原子番号の小さい4属元素M4(M4は、Si,Ge,Zr)、5属元素M5(M5は、V,Nb,Ta)およびLu、Wのうち、少なくとも1種類の元素を含むアモルファス酸化物膜。
(g) 結晶状態における組成がIn1−xM3xO3(Zn1−yM2yO)m(0≦x、y≦1、mは0又は6未満の自然数)である化合物単体又はmの異なる化合物の混合体である(a)から(f)のいずれかに記載のアモルファス酸化物膜。M3たとえば、Gaであり、M2は例えば、Mgである。
(h) ガラス基板、金属基板、プラスチック基板又はプラスチックフィルム上に設けた上記(a)から(g)記載のアモルファス酸化物膜。
KrFエキシマレーザーを用いたPLD法により、ガラス基板(コーニング社製1737)上にIn−Zn―Ga―O系アモルファス酸化物膜を堆積させた。このとき、InGaO3(ZnO)及びInGaO3(ZnO)4組成を有する多結晶焼結体をそれぞれターゲットとした。
ターゲットとして多結晶InGaO3(Zn1−xMgxO)4(0<x≦1)を用い、PLD法により、ガラス基板上にInGaO3(Zn1−xMgxO)4(0<x≦1)膜を成膜した。成膜装置は、図7に記載の装置を用いた。
KrFエキシマレーザーを用いたPLD法により、In2O3多結晶焼結体をターゲットとして、厚さ200μmのPETフィルム上にIn2O3膜を成膜した。
KrFエキシマレーザーを用いたPLD法により、(In0.9Sn0.1)O3.1多結晶焼結体をターゲットとして、厚さ200μmのPETフィルム上にIn−Sn−O系酸化物膜を成膜した。
具体的には、
被成膜基板として、SiO2ガラス基板(コーニング社製1737)を用意した。
基板前処理として、超音波脱脂洗浄をアセトン、エタノール、超純水を用いて各5分間ずつ行った。 その後、空気中100℃で乾燥させた。
ターゲットは、In2O3−SnO2焼結体(サイズ 20mmΦ5mmt)を準備した。これは、出発原料として、In2O3−SnO2(4N試薬)を湿式混合(溶媒:エタノール)、仮焼(1000℃:2h)、乾式粉砕、本焼結(1550℃:2h)を経て得られる。
被成膜基板として、SiO2ガラス基板(コーニング社製1737)を用意した。
TFT素子の作製
図5に示すトップゲート型TFT素子を作製した。
図6に、室温下で測定したTFT素子の電流−電圧特性を示す。ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型伝導であることが分かる。
図5に示すトップゲート型TFT素子を作製した。
まず、ポリエチレン・テレフタレート(PET)フィルム(1)上に、PLD法により、酸素分圧5Paの雰囲気で、チャンネル層(2)として用いる厚さ120nmのIn−Zn−Ga−O系アモルファス酸化物膜を形成した。このとき、InGaO3(ZnO)組成を有する多結晶焼結体をターゲットとした。
PETフィルム上に形成したTFTの室温下で測定した電流−電圧特性は、図6と同様であった。すなわち、ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことから、チャネルがn型伝導であることが分かる。これは、アモルファスIn−Ga−Zn−O系アモルファス酸化物膜がn型伝導体であるという事実と矛盾しない。IDSはVDS=6V程度で飽和(ピンチオフ)する典型的なトランジスタの挙動を示した。また、Vg=0のときには、Ids=10−8A,Vg=10V時には、IDS=2.0×10−5Aの電流が流れた。これはゲートバイアスにより絶縁体のIn−Ga−Zn−O系アモルファス酸化物膜内に電子キャリアを誘起できたことに対応する。
図5に示すトップゲート型TFT素子を作製した。まず、ポリエチレン・テレフタレート(PET)フィルム(1)上に、PLD法により、チャンネル層(2)として用いる厚さ80nmのIn2O3アモルファス酸化物膜を形成した。
PETフィルム上に形成したTFTの室温下で測定した電流−電圧特性を測定した。ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型半導体であることが分かる。これは、In−O系アモルファス酸化物膜がn型伝導体であるという事実と矛盾しない。IDSはVDS=5V程度で飽和(ピンチオフ)する典型的なトランジスタの挙動を示した。また、Vg=0V時には、2×10−8A、VG=10V時には、IDS=2.0×10−6Aの電流が流れた。これはゲートバイアスにより絶縁体のIn−O系アモルファス酸化物膜内に電子キャリアを誘起できたことに対応する。
図5に示すトップゲート型TFT素子を作製した。まず、ポリエチレン・テレフタレート(PET)フィルム(1)上に、PLD法により、チャンネル層(2)として用いる厚さ100nmのIn−Sn−O系アモルファス酸化物膜を形成した。さらにその上に、チャンバー内酸素分圧を1Pa未満にして、さらに酸素ラジカル発生装置への印加電圧をゼロにして、PLD法により、電気伝導度の大きなIn−Sn−O系アモルファス酸化物膜及び金膜をそれぞれ30nm積層した。そして、フォトリソグラフィー法とリフトオフ法により、ドレイン端子(5)及びソース端子(6)を形成した。最後にゲート絶縁膜(3)として用いるY2O3膜を電子ビーム蒸着法により成膜し、その上に金を成膜して、フォトリソグラフィー法とリフトオフ法により、ゲート端子(4)を形成した。
PETフィルム上に形成したTFTの室温下で測定した電流−電圧特性を測定した。ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型半導体であることが分かる。これは、In−Sn−O系アモルファス酸化物膜がn型伝導体であるという事実と矛盾しない。IDSはVDS=6V程度で飽和(ピンチオフ)する典型的なトランジスタの挙動を示した。また、Vg=0V時には、5×10−8A、VG=10V時には、IDS=5.0×10−5Aの電流が流れた。これはゲートバイアスにより絶縁体のIn−Sn−O系アモルファス酸化物膜内に電子キャリアを誘起できたことに対応する。
図5に示すトップゲート型TFT素子を作製した。まず、ポリエチレン・テレフタレート(PET)フィルム(1)上に、実施例6に示した成膜法により、チャンネル層(2)として用いる厚さ120nmのIn−Ga−O系アモルファス酸化物膜を形成した。さらにその上に、チャンバー内の酸素分圧を1Pa未満にして、さらに酸素ラジカル発生装置への印加電圧をゼロにして、PLD法により、電気伝導度の大きなIn−Ga−O系アモルファス酸化物膜及び金膜をそれぞれ30nm積層した。そして、フォトリソグラフィー法とリフトオフ法により、ドレイン端子(5)及びソース端子(6)を形成した。最後にゲート絶縁膜(3)として用いるY2O3膜を電子ビーム蒸着法により成膜し、その上に金を成膜して、フォトリソグラフィー法とリフトオフ法により、ゲート端子(4)を形成した。
PETフィルム上に形成したTFTの室温下で測定した電流−電圧特性を測定した。ドレイン電圧VDSの増加に伴い、ドレイン電流IDSが増加したことからチャネルがn型半導体であることが分かる。これは、In−Ga−O系アモルファス酸化物膜がn型伝導体であるという事実と矛盾しない。IDSはVDS=6V程度で飽和(ピンチオフ)する典型的なトランジスタの挙動を示した。また、Vg=0V時には、1×10−8A、VG=10V時には、IDS=1.0×10−6Aの電流が流れた。これはゲートバイアスにより絶縁体のIn−Ga−O系アモルファス酸化物膜内に電子キャリアを誘起できたことに対応する。
図7に記載の装置を用いて行う。
図5に示すトップゲート型MISFET素子を作製する。
KrFエキシマレーザーを用いたパルスレーザー蒸着法により、ガラス基板(コーニング社製1737)上に膜厚方向で組成分布を有するIn−Ga−Zn−O系アモルファス酸化物半導体薄膜を堆積する。このとき、InGaO3(ZnO)4組成を有する多結晶焼結体をターゲットとした。
アルゴンガスを用いたスパッタ蒸着法を用いる。
非晶質酸化物に添加物として窒素(N)を含む酸化物の製法について説明する。
KrFエキシマレーザーを用いたパルスレーザー蒸着法により、InGaO3(ZnO)4組成を有する多結晶焼結体をターゲットとして、ガラス基板(コーニング社製1737)上に、In−Ga−Zn−O系アモルファス酸化物半導体薄膜を堆積させる。
2 チャネル層
3 ゲート絶縁膜
4 ゲート電極(ゲート端子)
5 ドレイン電極(ドレイン端子)
6 ソース電極(ソース端子)
Claims (1)
- 電界効果型トランジスタであって、
活性層と、
前記活性層に対してゲート絶縁膜を介して設けられたゲート電極と、
前記活性層に接して前記ゲート電極の両側に設けられたソース電極及びドレイン電極とを具備し、
前記活性層は、In−Zn−O系酸化物、In−O系酸化物、In−Ga−O系酸化物、In−Zn−Sn−O系酸化物のうちのいずれかである非晶質酸化物を含み、前記非晶質酸化物は、微結晶を含み、前記微結晶は、微結晶粒界界面がアモルファス構造で覆われており、前記非晶質酸化物の電子キャリア濃度が1012/cm3以上、1018/cm3未満であり、更に、ゲート電圧無印加のドレイン・ソース端子間の電流が10マイクロアンペア未満、電界効果移動度が1cm2/(V・秒)超であることを特徴とする電界効果型トランジスタ。
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US11075303B2 (en) | 2016-03-02 | 2021-07-27 | Tokyo Institute Of Technology | Oxide semiconductor compound, semiconductor element provided with layer of oxide semiconductor compound, and laminated body |
KR20200088330A (ko) | 2017-11-28 | 2020-07-22 | 에이지씨 가부시키가이샤 | 박막 트랜지스터 |
KR20200088335A (ko) | 2017-11-28 | 2020-07-22 | 에이지씨 가부시키가이샤 | 반도체 화합물, 반도체 화합물의 층을 갖는 반도체 소자, 적층체 및 타깃 |
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