CN101123194A - 干蚀刻氧化物半导体膜的方法 - Google Patents
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Abstract
提供了含有至少In、Ga和Zn的氧化物半导体膜的干蚀刻法,其包括在含有卤素基气体的气氛中蚀刻氧化物半导体膜。
Description
技术领域
本发明涉及干蚀刻含有In、Ga和Zn的氧化物膜(下文称作“In-Ga-Zn-O”)的方法。特别地,本发明涉及干蚀刻用于制造精细电子部件,例如半导体器件、半导体集成电路和电极的含有In-Ga-Zn-O的氧化物半导体膜的方法。
背景技术
近年来,如日本专利申请公开No.2004-103957中公开的那样,含有In-Ga-Zn-O的半导体氧化物膜及其沉积条件的研究和开发已经广泛进行。特别由于半导体氧化物膜可以在低温下在树脂膜上形成,已经以半导体氧化物膜未来在轻重量的便携电子产品中的应用作为目标。
迄今已经通过剥离(lift-off)法进行含有In-Ga-Zn-O或Ga-Zn-O的制成薄膜的图案化。在例如K.Nomura等人,Nature,卷432,2004年11月25日,第488-492页,或E.M.C.Fortunato等人,AdvancedMaterials,2005,17,No.5,第590-594页中公开了剥离法。
日本专利申请公开No.H11-335874公开了使用含有甲烷的工艺气体进行传统透明导电氧化物膜例如氧化锌(ZnO)膜的干蚀刻法。
日本专利申请公开No.H03-077209公开了一种技术,其中当在玻璃基板上形成的含有ITO的透明导电薄膜经受干蚀刻法时,在加热ITO薄膜的同时使用氢气和碳氢化合物的混合气体进行反应性干蚀刻。此外,日本专利申请公开No.H10-087301公开了使用碘化氢干蚀刻含有SnO2、In2O3和ZnO作为主要成分的导电薄膜的技术。
在半导体膜的传统干蚀刻法中,在许多情况下使用氟基气体作为蚀刻介质。
但是,上述剥离法具有光致抗蚀剂在高温下熔化并变形的问题。剥离法具有另一问题,即在去除光致抗蚀剂时,沉积膜的图案边缘卷起,此后跨过图案边缘的电线容易断裂,这降低了产量。
此外,通过光刻法图案化的光致抗蚀剂被用作反应性离子蚀刻(RIE)的蚀刻掩模。在这种情况下,出现不挥发物质在蚀刻之后沉积在光致抗蚀剂表面上的问题,这导致即使用超声波清洗也难以去除光致抗蚀剂。
因此,为了加工含有In-Ga-Zn-O的薄膜,已经研究了用于获得具有高再现性和所需形状的图案的各种蚀刻方法。蚀刻方法大致分成两种方法。一种是湿蚀刻,其中将样品浸在化学试剂中,另一种是使用气态蚀刻介质的干蚀刻。原则上,在湿蚀刻中,蚀刻各向同性地进行,因此出现的一个问题是产生例如如下现象:掩模下方的底切、由掩模与被加工的薄膜之间的粘合不足引起的图案剥落、和蚀刻剂的渗透。出现的另一问题是蚀刻残留物漂浮或残留在器件表面上。因此,必须频繁更换蚀刻液,这导致蚀刻液的大量消耗。
另一方面,干蚀刻法具有如下优点:在等离子体中生成的化学活性离子垂直轰击基板表面,由此精确地从掩模图案上转移蚀刻形状。
作为普通干蚀刻法,使用RIE法。RIE的原理简单描述如下。将蚀刻气体引入带有平行板式电极的真空室,并对电极施加高频功率。在高频电场中加快到高速的电子使蚀刻气体由于电离而离子化以形成等离子态。等离子体中产生的自由基和离子在基板表面上引起蚀刻反应。主要蚀刻机制如下。一个机制是化学反应,其中活性物质被吸附到基板表面上以形成二次产物,随后释放。另一机制是物理反应,例如溅射效应,其中加速的正离子与基板碰撞以物理轰击基板。
但是,上述文件没有明确公开对In-Ga-Zn-O膜的干蚀刻。
此外,日本专利申请公开No.H03-077209中描述的干蚀刻法存在的问题是,在ITO没有加热的情况下,In和碳化合物副产物沉积在ITO薄膜上,这样难以获得具有所需形状的图案。此外,其中没有描述该方法对含有In-Ga-Zn-O的薄膜的适用性、其蚀刻速率等。
发明内容
为了解决上述问题,本发明提供了以高加工精确度加工含有In-Ga-Zn-O的薄膜的方法。此外,本发明还提供了使用含有卤素基气体的蚀刻气体以高蚀刻速率和高加工精确度干蚀刻含有In-Ga-Zn-O的薄膜的方法。
为了解决上述问题,通过对含有In-Ga-Zn-O的薄膜、该薄膜的沉积条件及其蚀刻条件的透彻研究,完成了本发明。
根据本发明,提供了蚀刻包含In、Ga和Zn的氧化物半导体膜的方法,其包括在含有卤素基气体的气氛中进行蚀刻。
从参照附图的示例性实施方案的下列描述中可以看出本发明的其它特征。
附图说明
图1是显示根据本发明的方法的一个例子的In-Ga-Zn-O膜的蚀刻速率和光致抗蚀剂的蚀刻速率的压力依赖性的特征图,也是显示对光致抗蚀剂的蚀刻选择性的压力依赖性的特征图。
图2是显示根据本发明的方法的一个例子的In-Ga-Zn-O膜、光致抗蚀剂和Si的蚀刻速率对偏压RF功率的依赖性的特征图,也是显示偏压RF功率与对光致抗蚀剂的蚀刻选择性之间的关系的特征图。
图3是显示根据本发明的方法的一个例子的蚀刻气体的Ar比率与In-Ga-Zn-O膜、光致抗蚀剂和Si的蚀刻速率之间的关系的特征图,也是显示蚀刻气体的Ar比率与对光致抗蚀剂的蚀刻选择性之间的关系的特征图。
具体实施方案
根据本发明,在使用含有卤素基气体的蚀刻气体的情况下,合意的压力条件在0.6Pa至2.4Pa的范围内。一旦压力低于0.6Pa,气体排放本身变成占支配地位,且不能在蚀刻装置中保持足以产生等离子体放电的气体量。另一方面,当压力高于2.4Pa时,中性气体没有被等离子体完全离解,并与离解离子碰撞,因此阻碍蚀刻速率。同时,可能容易地同时生成大量不挥发副产物。
一般而言,使用在氧化物膜表面上图案化的光致抗蚀剂层作为蚀刻掩模蚀刻氧化物半导体膜。除了有机光致抗蚀剂外,也可以使用氧化硅、非晶硅和氮化硅,只要其在蚀刻过程中对蚀刻等离子体保持耐受。
此外,蚀刻气体可以含有氢或惰性气体(例如Ar)。但是,在这种情况下,由于Ar气体的添加,可以获得对抗蚀剂的更高蚀刻选择性,但蚀刻速率降低。相应地,理想的是,确定哪种气体在生产率方面是合适的。此外,作为蚀刻气体,还可以使用含碳氢化合物(例如甲烷(CH4)或甲醇(CH3OH)蒸气)的气体。
根据本发明,可以显著改进带有含In-Ga-Zn-O的氧化物半导体膜作为活性层的半导体器件的产量。这对于大面积基板特别重要。半导体器件的活性层可以通过沉积法,例如溅射法、气相沉积法、CVD法、外延生长法、光致激发沉积法、脉冲激光沉积法和离子镀覆法制造。在这些方法中,溅射法在大规模生产能力方面是最优选的。
此外,由于含有In-Ga-Zn-O的氧化物半导体膜的电导率随温度而发生很大变化,需要在干蚀刻法过程中抑制温度升高。当温度升高时,含有In-Ga-Zn-O的氧化物半导体膜的电导率提高。特别地,当温度变成200℃或更高时,其电导率变得太高,结果带有In-Ga-Zn-O活性层的薄膜晶体管TFT不会转到断开状态。因此,需要将干蚀刻过程中的温度设定在低于200℃。此外,用作蚀刻掩模的光致抗蚀剂在高温下可能熔化并变形,因此优选将干蚀刻过程中的加工温度保持在低于150℃。
另一方面,一旦实现干蚀刻过程中的低温工艺,就可以使蚀刻断面保持垂直。当温度过度降低时,在蚀刻后不久可能在氧化物膜表面上发生冷凝,然后氧化物膜的电特性可能由于水分子的渗透性而改变。为了消除这种问题,必须提供加载互锁真空室以实现蚀刻室与大气压条件之间的抽真空和温度恢复,这使工艺操作变复杂并提高成本。此外,当干蚀刻法过程中的温度过度降低时,出现容易产生不挥发副产物的另外的问题。根据上述原因,干蚀刻法的温度合意地高于0℃。在不能提供加载互锁真空室的情况下,干蚀刻法的温度合意地高于200℃。
通过调节氧化物的组成和成膜条件,可以调节电导率。通过薄膜沉积条件的调节,可以得到载流子浓度为1013/cm3至1020/cm3的薄膜。在室温下,可以获得厚度为200纳米且电阻率为10-2至105Ωcm的含有In-Ga-Zn-O的无定形透明氧化物膜。为此,在带有含In-Ga-Zn-O的氧化物薄膜的TFT中,氧化物膜可以不仅用作活性层还用作具有高导电性的液晶的象素线。通常,在用于驱动正常液晶的TFT中,要求断态电流小于10-12A,并要求通态电流高于10-5A。通态电流和断态电流取决于器件的结构、尺寸和材料之类的因素。考虑到上述各种要求,在In-Ga-Zn-O氧化物膜用作TFT的活性层的情况下,氧化物膜的厚度合意地在5纳米或更高至400纳米或更低的范围内,更合意在10纳米或更高至300纳米或更低的范围内,最合意在20纳米或更高至200纳米或更低的范围内。根据本发明人的知识,在氧化物膜的厚度为400纳米或更高时,难以将断态电流抑制至10-12A或更低。另一方面,在氧化物膜的厚度为5纳米或更低时,难以将通态电流提高至10-5A。
作为氧化物薄膜的材料,可以在含In-Ga-Zn-O的化合物中添加至少一种杂质,例如Sn、Al、Sb、Cd、Ge、P、As、N和Mg。此外,理想的是,不刻意添加用于提高氧化物薄膜的电阻的杂质离子并在含氧气的气氛中进行薄膜沉积。
此外,在要制造使用含In-Ga-Zn-O的氧化物薄膜作为活性层的TFT的情况下,理想的是,氧化物半导体膜含有In-Ga-Zn-O并具有小于1018/cm3的电子载流子浓度。此外,出于相同原因,理想的是将透明无定形氧化物膜的电子载流子浓度设定至109/cm3或更高。
此外,只要通过等离子体制造卤素元素的自由基或离子且氧化物半导体膜中所含的金属原子可以被气化,就可以使用任何类型的等离子体源。例如,可以使用高频电感耦合等离子体(ICP)蚀刻装置和平行板的反应性离子蚀刻(RIE)装置。此外,也可以使用微波等离子蚀刻(电子回旋共振(ECR))装置和磁控管等离子蚀刻装置。此外,通过使用筒型等离子蚀刻装置、下流型(down flow)蚀刻装置等,可预计具有相同效果。
(实施例)
在下列描述中,描述了根据本发明的含有In-Ga-Zn-O的薄膜的干蚀刻法的具体实施例。但是,本发明不特别限于这些实施例。
首先,通过下述程序制造实验用样品。使用其上形成了厚度100纳米的Si氧化物膜的Si基板(厚度:525微米)作为基层。在表1中所示的条件下,通过反应性溅射法形成厚900纳米的In-Ga-Zn-O4薄膜。
表1
靶 | In-Ga-Zn-O4 |
基板温度 | 室温(60℃或更低) |
Ar流速 | 50sccm |
O2流速 | 0.6sccm |
压力 | 0.326Pa |
RF功率 | 150W |
时间 | 40分钟 |
膜厚度 | 900纳米 |
通过溅射成膜法和通过使用具有In-Ga-Zn-O4组成的多晶烧结体作为靶,在基板上沉积含有微晶的In-Ga-Zn-O基无定形氧化物半导体薄膜。此外,当对In-Ga-Zn-O基薄膜进行入射X-射线衍射(入射角:0.5度)时,没有发现明显的衍射峰。相应地,可以说,由此制成的In-Ga-Zn-O基薄膜是无定形的。
接着,通过已知光刻法在In-Ga-Zn-O膜上形成线宽3微米且间隙宽度3微米的线-间隙(line-and-space)抗蚀图。作为抗蚀剂,使用正抗蚀剂AZ1500(20cp)(商品名;Clariant International Ltd.制造)。使用焙烧炉在大约120℃对带有抗蚀剂的Si基板进行硬焙烧,由此制造实验用样品。硬焙烧法用于改进抗蚀剂在随后进行的反应性干蚀刻过程中的耐等离子体性。
接着,用含氯的蚀刻气体,对在由此制成的样品上从抗蚀图中暴露出来的In-Ga-Zn-O膜进行干蚀刻。所用干蚀刻装置是高频电感偶合等离子体(ICP)系统(其使用上部线圈作阳极并将基板放在阴极上进行操作)的RIE-101iP-CIP蚀刻系统(商品名;SAMCO Inc.制造)。分别对阳极和阴极使用具有13.56MHz高频的电源,可以稳定地控制高密度等离子体和偏压。施加到线圈(阳极)上的高频功率被称作“ICPRF功率”,施加到紧接基板下方放置的支承件(阴极)上的高频功率被称作“偏压RF功率”。当施加到ICP线圈上的RF功率提高时,等离子体中离子和自由基的离解程度提高。
接着,将样品放在室中并抽真空。在达到1×10-4pa或更低的足够真空度后,使各自的气体流动以激发等离子体,由此在各种条件下进行蚀刻。
在完成蚀刻后,用丙酮除去每一样品的抗蚀剂,并测量和观察In-Ga-Zn-O膜的图案。用KLA-Tencor公司制造的表面轮廓仪测量由蚀刻形成的阶梯(step),由此准确计算干蚀刻速率。根据实验条件,可以明显看出下述适当的蚀刻条件。此外,不仅测量对In-Ga-Zn-O膜的蚀刻速率,还测量对Si的蚀刻速率。
在实验1中,研究压力依赖性。作为实验条件,设定温度为35℃,纯氯流速为20sccm,ICP RF功率为300W,偏压RF功率为30W。值得考虑的结果显示在图1中。在图1中,横坐标表示室压力,左侧纵坐标表示蚀刻速率,右侧纵坐标表示对抗蚀剂的蚀刻选择性。在0.6Pa至5Pa的范围内调节压力。根据该实验,在压力为0.6Pa或更低的情况下,等离子体变得不稳定或有时不能被激发。另一方面,在压力为5Pa或更高的情况下,等离子体变暗或有时不能被激发。从图1中看出,对In-Ga-Zn-O(IGZO)膜的蚀刻速率比对抗蚀剂(PR)的蚀刻速率小得多。蚀刻速率之间的比率表示为右侧纵坐标所示的对抗蚀剂的蚀刻选择性。在0.6Pa至2.4Pa的压力范围内,对抗蚀剂的选择性据测为0.13或更大。特别在压力为1Pa的情况下,可以获得0.22的对抗蚀剂的合意选择性。
根据上述实验结果,蚀刻过程中最合意的室压力条件在0.6Pa至2.4Pa的室压力范围内。在这种情况下,可以看出,对抗蚀剂的选择性为0.13或更大。考虑到实际蚀刻条件和等离子体激发条件,在上述压力范围内获得对抗蚀剂的高选择性是合意的。
在实验2中,研究对施加到基板侧上的偏压RF功率的依赖性。作为实验条件,设定温度为35℃,纯氯流速为20sccm,ICP RF功率为300W,压力为0.8Pa。值得考虑的结果显示在图2中。在图2中,横坐标表示偏压RF功率,左侧纵坐标表示蚀刻速率,右侧纵坐标表示对抗蚀剂的蚀刻选择性。从图2中看出,具有在偏压RF功率变大时整体蚀刻速率和对抗蚀剂的选择性也提高的趋势。这可能是因为当RF功率大时,等离子体中的离子具有更大的动能,由此获得大的物理撞击效果。
从图2中看出,当偏压RF功率接近0时,蚀刻速率也接近0。这是因为,在偏压RF功率为0的情况下,即使在ICP RF功率提高时,等离子体中的离子也未加速,由此没有表现出物理撞击的蚀刻效果。特别是对于In-Ga-Zn-O膜,物理撞击的效果大于化学腐蚀反应的效果。换言之,对基板侧施加偏压RF功率是可靠地进行蚀刻的必要条件之一。如图2中所示,在偏压RF功率为2W时,对In-Ga-Zn-O膜的蚀刻速率仅为1.03纳米/分钟,这是该实施例中的最小蚀刻速率。顺便提及,位于基板侧上的电极的直径为4英寸,当偏压RF功率为2W时,偏压RF功率密度为大约0.02W/Gm2。
适用于大规模制造的高速蚀刻法是合意的。从实验结果看出,合意的偏压RF功率密度为0.02W/cm2或更高,最合意的偏压RF功率密度为0.2W/cm2或更高。当偏压RF功率密度变高并超出本发明的范围时,光致抗蚀剂在高温下熔化并形变,且有时不能精确地进行蚀刻。
另一方面,如图2中所示,在偏压RF功率为120W(大约6W/cm2的功率密度)时,对In-Ga-Zn-O膜的蚀刻速率为120纳米/分钟。
从图2中看出,对Si的蚀刻速率与对抗蚀剂的蚀刻速率彼此接近。相应地,Si具有与抗蚀剂相同的对氯等离子体的抗蚀刻能力。
在实验3中,研究了在氯气中加入Ar气体的效果。作为实验条件,设定温度为35℃,压力为0.8Pa,混合气体的总流速为20sccm,ICP RF功率为300W,偏压RF功率为30W。值得考虑的结果显示在图3中。在图3中,横坐标表示Ar的流速,左侧纵坐标表示蚀刻速率,右侧纵坐标表示对抗蚀剂的选择性。从图3中看出,当Ar的比例提高时,对Si的蚀刻速率和对抗蚀剂的蚀刻速率迅速降低。相应地,对抗蚀剂的蚀刻选择性也提高的趋势是显著的。具有随着Ar比率提高,整体蚀刻速率降低且两个值彼此靠近的趋势。因此,对抗蚀剂的选择性经证实接近1。在用纯Ar进行蚀刻的情况下,可以获得0.96的对抗蚀剂的最大选择性。另一方面,在氯的比率大时,对于Si和抗蚀剂,化学腐蚀反应的效果大于物理撞击的效果。因此,对Si的蚀刻速率大于对抗蚀剂的蚀刻速率。此外,从图3中看出,在Ar的比率为25%的情况下,对In-Ga-Zn-O膜的蚀刻速率达到最大。通过添加Ar,等离子体的离解程度变高,由此可以获得具有高密度的等离子体。当添加过量Ar时(在25%或更高的情况下),氯自由基或离子的化学蚀刻效果变小,这降低了对In-Ga-Zn-O膜的蚀刻速率。
与图2的结果类似,从图3中也看出,Si和抗蚀剂的耐等离子体蚀刻趋势彼此接近。作为蚀刻掩模,可以使用如非晶硅、氧化硅和氮化硅之类的材料代替有机抗蚀剂。在图3中,在极端情况下,也就是在用纯Ar进行蚀刻的情况下,对In-Ga-Zn-O膜、光致抗蚀剂和硅各自的蚀刻速率相同。根据该实施例的实验1至3的结果,对In-Ga-Zn-O膜的光致抗蚀剂的蚀刻选择性在0.03至0.98的范围内。此外,光致抗蚀剂的必需膜厚度为In-Ga-Zn-O膜的厚度的大约1.0至33.4倍。因此,要求蚀刻掩模(例如光致抗蚀剂)的膜厚度等于或大于In-Ga-Zn-O膜的厚度。
在整个干蚀刻法完成后,用光学显微镜和扫描电子显微镜观察样品。结果,在充当蚀刻掩模的抗蚀剂的表面上,没有观察到不挥发沉积物。
此外,在整个干蚀刻法中,为了稳定基板的温度,使冷却剂在基板支承件内部流动并将基板温度设定至大约35℃。当用300W的线圈RF功率和30W的偏压RF功率进行蚀刻4分钟后用Thermo Label(former Nicihyu Giken Kogyo Co.,Ltd制造)测量温度时,可以看出,温度升至大约55℃,其是根据该实施例的蚀刻法的最大温度。
尽管该实施例中主要使用的蚀刻气体源是氯气,但只要可以通过等离子体产生卤素元素的自由基或离子,就可以使用任何其它来源。例如,通过使用氟气(F2)、HBr、HI、HCI、SiCl4、CF2Cl2、CF4或类似物,预计具有相同效果。
如果使用高频等离子体干蚀刻含有In-Ga-Zn-O的薄膜时的等离子体功率密度为2W/cm2或更高,就可以在实际应用中高速进行干蚀刻。
根据本发明,可以防止由反应沉积物引起的副作用。由此,在干蚀刻含有In-Ga-Zn-O的薄膜的情况下,可以在高蚀刻速率下以高均匀性进行干蚀刻。
例如,在晶体管器件的制造方法中——其中使用含有In-Ga-Zn-O的氧化物半导体膜作为在基板上形成的薄膜晶体管的通道层,可以进行具有高再现性的更实用的蚀刻。
根据本发明,可以获得含有In-Ga-Zn-O并在基板上形成的氧化物半导体膜的干蚀刻法,并可以提供以稳定性和均匀电特性在基板上形成的半导体器件。
例如,本发明可以首先用于TFT(其中透明氧化物膜在软塑料膜上形成并充当活性层),并可进一步用于挠性显示器的象素驱动器、认证用IC卡、产品ID标签和类似物的领域。
当参照示例性实施方案描述本发明时,要理解的是,本发明不限于所公开的示例性实施方案。对下列权利要求的范围要给予最广义的解读以包含所有这类修改和对等的结构和功能。
Claims (8)
1.干蚀刻包含In、Ga、和Zn的氧化物半导体膜的方法,其包括在含有卤素基气体的气氛中进行蚀刻。
2.根据权利要求1的干蚀刻法,其中蚀刻过程中的反应压力在0.6Pa或更高至2.4Pa或更低的范围内。
3.根据权利要求1的干蚀刻法,其中在蚀刻过程中以0.02W/cm2或更高的密度对基板侧施加偏压RF功率。
4.根据权利要求1的干蚀刻法,其中在用包含选自有机光致抗蚀剂、氧化硅、非晶硅、和氮化硅的材料的蚀刻掩模覆盖氧化物半导体膜的部分表面的同时,进行蚀刻。
5.根据权利要求4的干蚀刻法,其中蚀刻掩模的厚度等于或大于氧化物半导体膜的厚度。
6.根据权利要求1的干蚀刻法,其中在蚀刻过程中氧化物半导体膜的表面温度保持在0℃或更高至小于200℃的范围内。
7.根据权利要求1的干蚀刻法,其中氧化物半导体膜具有小于1018/cm3的电子载流子浓度。
8.根据权利要求1的干蚀刻法,其中氧化物半导体膜的厚度在5纳米或更高至400纳米或更低的范围内。
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Also Published As
Publication number | Publication date |
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US20080038929A1 (en) | 2008-02-14 |
CN100514582C (zh) | 2009-07-15 |
JP2008042067A (ja) | 2008-02-21 |
US7767106B2 (en) | 2010-08-03 |
JP4999400B2 (ja) | 2012-08-15 |
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