TWI575605B - 用於低蝕刻速率硬遮罩膜之具有氧摻雜之pvd氮化鋁膜 - Google Patents
用於低蝕刻速率硬遮罩膜之具有氧摻雜之pvd氮化鋁膜 Download PDFInfo
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Description
本發明實施例大體而言係有關於一摻雜的氮化鋁硬遮罩以及製造一摻雜的氮化鋁硬遮罩的方法。
隨著半導體元件尺寸持續縮小,形成此類小尺寸元件所需的精準度增加。不僅縮小半導體晶片尺寸變得益發困難,更有甚者,形成電氣互連的個別特徵也變得益發困難。
製造一半導體晶片需執行眾多製程。圖案化是該等製程其中之一。在一圖案化製程中,一遮罩,例如一硬遮罩,係形成在欲加以圖案化的一或多個層上方。之後,使用該硬遮罩讓該或該等下層暴露在一蝕刻劑中,以除去暴露材料(即,未受該硬遮罩或光遮罩覆蓋的材料)並轉印該硬遮罩的圖案至該或該等下層。
在理想的蝕刻製程中,暴露材料被蝕刻而該硬遮罩不被蝕刻。換句話說,該硬遮罩理想上對該蝕刻劑是惰性的,其可採用液態蝕刻劑或氣態蝕刻劑的型態。若該硬遮罩對於該蝕刻劑是惰性的,則該硬遮罩的特徵可相當順利地轉印至該或該等下層。
自然地,製造一化學惰性的硬遮罩並不便利。因此,預期一些硬遮罩蝕刻。由於硬遮罩經過蝕刻,圖案轉印的精準度便受到折衷。
因此,技藝中需要一種對用來從硬遮罩轉印圖案至下層的蝕刻製程更具化學惰性的硬遮罩。
本發明大體而言係有關於一摻雜的氮化鋁硬遮罩以及製造一摻雜的氮化鋁硬遮罩的方法。藉由在形成該氮化鋁硬遮罩時添加少量摻雜劑,例如氧,該硬遮罩的溼蝕刻速度可顯著降低。此外,與一無摻雜的氮化鋁硬遮罩相比,由於摻雜劑的存在,該硬遮罩的粒徑縮小。縮小的粒徑使硬遮罩內的特徵更平滑,導致使用該硬遮罩時更為精準的下層蝕刻。
在一實施例中,一硬遮罩包含氮化鋁與摻雜劑。在另一實施例中,製造一硬遮罩的方法包含在含有一惰性氣體、一含氮氣體、及一含氧氣體的環境中濺射一鋁靶材,以形成一氧摻雜的氮化鋁材料,其中含氮氣體量係含氧氣體量的兩倍以上。該方法另外包含圖案化該氧摻雜的氮化鋁材料以形成該硬遮罩。
在另一實施例中,製造一硬遮罩的方法包含在含有一惰性氣體、一含氮氣體、及一含氧氣體的環境中濺射一氮化鋁靶材,以形成一氧摻雜的氮化鋁材料,其中含氮氣體量係含氧氣體量的兩倍以上。該方法另外包含圖案化該氧摻雜的氮化鋁材料以形成該硬遮罩。
100‧‧‧PVD設備
102‧‧‧腔室主體
104‧‧‧氣源
106‧‧‧背板
108‧‧‧靶材
110‧‧‧電源
112‧‧‧基板支撐
114‧‧‧基板
116‧‧‧電源
202‧‧‧層
204‧‧‧硬遮罩
206‧‧‧特徵
208‧‧‧暴露部分
因此可以詳細暸解上述本發明之特徵的方式,即對本發明更明確的描述,簡短地在前面概述過,可藉由參考實施例來得到,其中某些在附圖中示出。但應注意到,附圖僅示出本發明之一般實施例,因此不應視為係對其範圍之限制,因為本發明可允許其他等效實施例。
第1圖係根據一實施例的物理氣相沉積(PVD)設備的概要剖面圖。
第2圖係形成在一層上方的硬遮罩的概要剖面圖。
第3A和3B圖分別示出一未摻雜的氮化鋁薄膜及一氧摻雜的氮化鋁薄膜的微粒結構。
為了促進了解,在可能時使用相同的元件符號來表示該等圖式共有的相同元件。預期到在一實施例中揭示的元件可有利地用於其他實施例而不需特別詳述。
本發明大體而言係有關於一摻雜的氮化鋁硬遮罩以及製造一摻雜的氮化鋁硬遮罩的方法。藉由在形成該氮化鋁硬遮罩時添加少量摻雜劑,例如氧,該硬遮罩的溼蝕刻速度可顯著降低。此外,與一無摻雜的氮化鋁硬遮罩相比,由於摻雜劑的存在,該硬遮罩的粒徑縮小。縮小的粒徑使硬遮罩內的特徵更平滑,導致使用該硬遮罩時更為精準的下層蝕刻。
第1圖係根據一實施例的PVD設備100的概要剖面圖。該設備100包含一腔室主體102。氣體係從一氣源104輸送至該腔室主體102。一濺射靶材108係設置在該腔室主體102內與基板114相對。該濺射靶材108係接合至一背板106。
一偏壓係從一電源110施加至該背板106。該基板114係設置在一基板支撐112上。該基板支撐112可由一電源116偏壓。應了解該基板支撐112可電氣浮接或直接接地。該電源110可包含一DC電源、一脈衝DC電源、一AC電源或一RF電源。該背板106係導電的。
如上所述,在此揭示的實施例係有關於一種硬遮罩與形成該硬遮罩的方法。第2圖係形成在一層202上方的硬遮罩204的概要剖面圖。該硬遮罩204係經圖案化而使一特徵206形成在其中,以暴露該層202的部分208。在一實施例中,該層202可包含鎢。在另一實施例中,該層202可包含多晶矽。該硬遮罩204包含摻雜的氮化鋁。該摻雜劑可包含一或多種選自氧、矽、氟、碳、及其組合物所組成的群組之摻雜劑。該硬遮罩204可包含多至25原子百分比的量之摻雜劑。
該摻雜劑擁有若干益處。當該摻雜劑是氧時,氧可控制該硬遮罩204的應力。當缺乏氧做為摻雜劑時,該未摻雜的氮化鋁硬遮罩會有約400MPa的張應力。但是,氧可顯著減少應力至非常低的張應力或甚至是壓應力。在一實施例中,應力水準係約0,因此該硬遮罩204內實質上無應力。該硬遮罩204的應力抵銷所有下層的殘餘應力。因此,可調整該硬遮罩204的應力以抵銷其上設置該硬遮罩204的結構之應力。
此外,氧摻雜劑縮小所形成的硬遮罩204的粒徑。明確地說,與一未摻雜的氮化鋁硬遮罩相比,一氧摻雜的氮化鋁硬遮罩擁有較小的粒徑。以XRD(X光繞射)分析測量時,
一未摻雜的氮化鋁硬遮罩擁有[0002]尖峰。但是,一氧摻雜的氮化鋁硬遮罩,雖仍有[0002]尖峰,但其[0002]尖峰的高度是未摻雜的氮化鋁硬遮罩[0002]尖峰的約1/10。此外,氧摻雜的氮化鋁硬遮罩的密度係低於該未摻雜的氮化鋁硬遮罩的密度。
由於該氧摻雜劑的存在,所形成的硬遮罩有較小粒徑(與一未摻雜的氮化鋁硬遮罩相比),這使特徵206更平滑,因而導致在蝕刻該下層202的圖案化製程期間該下層202較尖銳且較平直的蝕刻。此外,與未摻雜的氮化鋁硬遮罩相比,該氧摻雜的氮化鋁硬遮罩擁有低許多的蝕刻速度。明確地說,該氧摻雜的氮化鋁硬遮罩在一稀釋的氟化氫溶液(100:1)中之溼蝕刻速度是每分鐘約4埃,而一未摻雜的氮化鋁硬遮罩的濕蝕刻速度是每分鐘約18埃。在一實施例中,因此,如上所述般,雖然一完全惰性的硬遮罩無法由添加例如氧的摻雜劑形成,但蝕刻耐受度好很多的硬遮罩係藉由使用例如氧的摻雜劑來形成。由於該更耐蝕刻的硬遮罩,該氧摻雜的氮化鋁硬遮罩在蝕刻製程期間維持其結構(優於一未摻雜的氮化鋁硬遮罩),因而在該下層202內造成界定較佳的特徵。
在形成該氧摻雜的氮化鋁硬遮罩時,使用如此微量的氧因而僅有少量至無鋁一氧鍵形成。可藉由在其上含有該層202的基板114對面提供一鋁靶材108來形成該硬遮罩204。從一氣源104將一惰性氣體,一含氮氣體、及一含氧氣體全體引進該腔室主體102。從一電源110施加一電偏壓至該背板106,而該基板114係在該基板支撐112上電氣接地。該
電源110施加一DC電偏壓至該濺射靶材108,以在該腔室主體內產生一電漿並從該靶材108彈射出鋁原子。該等鋁原子與氮反應形成氮化鋁。氧沒有與鋁反應因而摻雜形成在該基板114上的氮化鋁層。在一實施例中,該靶材108可包含氮化鋁,而該電源110包含一RF電源。在一實施例中,該濺射靶材可在一毒化模式(poisoned mode)下運作,此時該靶材包含鋁,但一氮化鋁膜形成在該暴露的靶材表面上。因此,在濺射製程開始時,從該濺射靶材濺射出氮化鋁。
在一實施例中,該含氮氣體包含氮氣而該含氧氣體包含氧氣。該惰性氣體可包含氬氣。惰性氣體對含氮氣體的比例可介於約1:1至約1:20間。在一實施例中,惰性氣體對含氮氣體的比例可以是約1:5。含氮氣體對含氧氣體的比例係大於2:1並且可介於約100:1至約20:1間。在一實施例中,含氮氣體對含氧氣體的比例可以是約50:3。
一旦沉積,該氧摻雜的硬遮罩可擁有高至約25原子百分比的氧含量。在一實施例中,氧含量可高至約10原子百分比。可維持該腔室主體102的腔室壓力在約1毫托耳和約100毫托耳間,以及基板支撐112溫度在約攝氏25度和約攝氏500度間。可從電源110施加約1千瓦和約20千瓦間的電力至該濺射靶材108。所形成的摻雜的氮化鋁硬遮罩是多晶的。第3A和3B圖分別示出一未摻雜的氮化鋁薄膜及一氧摻雜的氮化鋁薄膜的微粒結構。如第3B圖所示,粒徑顯著縮小。
藉由使用一摻雜劑,例如氧,可製造出與一未摻雜的氮化鋁硬遮罩相比蝕刻速度較慢的氮化鋁硬遮罩。此外,
該摻雜的氮化鋁硬遮罩有較小的粒徑,因此,圖案化時有更平滑的表面。由此,該摻雜的氮化鋁硬遮罩,雖然並非化學惰性,但可容許更細微、更複雜的特徵在一圖案化製程期間形成在其下的層內。
雖然前述係針對本發明實施例,但本發明的其他及進一步實施例可在不背離其基本範圍下設計出,而其範圍係由如下申請專利範圍判定。
202‧‧‧層
204‧‧‧硬遮罩
206‧‧‧特徵
208‧‧‧暴露部分
Claims (20)
- 一種硬遮罩,包含:一多晶氮化鋁,其包含一摻雜劑。
- 如請求項1所述之硬遮罩,其中該摻雜劑係選自氧、矽、氟、碳、及其組合物所組成的群組。
- 如請求項2所述之硬遮罩,其中該摻雜劑包含氧。
- 如請求項3所述之硬遮罩,其中該氧係以高至25原子百分比的量存在。
- 如請求項4所述之硬遮罩,其中該硬遮罩擁有一[0002]尖峰,該尖峰係小於由未摻雜的氮化鋁硬遮罩構成的一硬遮罩之一[0002]尖峰。
- 如請求項5所述之硬遮罩,其中該硬遮罩擁有一粒徑,該粒徑係小於一未摻雜的氮化鋁硬遮罩的一粒徑。
- 如請求項6所述之硬遮罩,其中該摻雜的氮化鋁硬遮罩的該[0002]尖峰之尺寸係該未摻雜的氮化鋁硬遮罩的該[0002]尖峰之尺寸的約1/10。
- 如請求項1所述之硬遮罩,其中該硬遮罩擁有介於約-5 MPa和約5MPa之間的一應力。
- 一種製造一硬遮罩的方法,包含:在含有一惰性氣體、一含氮氣體、及一含氧氣體的一氣氛中濺射一鋁靶材,以沉積一氧摻雜的多晶氮化鋁材料,其中該含氮氣體的量係該含氧氣體的量的兩倍以上;及圖案化該氧摻雜的多晶氮化鋁材料,以形成該硬遮罩。
- 如請求項9所述之方法,其中該含氮氣體包含氮氣。
- 如請求項10所述之方法,其中該含氧氣體包含氧氣。
- 如請求項11所述之方法,其中該惰性氣體對氮氣的比例係介於約1:1至約1:20間。
- 如請求項12所述之方法,其中該惰性氣體對氮氣的比例係約1:5。
- 如請求項13所述之方法,其中氮氣對氧氣的比例係介於約100:1至約20:1間。
- 如請求項14所述之方法,其中氮氣對氧氣的比例係約50:3。
- 如請求項9所述之方法,其中該濺射係在介於約攝氏25度和約攝氏500度之間的溫度下發生。
- 如請求項16所述之方法,其中該濺射係在介於約1毫托耳和約100毫托耳之間的一腔室壓力下發生。
- 如請求項9所述之方法,其中該濺射係直流濺射或脈衝直流濺射。
- 一種製造一硬遮罩的方法,包含:在含有一惰性氣體、一含氮氣體、及一含氧氣體的一氣氛中濺射一氮化鋁靶材,以形成一氧摻雜的多晶氮化鋁材料,其中該含氮氣體的量係該含氧氣體的量的兩倍以上;及圖案化該氧摻雜的多晶氮化鋁材料,以形成該硬遮罩。
- 如請求項19所述之方法,其中該濺射係射頻濺射。
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US11851785B2 (en) | 2021-05-21 | 2023-12-26 | Raytheon Company | Aluminum nitride passivation layer for mercury cadmium telluride in an electrical device |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010034106A1 (en) * | 1999-12-22 | 2001-10-25 | Theodore Moise | Hardmask designs for dry etching FeRAM capacitor stacks |
TW548722B (en) * | 2001-07-07 | 2003-08-21 | Trikon Holdings Ltd | Method of depositing aluminium nitride |
TW200839874A (en) * | 2007-03-16 | 2008-10-01 | Au Optronics Corp | Manufacturing method for low leakage aluminum nitride dielectric layer |
US20110031109A1 (en) * | 2008-04-21 | 2011-02-10 | Honeywell International Inc. | Design and use of dc magnetron sputtering systems |
US20110042200A1 (en) * | 2008-03-25 | 2011-02-24 | Anthony Wilby | Method of depositing amorphus aluminium oxynitride layer by reactive sputtering of an aluminium target in a nitrogen/oxygen atmosphere |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6177351B1 (en) * | 1997-12-24 | 2001-01-23 | Texas Instruments Incorporated | Method and structure for etching a thin film perovskite layer |
KR100646296B1 (ko) * | 2001-09-12 | 2006-11-23 | 닛본 덴끼 가부시끼가이샤 | 반도체 장치 및 그 제조 방법 |
JP4024510B2 (ja) * | 2001-10-10 | 2007-12-19 | 株式会社半導体エネルギー研究所 | 記録媒体、および基材 |
KR100532446B1 (ko) * | 2003-07-10 | 2005-11-30 | 삼성전자주식회사 | 반도체 소자의 금속배선층 형성방법 |
US7157366B2 (en) * | 2002-04-02 | 2007-01-02 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection layer of semiconductor device |
US6576482B1 (en) * | 2002-05-07 | 2003-06-10 | Texas Instruments Incorporated | One step deposition process for the top electrode and hardmask in a ferroelectric memory cell |
US20030221620A1 (en) * | 2002-06-03 | 2003-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Vapor deposition device |
US7045406B2 (en) | 2002-12-03 | 2006-05-16 | Asm International, N.V. | Method of forming an electrode with adjusted work function |
US6927651B2 (en) * | 2003-05-12 | 2005-08-09 | Agilent Technologies, Inc. | Acoustic resonator devices having multiple resonant frequencies and methods of making the same |
CN100407374C (zh) * | 2003-08-29 | 2008-07-30 | 日本电气株式会社 | 氮化物半导体基底以及使用该基底的氮化物半导体装置 |
KR100753152B1 (ko) * | 2005-08-12 | 2007-08-30 | 삼성전자주식회사 | 질화물계 발광소자 및 그 제조방법 |
KR100636796B1 (ko) * | 2005-08-12 | 2006-10-20 | 한양대학교 산학협력단 | 반도체 소자 및 그 제조방법 |
JP4997448B2 (ja) * | 2007-12-21 | 2012-08-08 | 独立行政法人産業技術総合研究所 | 窒化物半導体の製造方法および窒化物半導体デバイス |
JP2011044493A (ja) * | 2009-08-19 | 2011-03-03 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
KR20180054919A (ko) | 2010-04-23 | 2018-05-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 |
KR101806271B1 (ko) | 2010-05-14 | 2017-12-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 |
CN102263175A (zh) * | 2010-05-26 | 2011-11-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Led衬底及其制备方法 |
WO2012017844A1 (en) | 2010-08-06 | 2012-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8422272B2 (en) | 2010-08-06 | 2013-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method thereof |
US8467231B2 (en) | 2010-08-06 | 2013-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method thereof |
US8467232B2 (en) | 2010-08-06 | 2013-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8446171B2 (en) | 2011-04-29 | 2013-05-21 | Semiconductor Energy Laboratory Co., Ltd. | Signal processing unit |
-
2013
- 2013-04-18 CN CN201380014792.1A patent/CN104170068B/zh active Active
- 2013-04-18 KR KR1020147030614A patent/KR102073414B1/ko active IP Right Grant
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- 2013-04-18 EP EP13782077.5A patent/EP2842158A4/en not_active Withdrawn
- 2013-04-22 US US13/867,606 patent/US9162930B2/en active Active
- 2013-04-24 TW TW102114631A patent/TWI575605B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010034106A1 (en) * | 1999-12-22 | 2001-10-25 | Theodore Moise | Hardmask designs for dry etching FeRAM capacitor stacks |
TW548722B (en) * | 2001-07-07 | 2003-08-21 | Trikon Holdings Ltd | Method of depositing aluminium nitride |
TW200839874A (en) * | 2007-03-16 | 2008-10-01 | Au Optronics Corp | Manufacturing method for low leakage aluminum nitride dielectric layer |
US20110042200A1 (en) * | 2008-03-25 | 2011-02-24 | Anthony Wilby | Method of depositing amorphus aluminium oxynitride layer by reactive sputtering of an aluminium target in a nitrogen/oxygen atmosphere |
US20110031109A1 (en) * | 2008-04-21 | 2011-02-10 | Honeywell International Inc. | Design and use of dc magnetron sputtering systems |
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