CN101258606A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101258606A
CN101258606A CNA2006800324606A CN200680032460A CN101258606A CN 101258606 A CN101258606 A CN 101258606A CN A2006800324606 A CNA2006800324606 A CN A2006800324606A CN 200680032460 A CN200680032460 A CN 200680032460A CN 101258606 A CN101258606 A CN 101258606A
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张建六
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Canon Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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Abstract

在本发明中，在塑料膜衬底(1)上形成薄膜晶体管，在所述塑料膜衬底(1)的面内方向中具有热收缩率或热膨胀系数的各向异性。形成沟道，使得所述衬底的热收缩率或热膨胀系数最大的方向(7)不平行于流过该薄膜晶体管的电流的方向(8)。于是，提供了在塑料膜衬底上形成的具有稳定且一致的电学特性的薄膜晶体管。

Description

半导体器件
技术领域
本发明涉及一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底上形成的半导体器件。
背景技术
近年来，设置在柔性且重量轻的衬底上的发光器件、显示板等已经处于活跃的研究和开发之下。例如，用包含ZnO作为主要材料的透明导电氧化物多晶薄膜作为沟道层的薄膜晶体管(TFT)已经被活跃地开发(见日本专利申请特许公开No.2002-76356)。
薄膜可以在低温下形成且对可见光透明，因此其使得可以在诸如塑料板或膜之类的衬底上形成柔性透明的TFT。
另一方面，通过汽相方法在膜形柔性衬底上形成的薄膜具有这样的问题：衬底由于薄膜中存在的残余应力而扭曲。作为解决该问题的一种方式，提出了一种在膜形成过程期间通过弯曲衬底来抵消或补偿残余内部应力的方法(日本专利申请特许公开No.H06-280026)。
发明内容
本发明的一个目的是提供一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底上形成的具有稳定的半导体器件特性的半导体器件，且本发明还提供一种制造半导体器件的方法。
当使用诸如塑料板或树脂膜之类的柔性衬底时，关于包括衬底的薄膜叠层的弯曲、由于例如热收缩或热膨胀而导致的尺寸变化、以及残余应力的因素对其上的器件具有负面影响。具体而言，当使用通过将热塑型树脂熔融处理成片形并沿纵向和横向方向双轴拉伸该热塑型树脂而获得的塑料膜作为衬底时，该负面影响可能很显著。这是因为由于双轴拉伸处理，导致热收缩率或热膨胀系数沿面内方向改变。例如，衬底尺寸的变化导致其上形成的半导体器件在电流流动路径的长度和宽度的变化、半导体的压电电阻的变化等等。因此，所制造的器件将不同于其原始设计。例如，当热收缩衬底缩短了漏极和源极之间的沟道时，寄生电容变大或截止频率减小。
一般而言，半导体器件制造工艺包括很多高温工艺。即，每个工艺包括室温变换到高温以及高温变换到室温的温度循环。因此，在面内方向中具有热收缩率或热膨胀系数的各向异性的衬底按照温度循环而膨胀和收缩，由此改变了衬底的尺寸。因而，半导体器件的尺寸变化、变形、内部扭曲以及应力受到影响，如上所述，使得半导体器件的特性受到负面影响。
本发明用于通过根据流过衬底上的半导体器件的电流的方向精巧地设计布图，来抑制半导体器件的尺寸变化、变形、内部扭曲、应力等的影响。
下面，将具体描述本发明。
根据本发明的一个方面，提供了一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底的表面上形成的半导体器件，所述半导体器件的特征在于，所述衬底的热收缩率或热膨胀系数最大的方向不平行于流过该半导体器件的电流的方向。
根据本发明的另一方面，还提供了一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底的表面上形成的半导体器件，所述半导体器件的特征在于，所述衬底的热收缩率或热膨胀系数最小的方向平行于流过该半导体器件的电流的方向。
在本发明中，半导体器件包括诸如MOSFET、薄膜晶体管(TFT)、紫外线传感器、太阳能电池或离子敏感晶体管之类的众所周知的电学器件。
根据本发明，可以避免由热收缩或热膨胀导致的不利影响。因此，可以获得均匀且高度稳定的半导体器件，其寿命延长，其产率改善。
本发明的其它特征和优点将从下面结合附图的详细描述变得更加清晰，在所有附图中，附图标记代表了相同或相似的部分。
附图说明
附图被包括在说明书中并组成该说明书的一部分，附图图解说明了本发明的实施例，并与文字说明一起用于解释本发明的原理。
图1是示出了根据本发明的实施例和例子1的顶部栅极TFT的截面图，其中使用在塑料膜衬底上形成的非晶In-Ga-Zn-O薄膜作为沟道；
图2是示出了根据本发明的实施例和例子1的TFT的顶视图。
图3是示出了例子1(θ＝90°)中制造的TFT的电流(IDS)-电压(VDS)特性的曲线图；
图4是示出了例子1(θ＝90°)中制造的TFT的电流(IDS)-电压(VGS)特性的曲线图；
图5是示出了例子2(θ＝45°)中制造的TFT的电流(IDS)-电压(VDS)特性)的曲线图；
图6是示出了例子2(θ＝45°)中制造的TFT的电流(IDS)-电压(VGS)特性)的曲线图；
图7是示出了对比例(θ＝0°)中制造的TFT的电流(IDS)-电压(VDS)特性)的曲线图；
图8是示出了对比例(θ＝0°)中制造的TFT的电流(IDS)-电压(VGS)特性)的曲线图。
具体实施方式
近年来，已经报告了使用In-Ga-Zn-O非晶氧化物作为沟道层的薄膜晶体管(K.Nomura et.al，Nature，Vol.432，pp.488-492，November 2004，the U.K.)。该晶体管可以在室温下形成在塑料或玻璃衬底上。场效应迁移率约为6至9cm2V-1s-1，从而可以获得常关型晶体管。
作为对包含In、Ga、Zn和O的膜及与其相关的生长条件的先进的积极研究和开发的结果，本发明的发明人开发了一种包括微晶的透明氧化物膜，在膜形成时，在氧气气氛条件下，该透明氧化物膜的电子载流子浓度低于1018/cm3。然后，发明人使用该透明半导体氧化物非晶薄膜作为TFT沟道层成功地制造了TFT。该透明半导体氧化物膜是包含In、Ga、Zn和O的透明非晶氧化物膜。该氧化物膜在结晶状态下的组成由InGaO3(ZnO)m表示(m是小于6的自然数)。该氧化物膜中包括微晶。电子载流子浓度低于1018/cm3。发明人还在塑料膜上使用包含In、Ga、Zn和O的膜成功地制造了半导体器件。
包括该薄膜晶体管的半导体器件可以应用于在衬底的面内方向中具有热收缩率或热膨胀系数各向异性的衬底的衬底表面上形成的半导体器件。
本发明不必限于上述薄膜晶体管。这种晶体管可以在室温下形成在塑料膜衬底上，使得可以适当地应用本发明。因此，作为本发明的优选实施例，将描述在塑料膜衬底上形成使用非晶透明氧化物薄膜作为沟道层的TFT的例子。用于本发明的薄膜晶体管的另一例子是其中使用包含ZnO作为主要材料的透明导电氧化物多晶薄膜作为沟道层的TFT。
图1是一种顶部栅极TFT器件的截面图，其中使用在塑料膜衬底上形成的非晶In-Ga-Zn-O薄膜作为沟道层。图2是该TFT器件的顶视图。
使用从膜制造商提供的测量数据或用户获得的测量数据，可以确定膜衬底在其面内方向中的热收缩率或热膨胀系数的各向异性。作为测量方法，已知机械或光学方法。
如图2所示，通过光刻方法在膜衬底1的表面上图案化漏电极和源电极，使得在衬底1的热收缩率或热膨胀系数最大的方向7(图2中由箭头表示)和流过TFT器件的沟道的电流的方向8(图2中由粗箭头表示)之间形成的角度被设置为角度θ(在该图中附图标记9表示角度θ)。此后，通过剥离方法形成漏电极4和源电极3。即，沟道中流动的电流的方向(漏电极和源电极之间流动的电流的方向)被确定以形成沟道。注意，漏电极4的位置和源电极3的位置可能彼此颠倒(在这种情况下，电流流动方向反转)。
作为该制造工艺的结果，当角度θ为0°时，流过TFT器件的导通电流IDS是1.69×10-4 A。注意，TFT器件的导通/截止比超过3×105。
角度θ被适当地设置为大于0°且小于或等于90°的值。角度θ是在衬底的热收缩率或热膨胀系数最大的方向和半导体器件的沟道中流动的电流的方向之间形成的角度。
对于在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底上形成的半导体器件，使衬底的热收缩率或热膨胀系数最大的方向与半导体器件中形成的沟道中流动的电流的方向不平行，从而导通电流增加。
在本发明中，只需要衬底的热收缩率或热膨胀系数最大的方向和半导体器件中形成的沟道中流动的电流的方向之间形成的角度θ使得这两个方向不平行即可(只排除了θ＝0的情况)。该角度优选地大于或等于45°且小于或等于90°。该角度更优选地大于或等于60°且小于或等于90°。该角度最佳为大于或等于80°且小于或等于90°。如上所述，当衬底的热收缩率或热膨胀系数最大的方向和半导体器件中形成的沟道中流动的电流的方向之间形成的角度被设置为使得这两个方向不平行时，TFT器件的迁移率可以提高，且亚阈值斜率特性的S值(下文中简称为“S值”)减小。在稍后描述的例子中，当角度45°与0°相比时以及当角度90°与45°相比时，TFT器件的迁移率可以大为提高，且S值可以进一步减小。当90°的情况与0°的情况相比时，TFT器件的迁移率可以增大约30％，而S值可以减小约60％。因此，可以获得晶体管特性的改善，例如，开关速率的提高。
当半导体器件中形成的沟道中流动的电流的方向与衬底的热收缩率或热膨胀系数最大的方向之间形成的角度接近90°时，TFT器件的迁移率可以进一步提高，且S值可以得到减小。这是因为，当该角度接近90°时，该角度更接近衬底的热收缩率或热膨胀系数最小的角度。因而，优选地，使衬底的热收缩率或热膨胀系数最小的方向与流过半导体器件的电流的方向基本上彼此平行(处于平行或几乎平行的状态)。使这两个方向最优地彼此平行。在此，平行或几乎平行的状态表示衬底的热收缩率或热膨胀系数最小的方向与流过半导体器件的电流的方向之间形成的角度大于或等于0°且小于或等于30°。
当在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底具有多个下述这种方向，其中每个方向都是衬底热收缩率或热膨胀系数最大的方向(例如，热收缩率或热膨胀系数在纵向方向和横向方向中的每个中都最大的情况)时，只需要将流过半导体器件的电流的方向设置为与这多个方向都不平行。
当形成诸如由化合物In-Ga-Zn-O组成的膜之类的透明氧化物半导体膜时，很多情况下在其中产生应力，这导致结晶的发生、取向的改变、裂缝的出现等。具体而言，当在其在面内方向中具有热收缩率或热膨胀系数的各向异性的衬底(如塑料衬底)上形成该膜时，在氧化物半导体膜中产生的应力可以改变氧化物半导体膜的非晶属性或影响膜的压电电阻和疲劳特性。
然而，当衬底的热收缩率或热膨胀系数最大的方向与半导体器件中形成的沟道中流动的电流的方向之间形成的角度被调整到合适的范围中时，TFT器件组的制造产率可以显著地改善。这在大尺寸衬底的情况下尤其重要。
优选地，使用在导电30分钟和150℃的情况下热收缩率大于或等于0.01％且小于或等于9％的衬底作为上述聚合物树脂衬底。
优选地，使用热膨胀系数大于或等于5×10-6且小于或等于1×10-5的衬底作为上述聚合物树脂衬底。
优选地，用厚度为25微米且电介质击穿电压大于或等于6KV的衬底作为上述树脂衬底。
根据优选方式，半导体器件的每个制造工艺中的最大温度设置为大于或等于50℃且小于或等于300℃。当用塑料膜作为衬底时，优选将衬底温度维持在200℃以下。
希望上述热塑性树脂衬底由选自以下材料的至少一种热塑性树脂制成：三醋酸脂、双乙酸脂、玻璃纸、聚醚砜、聚醚醚砜(polyetherether sulfone)、聚砜、聚醚酰亚胺、聚碳酸酯、聚酯、聚乙烯醇、多芳基化合物、聚甲基丙烯酸甲酯、偏二氟乙烯、聚苯乙烯、AS树脂、ABS树脂、聚乙烯、聚丙烯、氯乙烯树脂、甲基丙烯酸脂树脂、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚酰胺、聚甲醛、改性的聚苯醚、聚对苯二甲酸丁二醇酯、聚苯硫醚(polypheylenesulfide)、聚酰胺酰亚胺、聚酰亚胺、聚邻苯二甲酰胺(polyphtalamide)、环聚烯烃聚合物、环烯聚合物(cycloolefin polymer)、聚醚醚酮、液晶聚合物。
可以使用通过将热塑性树脂熔融处理成片形且在纵向和横向方向双轴拉伸该热塑性树脂而获得的膜衬底作为热塑性树脂衬底。
薄膜晶体管(TFT)包括栅极端、源极端和漏极端。TFT是有源器件，其中用在陶瓷、玻璃或塑料等制成的电介质衬底上形成的半导体薄膜作为沟道层，电子或空穴通过该沟道层运动，且该沟道层具有对应于施加到栅极端的电压控制在源极端和漏极端之间的沟道层中流动的电流的功能。
在此可以使用的TFT器件例如是：具有交错(例如，顶部栅极)结构的器件，其中栅极电介质膜和然后的栅极端以此顺序形成在半导体沟道层上；或者是具有反交错(例如，底部栅极)结构的器件，其中栅极电介质膜和然后的半导体沟道层以此顺序形成在栅极端上。
半导体器件的有源层(active layer)可以通过选自溅射方法、沉积方法、CVD方法、外延生长方法、光致沉积(light-induced deposition)方法、脉冲激光沉积方法、离子镀方法的薄膜形成方法形成。就大规模制作而言，溅射方法是最合适的。可以通过溅射方法在等于或低于140℃的温度下制造用包含In、Ga、Zn和O的非晶透明氧化物薄膜作为有源层的TFT。
优选地，用诸如In-Ga-Zn-O、In-Ga-Zn-Sn-O、Ga-Zn-Sn-O、In-Sn-Zn-O、In-Zn-O或In-Sn-Sb-O之类的化合物作为用于非晶透明氧化物薄膜的材料以形成半导体器件的有源层。
对于用于非晶透明氧化物薄膜的材料，可以将选自Sn、Al、Sb、Cd、Ge、P、As、N和Mg的至少一种杂质添加到包含In、Ga、Zn和O的化合物中。
一种优选方式是在包含氧气的气氛中形成非晶透明氧化物薄膜，而不刻意添加用于增加薄膜的电阻的杂质离子。
在用透明半导体非晶In-Ga-Zn-O氧化物薄膜作为TFT的沟道层的情况下，当电子迁移率超过1cm2/(V·秒)，优选地超过5cm2/(V·秒)且电子载流子浓度低于1018/cm3，优选地低于1016/cm3时，在截止状态(即没有施加栅电压时)，在漏极和源极端之间流动的电流低于10微安，优选地低于0.1微安。在使用薄膜的情况下，当电子迁移率超过1cm2/(V·秒)，优选地超过5cm2/(V·秒)时，夹断之后的饱和电流可以超过10微安且电流导通/截止比超过103。
当用透明氧化物膜作为沟道层时，一种优选方式是产生包括栅极电介质膜的晶体管，其中使用SiO2；Al2O3；Y2O3；HfO2、HfSiOx、HfSiON和HfAlOx之一；或包含这些化合物中的至少两种的混合晶体化合物构成所述栅极电介质膜。当在栅极电介质膜和沟道层的薄膜之间的界面处存在缺陷时，电子迁移率减小且在晶体管特性中发生滞后效应。漏电流根据栅极电介质膜的类型而显著变化。因此，必须选择适用于沟道层的栅极电介质膜。当使用Al2O3膜时，可以减小漏电流。当使用Y2O3膜时，可以使滞后效应更小。当使用具有高介电常数的HfO2膜时，可以增大电子迁移率。当使用混合晶体膜时，可以产生漏电流和滞后效应小而电子迁移率大的TFT。栅极电介质膜和沟道层的形成可以在室温下进行，所以可以形成交错结构和反交错结构中的任何一种作为TFT结构。
描述了包含In、Ga和Zn的非晶氧化物的例子。本发明可以适用于包含选自Sn、In和Zn中至少一种元素的非晶氧化物。
当选择Sn作为非晶氧化物的至少一种组成元素时，Sn可以被Sn1-xM4x代替，其中，0＜x＜1，且M4选自Si、Ge和Zr，它们每一个都是原子序数小于Sn的IV族元素。
当选择In作为非晶氧化物的至少一种组成元素时，In可以被In1-yM3y代替，其中，0＜y＜1，且M3选自B、Al、Ga和Y，它们每一个都是原子序数小于Lu或In的III族元素。
当选择Zn作为非晶氧化物的至少一种组成元素时，Zn可以被Zn1-zM2z代替，其中，0＜z＜1，且M2选自Mg和Ca，它们每一个都是原子序数小于Zn的II族元素。
可以适用于本发明的非晶材料的具体例子包括Sn-In-Zn氧化物、In-Zn-Ga-Mg氧化物、In氧化物、In-Sn氧化物、In-Ga氧化物、In-Zn氧化物、Zn-Ga氧化物以及Sn-In-Zn氧化物。组成材料的成分比例不必设置为1∶1。当单独使用Zn或Sn时，难以产生非晶相。然而，当添加In时，容易产生非晶相。例如，在In-Zn系统的情况，除去氧之外的原子的数目比例优选被调整为获得In的浓度大于或等于约20％原子百分比的合成物。在Sn-In系统的情况下，除去氧之外的原子的数目比例优选被调整为获得In的浓度大于或等于约80％原子百分比的合成物。在Sn-In-Zn系统中，除去氧之外的原子的数目比例优选被调整为获得In的浓度大于或等于约15％原子百分比的合成物。
当在以例如约0.5度的入射角度这样的低入射角度对作为测量对象的薄膜进行X射线衍射的情况下未检测到清晰的衍射峰(即，观察到晕圈图案)时，可以确定薄膜是非晶态的。当使用上述材料中任何一种作为场效应晶体管的沟道层时，本发明不排除沟道层包含微晶状态的组成材料。
下文中，将描述本发明的例子。下面的每个例子都是在塑料膜衬底上制造用非晶透明氧化物薄膜作为沟道层的TFT的例子。
(例子1)
示出了使用非晶In-Ga-Zn-O薄膜作为沟道的TFT的制造示例，其中，在双轴拉伸的塑料膜衬底上形成沟道，使得在TFT的沟道中流动的电流的方向不平行于塑料膜衬底的热收缩率最大的方向。塑料膜衬底上制造的TFT是顶部栅极TFT器件，且与上文描述且在图1和2中示出的TFT具有相同的结构。
要使用的塑料膜衬底是片状塑料膜(TORAY Industries，Inc.制造的双轴拉伸聚对苯二甲酸乙二醇酯膜，其产品名为Lumira，产品号为T56，厚度为125微米，尺寸为5厘米见方，纵向(薄膜纵向)热收缩率为1.2，而横向热收缩率为0.5)。
如图2所示，通过光刻方法在膜表面上图案化漏电极和源电极，使得塑料膜衬底的热收缩率最大的方向不平行于流过TFT沟道的电流的方向，以获得90°的角度θ。此后，通过剥离方法形成漏电极和源电极(其材料是Au/Ti，且厚度为45nm)。
此后，使用成分为InGaO3(ZnO)4的多晶烧结材料作为靶通过溅射方法在膜衬底上沉积包括微晶的In-Ga-Zn-O非晶氧化物半导体薄膜。膜形成条件如下：Ar：44sccm，O2：1.6sccm至1.7sccm，处理压力：4.2mTorr，高频功率密度：约3.7W/cm2，衬底温度：不加热，且膜厚度：50nm。
最后，通过溅射方法形成用作栅极电介质膜的Y2O3膜(厚度为140nm，介电常数约为15，且在施加0.5MV/cm的情况下的漏电流密度为10-3A/cm2)。然后，在Y2O3膜上形成Au/Ti膜(厚度为45nm)且通过光刻和剥离方法形成栅极端。因而，在塑料膜衬底上制造了使用非晶In-Ga-Zn-O薄膜作为沟道的顶部栅极TFT。
上述所有工艺都在不刻意加热衬底的状态下进行。因此，使用热变色标签(Nichiyu Giken Kogyo Co，.Ltd.)进行温度测量。然后发现：当通过溅射形成Y2O3膜时，工艺温度达到约135度。确定该温度是TFT制造工艺中的最高温度。最后，在一系列温度循环之后，5厘米见方的膜衬底弯曲。结果，其中心部分与其边缘部分相比降低大约1mm。
图3示出了在室温下测量的该TFT器件(沟道长度为3微米，沟道宽度为30微米，而角度θ为90°)的电流(IDS)-电压(VDS)特性。显然，沟道是n型半导体，因为漏电流IDS随漏电压VDS增加而增加。图4示出了在室温下测量的TFT器件的电流(IDS)-电压(VGS)特性。VDS＝6V时栅电压VGS的阈值为大约0.35V。在VGS＝6V时，流过IDS＝2.66×10-4A的电流。这对应于这一事实：可以通过栅偏压在包括绝缘微晶的In-Ga-Zn-O非晶半导体薄膜中诱生载流子。晶体管的导通/截止比超过5.5×104。亚阈值斜率特性的S值约为0.07V/dec。从输出特性计算场效应迁移率。结果发现在饱和区中场效应迁移率约为20.3cm2(V·sec.)-1。
(例子2)
制造了具有与例子1相同尺寸的TFT器件，而角度θ被设置为45°。图5示出了在室温下测量的该TFT器件(沟道长度为3微米，沟道宽度为30微米，而角度θ为45°)的电流(IDS)-电压(VDS)特性。图6示出了在室温下测量的TFT器件的电流(IDS)-电压(IGS)特性。VDS＝6V时栅电压VGS的阈值大约为0.64V。在VGS＝6V时，流过IDS＝1.83×10-4A的电流。亚阈值斜率特性的S值约为0.14V/dec。从输出特性计算场效应迁移率。结果发现在饱和区中场效应迁移率约为17.1cm2(V·sec)-1。
(对比例)
制造了具有与例子1相同尺寸的TFT器件，而角度θ被设置为0°。图7示出了在室温下测量的TFT器件(沟道长度为3微米，沟道宽度为30微米，而角度θ为0°)的电流(IDS)-电压(VDS)特性。图8示出了在室温下测量的TFT器件的电流(IDS)-电压(IGS)特性。VDS＝6V时栅电压VGS的阈值大约为0.72V。在VGS＝6V时，流过IDS＝1.69×10-4A的电流。亚阈值斜率特性的S值约为0.20V/dec。从输出特性计算场效应迁移率。结果发现在饱和区中场效应迁移率约为15.6cm2(V·sec)-1。
表1示出了通过总结例子1和2以及对比例获得的数据。
表1
  θ(°)   导通电流(×10-4A)  迁移率(cm2(V·sec)-1)   S值(V/dec)   栅电压(V)
  例子1   90   2.66   20.3   0.07   0.35
  例子2   45   1.83   17.1   0.14   0.64
  对比例   0   1.69   15.6   0.20   0.72
根据上述实验性的例子，发现导通电流随角度θ增加而增加。注意，没有观测到截止电流和漏电流IGS的任何显著改变。
如上所述，当衬底的热收缩率或热膨胀系数最大的方向与半导体器件中形成的沟道中流动的电流的方向之间形成的角度被设置为使得这两个方向不平行时，可以增大TFT器件的迁移率，且可以减小亚阈值斜率特性的S值。在此，当角度45°与0°相比，以及当角度90°与45°相比时，TFT器件的迁移率可以进一步增大以减小S值。当90°的情况与0°的情况相比时，TFT器件的迁移率可以增大约30％，且亚压阈值斜率特性的S值可以减小约60％。因此，可以实现诸如开关速度增加之类的晶体管特性的改善。
TFT是常关型的，具有这样的晶体管特性：TFT的截止状态下的栅电流小于0.1微安，且导通/截止比超过104。根据本发明，可以通过溅射沉积方法在塑料膜上制造对可见光透明的TFT。
根据本发明，可以提供具有稳定且一致的电学特性的半导体器件、使用该半导体器件的电路、使用该半导体器件的装置等，所述半导体器件在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底上形成。
例如，本发明可以适用于用在用软塑料膜上形成的透明氧化物膜作为TFT的有源层的TFT，并且还适用于包括柔性显示器的像素驱动器、用于认证的IC卡以及产品ID标签的应用领域。
由于可以在不脱离本发明的精神和范围情况下做出很多明显不同的实施例，所以应当理解，本发明不限于其特定实施例，除非在权利要求中限定。
本申请要求享受2005年9月6日提交的日本专利申请No.2005-258269的优先权，通过引用将其合并于此。

Claims (6)

1.一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底的衬底表面上形成的半导体器件，
其中所述衬底的热收缩率或热膨胀系数最大的方向不平行于流过该半导体器件的电流的方向。
2.一种在衬底的面内方向中具有热收缩率或热膨胀系数的各向异性的衬底的衬底表面上形成的半导体器件，
其中所述衬底的热收缩率或热膨胀系数最小的方向平行于流过该半导体器件的电流的方向。
3.根据权利要求1或2的半导体器件，其中所述半导体器件包括使用包含In、Ga、Zn和O的透明氧化物半导体制成的有源层。
4.根据权利要求1、2或3的半导体器件，其中所述衬底由聚合物树脂构成。
5.根据权利要求1、2或3的半导体器件，其中所述衬底是通过将热塑性树脂熔融处理成片形并且在纵向和横向方向上双轴拉伸所述热塑性树脂而获得的塑料膜。
6.根据权利要求1、2、3、4或5的半导体器件，其中所述半导体器件是薄膜晶体管。
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