CN101048871A - 结合有机发光二极管利用集成氧化锌行和列驱动器的方法和显示器 - Google Patents

结合有机发光二极管利用集成氧化锌行和列驱动器的方法和显示器 Download PDF

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CN101048871A
CN101048871A CNA2005800370296A CN200580037029A CN101048871A CN 101048871 A CN101048871 A CN 101048871A CN A2005800370296 A CNA2005800370296 A CN A2005800370296A CN 200580037029 A CN200580037029 A CN 200580037029A CN 101048871 A CN101048871 A CN 101048871A
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保罗·F·博德
史蒂文·D·泰斯
迈克尔·A·哈斯
埃里克·W·黑默施
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3M Innovative Properties Co
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Abstract

利用具有ZnO沟道的行和列驱动器的方法和显示器，该驱动器控制具有ZnO沟道的像素晶体管，该像素晶体管寻址阵列中的OLED从而使显示屏产生图像。通过利用多孔掩模或者光刻和多孔掩模的组合可以构造一种包括ZnO行和列驱动器和OLED的显示器底板。由此实现了ZnO行和列驱动器以及ZnO像素晶体管的整体集成。

Description

结合有机发光二极管利用集成氧化锌行和列驱动器的方法和显示器
技术领域
本发明涉及包括包含在显示器底板上的电路的显示器。尤其是，本发明涉及显示器的底板，其中在底板的电路中包括行和列驱动器以控制像素晶体管，以及在该电路中包括有机发光二极管作为由像素晶体管激发的像素元件。
背景技术
显示器底板是显示装置例如液晶显示器(LCD)、有机发光二极管(OLED)显示器或者其它显示技术中的重要部件。显示器底板包括提供平台以在其上创建电路使显示屏显示图像的基板。一般，底板包括像素晶体管阵列，其给像素元件(例如OLED单元)阵列提供电信号，以使图像元素或像素产生形成供观看的图像的光。附加电路包括行和列驱动器，并且一般与底板分开设置。行和列驱动器解码输入的视频数据以单独激活像素晶体管，从而单独控制像素。
因为在一般情况下像素晶体管位于底板本身上，像素晶体管形成为薄膜晶体管(TFT)，因此实现极薄的显示屏，例如用于薄屏计算机和电视监视器、电话机和其它小型装置。因为在一般情况下行和列驱动器不位于底板上，它们不必是TFT。然而，行和列驱动器占用分离的空间，例如在安置在显示电路板上的集成电路芯片上。
行和列驱动器与底板阵列之间的互连可能是复杂的。随着行和列数目的增加，互连密度增加。甚至当行和列驱动器是粘接到玻璃的硅芯片时，该互连的复杂程度会成为限制因素。
希望在一些显示屏应用中消除行和列驱动器芯片所需要的空间或使其用于其它目的和/或使行和列驱动器与像素晶体管极接近。因此，希望连同像素晶体管将行和列驱动器直接移到底板上。然而，行和列驱动器必须有非常快的开关性能，由此利用低迁移率半导体沟道的常规TFT结构例如非晶硅是有问题的。
尤其是对于基于OLED的显示器，具有包括尽可能大的电子迁移率的半导体的TFT是有利的。通常，电子迁移率直接影响晶体管的速度和/或者晶体管的大小。例如非晶硅的半导体具有0.5cm2/V-sec级的场效应迁移率。例如多晶硅的材料具有更高的迁移率(大于20cm2/V-sec)，然而需要更高的处理温度和更复杂的制造工序。
发明内容
本发明的实施例通过提供利用在显示器基板上提供利用整体集成的(也就是，同时图案化和通过基本相同的工艺)行和列驱动器与像素晶体管的显示器和方法，同时还采用OLED作为前板元件，来解决这些和其它的问题。行和列驱动器以及像素晶体管都构造为具有氧化锌(ZnO)沟道的TFT，其具有足够高的迁移率来获得恰当译码显示信号和激发OLED像素所必需的开关速度。ZnO行和列驱动器寻址ZnO像素晶体管，该像素晶体管激发阵列中的OLED从而在显示屏上形成图像。可以通过包括多孔掩模例如可重新配置的聚合多孔掩模的工艺来图案化TFT。替代地，可以通过光刻来图案化TFT。
一个实施例是包括底板基板的显示器。在底板基板上图案化一组包括ZnO沟道的薄膜晶体管行和列驱动器。另外，一组包括ZnO沟道的像素薄膜晶体管与在底板基板上的该组行和列驱动器薄膜晶体管整体集成。在底板基板上图案化一组有机发光二极管。通过该组中对应的一个或多个像素薄膜晶体管激发包括叠层的每个有机发光二极管来发光，并通过该组薄膜晶体管行和列驱动器寻址该对应的一个或多个像素薄膜晶体管。
另一个实施例是一种制造显示器的方法。该方法包括在底板基板上图案化一组ZnO沟道薄膜晶体管行和列驱动器。该方法进一步包括在底板基板上图案化一组ZnO沟道像素薄膜晶体管，以使得该像素薄膜晶体管与薄膜行和列驱动器电连接。该方法还包括图案化与像素薄膜晶体管电连接的一组有机发光二极管。每个有机发光二极管包括层的叠层。
另一个实施例是一种制造视频显示器底板的方法。该方法包括利用聚合多孔掩模来限定在底板基板上的ZnO沟道行和列驱动器和ZnO沟道像素薄膜晶体管。该方法进一步包括利用聚合多孔掩模来限定在底板基板上的有机发光二极管。
附图说明
图1示例了可用来在公共基板上构造ZnO行和列驱动器、ZnO像素晶体管和OLED的多孔掩模工艺。
图2示例了具有驱动顶部发射OLED叠层的ZnO TFT像素晶体管的基板的一个实例的截面图，该顶部发射OLED叠层背离基板发射光。
图3示例了具有驱动底部发射OLED叠层的ZnO TFT像素晶体管的基板的另一个实例的截面图，该底部发射OLED叠层穿过基板发射光。
图4是形成显示器单个像素的ZnO像素晶体管和OLED电路的一个单元的示例性实例。
图5是形成显示器像素阵列的ZnO像素晶体管和OLED电路的单元阵列的示例性实例。
图6是形成显示器单个像素的ZnO像素晶体管和OLED电路的一个单元的示例性实例。
图7是用于建立行和列驱动器电路的基于ZnO TFT的数字逻辑门的示例性实例，所述行和列驱动器电路与例如图5所示的基于图4或6任一个的电路的单元阵列相接。
图8是由例如图7中的那些基于ZnO TFT的数字逻辑门形成、用于建立行和列驱动器电路的数字逻辑触发器的示例性实例。
图9是由例如图8中的那些基于ZnO TFT的数字逻辑触发器形成、用于提供行或列驱动器电路的数字逻辑移位寄存器的示例性实例。
具体实施方式
本发明的实施例提供了具有与ZnO像素晶体管集成到同一基板上的ZnO行和列驱动器以及OLED的组合的显示器底板。这些实施例提供了OLED的出色的观看特性与集成的行和列驱动器的紧凑性。此外，一些实施例提供了利用聚合多孔掩模来图案化ZnO行和列驱动器、ZnO像素晶体管和OLED的底板构造。这些实施例中的一些提供了聚合多孔掩模工艺的有效利用，对于底板构造产生了高的产量，同时从制造期间具有减少OLED损坏可能性的OLED的优点中受益。
可以利用本领域中所知的各种技术图案化晶体管。例如，在一些实施例中，在通过利用多孔掩模图案化OLED层之后，可以利用光刻图案化TFT。在其它实施例中，由于可以利用多孔掩模图案化OLED叠层以及用作行和列驱动器的TFT和像素TFT，可以完全地避免湿式化学处理。
如所提到的，在本发明的某些实施例中，可以利用多孔掩模，例如遮蔽掩模，来制备晶体管。在美国专利申请No.2003/0152691和US2003/0150384中提出了利用多孔掩模的示例性工序，作为参考融入于此。为了进一步示例说明多孔掩模工艺，图1是可以使用多孔掩模来图案化OLED叠层以及TFT行和列驱动器和像素TFT的的沉积台简化结构图。尤其是，可以构建沉积台10以进行汽相沉积处理，其中通过多孔掩模使材料蒸发和沉积在沉积基板上。该沉积材料可以是包括半导体材料、电介质材料或用于形成各种元件的导电材料的OLED层或者TFT层所需的任一材料。例如，可以沉积有机或无机材料。在一些情况下，可以沉积有机和无机这两种材料。
形成有多孔掩模图案的多孔掩模20穿过沉积台10，以便邻近显示器底板基板12布置多孔掩模。底板基板12可以包括取决于想要建立的显示电路的多种材料的任一种。例如，底板基板12可以包括柔性材料或者替代地包括刚性材料。也可以使用任何底板基板，例如玻璃基板、硅基板、刚性塑料基板、涂有绝缘层的金属箔等。在任一情况下，底板基板12可以包括或不包括先前形成的特征，例如首先利用光刻将TFT图案化到底板基板12上，随后利用多孔掩模图案化OLED的至少一层。在一些实例中，利用多孔掩模图案化OLED的所有层。
一般沉积台10是真空室。在确保多孔掩模20中的图案邻近于底板基板12之后，通过沉积单元14使材料16蒸发。例如，沉积单元14可以包括受热而使材料蒸发的一舟材料。蒸发的材料16通过多孔掩模20的沉积孔沉积于底板基板12上，以在底板基板12上限定电路层的至少一部分。一旦沉积，材料16就形成由多孔掩模20中的图案限定的沉积图案。多孔掩模20可以包括足够小的孔和空隙，以便于利用如上所述的沉积工艺建立小电路元件。另外，在多孔掩模20中沉积孔的图案可具有如上述提及的大尺寸。其它适当的沉积技术包括e-束蒸发、各种形式的溅射和脉冲激光沉积。下面与图2和3相关参考的实例1，包括通过利用多孔掩模来图案化TFT和OLED的一个示例性方法的细节。
因此，利用如上论述的多孔掩模是沉积构成行和列驱动器的TFT以及显示器底板的像素TFT的一种方式。此外，如上论述的多孔掩模也是用于图案化也呈现在邻近像素TFT的基板上的OLED的一个或多个层的一种方式。邻近用于激发OLED的像素TFT沉积的OLED的截面在图2和3的实例中显示。在一些装置中，利用多孔掩模图案化OLED叠层的所有层。
利用由例如聚酰亚胺的材料构造的聚合多孔掩模是有利的。利用用于图案化OLED叠层的聚合多孔掩模的优点包括：通过多孔掩模对OLED材料潜在地较小损坏，和拉伸多孔掩模以减小由于各种原因例如热膨胀引起掩模中尺寸变化的能力。
作为多孔掩模工序的替代方案，基于ZnO的TFT电路可以通过光刻制造，同时经由上面论述的多孔掩模工序分别沉积OLED。可以利用众所周知的光刻技术，用于限定ZnO像素电路。在Badih E1-Kareh，Fundamentals of Semiconductor Processing Technologies，KluwerAcademic Publishers，第四章，第590-592页，波士顿，(1995)中公开了这种光刻技术的实例。另外，以下关于图2和3参考的实例2，包括应用光刻来首先图案化TFT、随后应用遮蔽掩模来图案化OLED叠层的示例性工艺的细节。因此，图1的多孔掩模工艺是为了说明而提供的，并且不意图限制图案化显示器的TFT的方式。
图2的实例示出了在公共基板42的顶部上沉积像素TFT和OLED。在这个实例中，OLED是顶部发射的(也就是说，背离底板而不是穿过基板发射)。如以上参考图1所述的，基板42可以用各种材料构造，例如玻璃和其它刚性材料，或者通过使用例如金属箔和塑料(例如聚酰亚胺，PEN)的材料可以制成柔性的。将由例如钛和金的材料构造的栅电极44直接图案化到基板42上，然后在栅电极44的顶部图案化栅电介质46，例如SiO2或者Al2O3，以使栅电极44与半导体沟道48完全隔离。半导体沟道48是图案化在栅电介质46顶部上的ZnO层。
在沟道48的一侧上图案化由例如铝的材料构造的漏电极52，同时将分离的源电极50图案化在沟道48的另一侧上，并且可以用与漏电极52相同的材料构造。源电极50延伸到基板42上并且沉积于基板42和OLED叠层56之间。在包括源/漏电极50、52和沟道48的TFT层上方图案化由例如光可成像环氧树脂的材料或例如SiO2的其它材料构造的密封层54，同时在图案化OLED叠层56的源电极50区域的上方留下空隙。应该注意，术语源和漏的使用在某种程度上是任意的，因为应意识到，依赖于选定的电路设计，连接OLED叠层56的电极既可以是源极也可以是漏极。
一般，将源电极和漏电极特征图案化，使得长约1微米到约50微米(优选约5微米到约20微米)的沟道分开它们。对于光刻图案化的TFT，栅长度可以小至1微米，一般是5微米。对于多孔掩模图案化的TFT，栅长度更可能是5到60微米，一般的栅长度为20到30微米。
在通过使用多孔掩模来图案化TFT的实例1中详细地阐述了用于图案化包括图2中的像素TFT的TFT的各层的一个示例性工艺的步骤。同样，在通过光刻来图案化TFT的实例2中详细地阐述了用于图案化包括图2中的像素TFT的TFT的各层的另一个示例性工艺的步骤。在任一情况下，可以在基本相同的时间和通过基本相同的工艺图案化TFT，以便TFT行和列驱动器和像素TFT整体集成到显示基板42上。
OLED叠层56由有机材料叠层构造。对于一个示例性实例，在实例1和2中提出了这些材料和它们在叠层56中的特定顺序。为了完成电流通过OLED叠层56的路径，在OLED叠层56的顶部上方图案化顶电极55。该顶电极55由透明材料例如氧化铟锡(ITO)或者薄金属层构造，以便可以穿过电极55发射光。一接收到电流，OLED叠层56的材料就开始发光。
在图2的结构的操作中，施加电压到漏电极52。然而，由于沟道48处于非导电状态，非常小的电流传递到源电极50，除非也施加电压到栅电极44。一旦施加电压到栅电极44，沟道48变得导电，并且电流通过沟道流到源电极50和流过OLED叠层56，从而引起OLED背离基板42发射光58。因此，以这种方式寻址的OLED阵列导致显示图像。
图3的实例示出了在由例如玻璃或者透明塑料的材料构造的公共透明基板62顶部上沉积的像素TFT和OLED，其中OLED是底部发射的(也就是，发射光穿过基板)。栅电极64直接图案化到基板62上，然后在栅电极64的顶部上图案化栅电介质66，以使栅电极64与半导体沟道68完全隔离。半导体沟道68也是在栅电介质66顶部上图案化的ZnO层。在沟道68一侧上图案化漏电极72，同时在沟道68的另一侧上图案化分离的源电极70。使源电极70与透明的OLED电极77例如ITO电极连接，以便OLED可以穿过电极77和基板62发射光。在包括源/漏电极70、72和沟道68的TFT的各层上方图案化也由例如光可图像化环氧树脂的材料或者例如SiO2的其它材料构造的密封层74，同时在图案化OLED叠层76的透明电极77的区域上方留下空隙。在OLED叠层76的顶部上沉积顶电极75。
在操作中，施加电压到漏电极72。然而，因为沟道68处于非导电状态，很小的电流传递到源电极70，除非也施加电压到栅电极64。一旦施加电压到栅电极64，沟道48变得导电，并且电流通过沟道流到源电极70和流过OLED叠层76，从而引起OLED发射光78穿过电极77和基板62。以这种方式寻址的OLED矩阵导致显示图像。
虽然上面没有具体论述，但将意识到，通过包括封装图2和3中的OLED叠层的密封剂可以保护OLED不暴露于周围元件。图2和3中的密封剂则进一步密封TFT和OLED叠层。
图4是使用两个ZnO像素TFT的单发光单元的电路80的示例性实例。第一电压源82周期性地提供启动脉冲以门控(gate)ZnO像素TFT 86。ZnO像素TFT 86一旦接通，就基于来自第二电压源84的数据脉冲给电容器88和ZNO像素TFT 90的栅极充电。给ZnO像素TFT90的栅极充电会使ZnO像素TFT 90切换到导通状态，从而允许电流从供应电压94流过OLED 92，供应电压94产生用于形成图像的光。提供启动脉冲的第一电压源82表示来自下面关于图7-9论述的行驱动器电路的输出，同时提供数据脉冲的第二电压源84表示来自也在下面关于图7-9论述的列驱动器电路的输出。
图5是一种基于图4所示结构的发光单元阵列的示范性电路图。为了说明，显示了四个单元，并且在该实例中的每一单元都有两个ZnO像素TFT。用来自基于ZnO TFT的行驱动器电路的输出95、98的启动脉冲驱动每个单元的一个ZnO像素TFT，同时还用来自基于ZnO TFT的列驱动器电路的输出97、99的数据脉冲驱动每个单元的每个OLED，以从电压源96提供电能到每个OLED。因此，作为通过行和列驱动器输出激活各个OLED而译码的结果，OLED的阵列产生图像。
图6是一示范性电路图，该图示例了一种替代的发光单元设计，它基于ZnO像素TFT并减小在ZnO TFT参数变化中的变化，这种参数变化否则会损害OLED性能。图4和图6的通用电路，不包括晶体管的ZnO方面，都是本领域中公知的。具体地，由Yi He等人、IEEE ElectronDevice Letters第21(12)卷、590-592(2000)显示和描述了象图6那样的电路设计。
在图6的该电路中，用来自电压源102的信号使ZnO晶体管106和108导通。在这期间电流源104提供数据并促使ZnO晶体管114通过来自电流源104的电流，同时将储能电容器110充电到以所期望的电流电平驱动ZnO晶体管所需的电压电平。在这期间，如果电源118处于低于ZnO晶体管的漏电极的电压，电流将不会流过ZnO晶体管112。此过程适应(accommodate)晶体管阈值电压随时间可能发生的移位。通过ZnO晶体管114的电流然后激活OLED 116以发光。当来自电源102的选择信号关闭时，ZnO晶体管106和108截止，但是只要储能电容器保持充电，则现在源于电压源118的电流继续流过ZnO晶体管114和OLED 16。也可以将图6的单元扩展以产生与图5所示相似的单元阵列。
图7是一示范性电路图，该图说明了基于ZnO TFT的数字逻辑门，可以用它作为行和列驱动器电路的结构单元，所述行和列驱动器电路产生上面关于图4-6论述的启动和数据脉冲。图7的特定逻辑门是“NOTOR”(NOR)门120的实例。然而，应该注意，可以利用由ZnO TFT形成的其它逻辑门设计作为行和列驱动器电路的结构单元，例如OR、AND、“异或”(XOR)逻辑门。在该实例中，第一ZnO TFT 124接收来自电压源122的电力。TFT 124保持在导通状态，并且输出125取自TFT 124的源极。然而，输出125又与ZnO TFT 126和ZnO TFT 130的漏极相连。如果在TFT 126的栅极128或者TFT 130的栅极132中的任一个处提供逻辑高，则输出125被拉到逻辑低。
在本发明的实施例中，通过与基于ZnO的像素TFT和OLED一起在所示的电结构中的底板基板上图案化基于ZnO的TFT 124、126、130来形成这些逻辑门120。通过基于多孔掩模的图案化或者基于光刻的图案化的前述工艺，可以将逻辑门的ZnO TFT与基于ZnO的像素TFT整体集成在显示器的底板基板上。参考下面论述的图8和9，形成行和列驱动器电路的基于ZnO的逻辑门的电连接的图案化将变得明显。
图8示例了一种标准的触发器134，但是该触发器通过一组互连的NOR门120形成，该NOR门120由如图7所示的基于ZnO的TFT组成，基于ZnO的TFT与ZnO像素TFT整体集成在显示器的底板基板上。如同数据输入138，提供时钟输入136。该触发器134提供输出140和反相输出142。应该注意，当构造行和列驱动器电路时，还可以利用除了触发器之外的其它逻辑器件。
图9示例了一种标准的移位寄存器144，但是该移位寄存器由级联的如图8所示的触发器134组成，该级联触发器由包括在底板基板上图案化的基于ZnO的TFT的逻辑门构成。从产生显示数据的装置的视频数据总线串行地提供时钟136和数据信号138。在该实例中，移位寄存器144串行接收像素阵列的列数据位，但必须通过将串行数据转换为并行数据使串行数据信号分离。与顺序地相对，并行数据允许每一像素同时地接收它的一个或者多个控制位。时钟信号136沿着级联触发器传送位，直到从对应于显示器适当列的输出140提供数据位。在所示的简单实例中，第一数据位打算供第四列使用，因此，第一数据位通过第四时钟脉冲到达它的目的列。
在传送过程中，行驱动器电路，其也可以是逻辑器件例如一组移位寄存器，为每一行线保持逻辑低输出，直到数据位位于列移位寄存器144的适当的列输出140。该定时基于自行驱动器电路的最后逻辑高输出信号以来时钟脉冲的数目。这防止门控晶体管(例如图4中的晶体管86)把错误的位传给与OLED直接连接的像素晶体管的栅极。一旦位与各个列适当排列，行驱动器电路就提供逻辑高输出以允许门控每一输出140的ZnO像素TFT变得导通。在这种情况下，使每一列的位传递到直接与OLED连接的ZnO像素TFT的栅极，由此根据该位的值，使OLED发光或者不发光。
虽然图7-9提供了行和列电路的一个实例，但应该注意，可以有行和列电路的很多变形，该行和列电路由在显示器基板上图案化的基于ZnO的TFT构成。从而，提供图7-9仅用于说明这样的行和列电路的一个实例。
实例1和2紧接着阐述在显示器基板上图案化ZnO TFT和OLED的细节。提供实例1和2每个的细节来说明图案化ZnO TFT和OLED的个别实例。应该注意，在多孔掩模制备工艺和替代的混合光刻-多孔掩模制备工艺中可以有很多变化。
实例
实例1：用于显示器的ZnO TFT和OLED遮蔽掩模的制备说明
集成电路由电路元件例如薄膜晶体管(TFT)和电容器组成，它们通过穿过用于图案化膜的柔性掩模真空沉积薄膜而形成。一般的薄膜材料是用于导体或者电极的金属、用于电容器或者防止在交叉金属线之间导电的电介质、和用于晶体管有源层的半导体。薄膜材料的例子是用于导体或者电极的金、钛和铝；用于电介质的Al2O3或者SiO2；和作为半导体的溅射ZnO或者热蒸镀的并五苯。
2”×2”载玻片用酒精冲洗干净。聚合遮蔽掩模如在申请人的U.S.专利申请2003/0152691和2003/0150384公开中先前描述的形成，这些申请作为参考合并于此。在掩模中用激光烧蚀形成孔。
栅电平(gate level)遮蔽掩模图案被置于玻璃基板上的中心。通过遮蔽掩模将100电子束的钛沉积在真空室中的玻璃基板上，之后沉积750的来自电阻加热源的蒸镀金。从真空系统中移除基板和遮蔽掩模。基板通过在其表面上吹氮使其清洁。
如下沉积栅电介质。具有用于栅电介质图案的孔的遮蔽掩模与基板上的栅电平沉积图案对准并套准。在真空室(450W)中通过遮蔽掩模沉积1600 SiO2。将基板和遮蔽掩模从真空系统移除并用吹氮清洗基板。
如下沉积ZnO半导体。具有用于半导体图案的孔的遮蔽掩模与基板上的栅电介质和栅电平沉积图案对准并套准。在真空室中沉积500ZnO(100W，6英寸直径的ZnO靶，在0.4sccm的Ar流中10％的O2)。从真空系统移除基板和遮蔽掩模，并用吹氮清洗基板。
同样通过来自电阻加热源的真空蒸发穿过适当的遮蔽掩模沉积源和漏电极(Al)。在这一点上完成了集成TFT电路。
在集成TFT的顶部上沉积密封剂，以使OLED层从TFT各层和集成电路隔开。通过使密封剂遮蔽掩模与之前的图案化层对准来沉积密封剂。使用电子束蒸发的Al2O3作为密封剂。其通过真空沉积沉积至3000厚。
然后可通过真空蒸发3000掺杂3％的氟化四氰基喹啉并二4苯基异氰酸甲烷(fluorinated tetracyanoquinodimethane)(TCNQ)的4，4’，4”-三(N-(3-甲苯基)-N-苯胺)三苯胺(MTDATA)、之后沉积400 N，N′-二(萘-1-基)-N，N′-二(苯基)联苯胺(NPB)、300掺杂10-(2-苯并噻唑基)-1，1，7，7-四甲基-2，3，6，7-四氢化-1H，5H，11H苯并吡喃(6，7，8-ij)quinolizin-11-一(C545T)的三-(8-羟基喹啉)铝(Alq3)、200 Alq3、7 LiF(以0.5/秒的速率沉积)、50 Al和最后的150 Ag，在密封层的顶部上沉积OLED叠层。
实例2：用于显示器的ZnO TFT光刻/OLED遮蔽掩模制备说明
利用酒精冲洗清洗2”×2”载玻片。在120℃预烘焙载片60秒，以提高光致抗蚀剂(PR)粘附性。通过旋涂将负光致抗蚀剂(FUTURREXNR7-1000PY，可从Futurrex Inc，Franklin，NJ获得)涂覆到载片上(5000RPM旋转60秒，之后在150℃软烘焙60秒)。以180mJ/cm2将光致抗蚀剂暴露到栅电平掩模，然后在100℃进行曝光后烘焙60秒。利用FUTURREX RD6显影剂显影具有曝光的光致抗蚀剂的载片大约10秒。检查显影的载片，然后在水中冲洗，之后在氮中干燥。随后，分别用电子束和电阻加热源真空蒸发50的电子束的钛和600的金。通过在丙酮中剥离该金属，之后是甲醇和水冲洗，完成栅金属层的图案化。
溅射1600 SiO2的栅电介质(450W，8英寸直径SiO2靶)。接下来，溅射500的ZnO(100W，6英寸ZnO靶，在0.4sccm的Ar流中10％的O2)。
如下光刻蚀刻ZnO。通过以5000RPM旋涂将正光致抗蚀剂(FUTURREX PR1-1000A)涂覆到基板上60秒，之后通过在120℃软烘焙120秒。通过光刻掩模以120mJ/cm2曝光该抗蚀剂。通过曝露到FUTURREX RD6显影剂40秒来显影该抗蚀剂。然后检查该样品，用水冲洗并用氮干燥。然后在0.5％HCl中蚀刻基板6秒并移除该光致抗蚀剂。
如下蚀刻SiO2。在120℃预烘焙蚀刻了的ZnO基板60秒。以5000RPM旋涂60秒将正光致抗蚀剂涂覆到预烘焙的基板(FUTURREXPR1-1000A)上，之后在120℃软烘焙120秒。通过光刻掩模以120mJ/cm2曝光抗蚀剂，利用FUTURREX RD6显影剂显影，检查，用水冲洗以及然后用氮干燥。然后在120℃硬烘焙基板60秒。用PAD ETCH4(可从Ashland Specialty Chemicals，Dublin，OH获得)蚀刻该样品90秒，之后移除光致抗蚀剂。
如下通过光刻来图案化源和漏电极。在120℃预烘焙蚀刻了的氧化物基板60秒。通过以5000RPM旋涂60秒涂覆一层负光致抗蚀剂(FUTURREX NR7-1000PY)，之后在150℃软烘焙60秒。通过源/漏多孔掩模以180mJ/cm2曝光该光致抗蚀剂，在100℃进行后烘焙60秒，利用FUTURREX RD6显影10秒，检查，水冲洗并在氮中干燥。最后，在基板顶部上依序沉积Ti/Au/Ag。通过在丙酮中剥离沉积的金属，之后在甲醇和水中冲洗，并氮吹干，完成源/漏金属层的图案化。
如下涂覆密封剂。通过0.45μm的过滤器过滤负环氧型光致抗蚀剂(SU-8-2000.5，可从MicroChem，Newton，MA获得，)，然后通过以5000RPM旋涂60秒将它涂覆到集成TFT基板上，之后在100℃软烘焙2分钟。用54mJ/cm2的照度通过光掩模曝光该样品，之后在100℃进行后烘焙2分钟。在SU-8 DEVELOPER(MicroChem)中显影该样品10秒，之后用异丙醇冲洗。在150℃硬烘焙该样品2分钟。在这一点完成了集成TFT电路，并准备好用于OLED部件。
通过真空蒸发3000掺杂3％的氟化四氰基喹啉并二4苯基异氰酸甲烷(fluorinated tetracyanoquinodimethane)(TCNQ)的4，4’，4”-三(N-(3-甲苯基)-N-苯胺)三苯胺(MTDATA)、之后沉积400 N，N′-二(萘-1-基)-N，N′-二(苯基)联苯胺(NPB)、300掺杂10-(2-苯并噻唑基)-1，1，7，7-四甲基-2，3，6，7-四氢化-1H，5H，11H苯并吡喃(6，7，8-ij)quinolizin-11-一(C545T)的三-(8-羟基喹啉)铝(Alq3)、200 Alq3、7 LiF(以0.5/秒的速率沉积)、50 Al和最后的150Ag，在密封层的顶部上沉积OLED叠层。
虽然已参考本发明的不同实施例特别示出和描述了本发明，但本领域技术人员应该明白，在不脱离本发明的精神和范围的前提下，可进行形式和细节上的各种其它改变。

Claims (14)

1.一种显示器，包括：
底板基板；
一组薄膜晶体管行和列驱动器，其在所述底板基板上图案化并包括ZnO沟道；
一组像素薄膜晶体管，其与所述底板基板上的所述一组薄膜晶体管行和列驱动器整体集成，并包括ZnO沟道；和
一组有机发光二极管，其包括在所述底板基板上图案化的层的叠层，其中通过所述组中对应的一个或多个像素薄膜晶体管激发每个有机发光二极管发光，并且通过该组薄膜晶体管行和列驱动器寻址该对应的一个或多个像素薄膜晶体管。
2.如权利要求1所述的显示器，其中所述有机发光二极管背离所述底板基板发射光。
3.如权利要求1所述的显示器，其中所述有机发光二极管穿过所述底板基板发射光。
4.如权利要求1所述的显示器，其中该组像素薄膜晶体管构成了每单元包括四个薄膜晶体管和一个有机发光二极管的单独单元。
5.如权利要求1所述的显示器，其中所述薄膜晶体管行和列驱动器具有超过4cm2/V-sec的电子迁移率。
6.一种制造显示器的方法，包括：
在底板基板上图案化一组ZnO沟道薄膜晶体管行和列驱动器；
在底板基板上图案化一组ZnO沟道像素薄膜晶体管，该像素薄膜晶体管与薄膜晶体管行和列驱动器电连接；和
在底板基板上图案化一组与所述像素薄膜晶体管电连接的有机发光二极管，其中每个有机发光二极管包括层的叠层。
7.如权利要求6所述的方法，其中通过光刻完成在底板基板上图案化该组ZnO沟道薄膜晶体管行和列驱动器以及图案化该组ZnO沟道像素薄膜晶体管。
8.如权利要求6所述的方法，其中通过聚合多孔掩模完成在底板基板上图案化该组ZnO沟道薄膜晶体管行和列驱动器以及图案化该组ZnO沟道像素薄膜晶体管。
9.如权利要求6所述的方法，其中通过借助聚合多孔掩模形成该有机发光二极管中层的叠层的至少一层，来完成在底板基板上图案化该组有机发光二极管。
10.一种构造视频显示器底板的方法，包括：
利用聚合多孔掩模在底板基板上限定ZnO沟道行和列驱动器以及ZnO沟道像素薄膜晶体管；和
利用聚合多孔掩模在所述底板基板上限定有机发光二极管。
11.如权利要求10所述的方法，其中利用聚合多孔掩模限定ZnO沟道行和列驱动器以及ZnO沟道像素薄膜晶体管包括：图案化该行和列驱动器以及该像素薄膜晶体管之间的电连接。
12.如权利要求10所述的方法，其中利用聚合多孔掩模在底板基板上图案化有机发光二极管包括：图案化该像素薄膜晶体管和该有机发光二极管之间的电连接。
13.如权利要求10所述的方法，其中利用聚合多孔掩模在底板基板上限定有机发光二极管包括：在该像素薄膜晶体管的电极层的顶上图案化形成该有机发光二极管的层。
14.如权利要求10所述的方法，进一步包括图案化在行和列驱动器以及像素薄膜晶体管上方的密封层。
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