WO2022193316A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022193316A1
WO2022193316A1 PCT/CN2021/081888 CN2021081888W WO2022193316A1 WO 2022193316 A1 WO2022193316 A1 WO 2022193316A1 CN 2021081888 W CN2021081888 W CN 2021081888W WO 2022193316 A1 WO2022193316 A1 WO 2022193316A1
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WIPO (PCT)
Prior art keywords
layer
spacer column
spacer
light
pixel
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PCT/CN2021/081888
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English (en)
French (fr)
Inventor
韩城
李鑫
吴启晓
吴淞全
孙猛
樊星
李彦松
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/633,589 priority Critical patent/US20230363209A1/en
Priority to CN202180000537.6A priority patent/CN115380386A/zh
Priority to PCT/CN2021/081888 priority patent/WO2022193316A1/zh
Publication of WO2022193316A1 publication Critical patent/WO2022193316A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/331—Nanoparticles used in non-emissive layers, e.g. in packaging layer

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • a display substrate includes a pixel definition layer and a spacer column disposed on a driving structure layer, the spacer column is disposed on a surface of the pixel definition layer on a side away from the driving structure layer, and the spacer column is The orthographic projection on the substrate is within the range of the orthographic projection of the pixel definition layer on the substrate; the surface of the spacer column on the side away from the driving structure layer has protrusions, and the height of the protrusions is less than 0.2 ⁇ m.
  • the material of the spacer column includes a polymer elastomer and nanoparticles, and the proportion of nanoparticles in the spacer column is 0.5 wt % to 5 wt %.
  • the nanoparticles are 20 nm to 100 nm in diameter.
  • the nanoparticles comprise methyl-modified inorganic nanoparticles.
  • the methyl-modified inorganic nanoparticles include at least one of methyl-modified inorganic silica nanoparticles, methyl-modified inorganic zinc oxide nanoparticles, and methyl-modified inorganic zirconia nanoparticles.
  • the polymeric elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology of the polymeric elastomer is a cross-linked network formed by chemical linkages , the mesh diameter of the cross-linked network is 0.5 ⁇ m to 2.0 ⁇ m.
  • the spacer column has a height of 1 ⁇ m to 1.5 ⁇ m.
  • the light emitting structure layer further includes a pixel definition layer, the spacer column is disposed on a side of the pixel definition layer away from the substrate, and the pixel definition layer and the spacer column are made of the same material.
  • the spacer column and the pixel defining layer are of an integral structure.
  • a display device includes the aforementioned display substrate.
  • a preparation method of a display substrate comprising:
  • a pixel definition layer and spacer pillars are formed on the driving structure layer, the spacer pillars are disposed on the surface of the pixel definition layer on the side away from the driving structure layer, and the orthographic projection of the spacer pillars on the substrate is located at within the range of the orthographic projection of the pixel definition layer on the substrate;
  • the organic light-emitting layer is evaporated by using a fine metal mask
  • the surface of the spacer column on the side away from the driving structure layer has protrusions, and the height of the protrusions is less than 0.2 ⁇ m.
  • the material of the spacer column includes a polymer elastomer and nanoparticles, and the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology It is a cross-linked network formed by chemical connection, and the mesh diameter of the cross-linked network is 0.5 ⁇ m to 2.0 ⁇ m; repairing the spacer column includes:
  • the spacer column is irradiated with ultraviolet light, and the polymer elastomer undergoes expansion and contraction of the cross-linked network under ultraviolet light irradiation, so that the protrusion on the surface of the spacer column changes from sharp to gentle, and the The height of the protrusions is less than 0.2 ⁇ m.
  • the irradiation intensity of the ultraviolet light is 5 mW/cm 2 to 20 mW/cm 2
  • the irradiation time of the ultraviolet light is 100 seconds to 300 seconds.
  • Forming a pixel definition layer and a spacer column on the driving structure layer includes: forming a pixel definition layer on the driving structure layer; using a spacer column mask to form a spacer column on the pixel definition layer;
  • Irradiating the spacer column with ultraviolet light includes: arranging the spacer column mask on the display substrate, irradiating with ultraviolet light equipment, and the ultraviolet light passing through the light transmission of the spacer column mask area is irradiated onto the septum column.
  • Forming the pixel definition layer and the spacer column on the driving structure layer includes: using a gray-tone mask to form the pixel definition layer and the spacer column on the driving structure layer through the same patterning process;
  • Irradiating the spacer column with ultraviolet light includes: arranging the gray-tone mask on the display substrate, irradiating with ultraviolet light equipment, and irradiating the ultraviolet light through the light-transmitting area of the gray-tone mask onto the septum column.
  • FIG. 1 is a schematic structural diagram of an OLED display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 4 is a working timing diagram of a pixel driving circuit
  • FIG. 5 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of an exemplary embodiment of the present disclosure after a driving structure layer pattern is formed
  • FIG. 7 is a schematic diagram of an exemplary embodiment of the present disclosure after an anode pattern is formed
  • FIG. 8 is a schematic diagram of forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an exemplary embodiment of the present disclosure after a spacer column pattern is formed
  • FIG. 10 is a schematic diagram of forming an organic light-emitting layer pattern according to an exemplary embodiment of the present disclosure.
  • Fig. 11 is the schematic diagram of the sharp protrusion produced on the surface of the spacer column
  • FIG. 12 is a schematic diagram after repairing the surface damage of the spacer column according to an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a cathode pattern
  • FIG. 14 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a pattern of a package structure layer
  • FIG. 15 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • 22 pixel definition layer
  • 23 organic light-emitting layer
  • 24 cathode
  • 102 storage capacitor
  • 103 drive structure layer
  • 104 light-emitting structure layer
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain region or drain electrode) and the source electrode (or source electrode terminal, source region or source electrode), and current can flow through the drain electrode, channel region and source electrode.
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, herein, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • the “element having a certain electrical effect” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors, or capacitors.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of an OLED display device.
  • the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may supply a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, etc., suitable for the specification of the scan signal driver When supplied to the scan signal driver, a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting signal driver can be supplied to the light-emitting signal driver.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values with a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be constructed in the form of a shift register, and may generate scans in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal signal, m can be a natural number.
  • the emission signal driver may generate emission signals to be supplied to the emission signal lines E1 , E2 , E3 , . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the emission signal driver may sequentially supply emission signals with off-level pulses to the emission signal lines E1 to Eo.
  • the light-emitting signal driver may be constructed in the form of a shift register, and may generate the light-emitting signal in such a manner that the light-emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a display area and a bezel area surrounding the display area.
  • the display area of the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color and emits light of a second color.
  • the second sub-pixel P2 for light and the third sub-pixel P3 for emitting light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels and white sub-pixels, which are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagon or hexagonal.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 3 , the pixel driving circuit may include seven transistors (the first transistor T1 to the seventh transistor T7 ), one storage capacitor C1 and seven signal lines (the data signal line D, the first scan signal line Two scan signal lines S2, light-emitting signal lines E, initial signal lines INIT, first power lines VDD and second power lines VSS).
  • the first end of the storage capacitor C1 is connected to the first power supply line VDD
  • the second end of the storage capacitor C1 is connected to the second node N2, that is, the second end of the storage capacitor C1 is connected to the third transistor T3 Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initialization voltage to the gate of the third transistor T3 to initialize the charge amount of the gate of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C1, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and enables the data voltage of the data signal line D to be input to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an on-level light emission signal is applied to the light emission signal line E, the fifth and sixth transistors T5 and T6 make the light emitting device emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize or discharge the amount of charge accumulated in the first electrode of the light emitting device to emit light The amount of charge accumulated in the first pole of the device.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend in the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and the data signal line D extends in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 4 is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in FIG. 3 includes seven transistors (the first transistor T1 to the sixth transistor T7 ) and one storage capacitor C1 and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), all seven transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are a high-level signal.
  • the signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are a high-level signal
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the second through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1, and the voltage at the second end (second node N2) of the storage capacitor C1 is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the internal pre-stored voltage, completes the initialization, and ensures that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 5 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a sub-pixel in the OLED display substrate.
  • the display substrate may include a driving circuit layer 103 disposed on the substrate 10 , a light emitting structure layer 104 disposed on the side of the driving circuit layer 103 away from the substrate 10 , and a light emitting structure layer 104 disposed on the light emitting The structure layer 104 is away from the package structure layer 105 on the side of the substrate 10 .
  • the driving circuit layer 103 may include a transistor 101 and a storage capacitor 102 .
  • the light emitting structure layer 104 is a light emitting device that emits light from an organic material
  • the light emitting structure layer 104 may include an anode 21 , a pixel definition layer 22 , an organic light emitting layer 23 , a cathode 24 and a spacer column 25
  • the pixel definition layer 22 is provided with a pixel opening exposing the anode 21
  • the organic light-emitting layer 23 is provided between the anode 21 and the cathode 24
  • the spacer column 25 is provided on the surface of the pixel definition layer 22 on the side away from the substrate 10
  • the spacer column 25 is located on the side of the pixel definition layer 22 away from the substrate 10.
  • the orthographic projection on the substrate is within the range of the orthographic projection of the pixel definition layer 22 on the substrate.
  • the photo spacer (Photo Spacer, PS for short) 25 is configured to support a fine metal mask or an open mask used for vapor deposition of organic light-emitting materials.
  • the encapsulation structure layer 105 may include a first encapsulation layer disposed on the side of the light emitting structure layer 104 away from the substrate, a second encapsulation layer disposed on the side of the first encapsulation layer away from the substrate, and a first encapsulation layer disposed on the side of the second encapsulation layer away from the substrate.
  • the second encapsulation layer of organic material is arranged between the first encapsulation layer of inorganic material and the third encapsulation layer, forming a stacked structure of inorganic material/organic material/inorganic material.
  • the material of the spacer column 25 may include polymeric elastomers and nanoparticles.
  • the material of the polymer elastomer can include polyurethane, polysiloxane or liquid crystal block polymer, etc.
  • the nanoparticles can be inorganic nanoparticles, the inorganic nanoparticles can be methyl modified inorganic nanoparticles, methyl
  • the modified inorganic nanoparticles may include methyl-modified inorganic silica nanoparticles, methyl-modified inorganic zinc oxide nanoparticles, methyl-modified inorganic zirconia nanoparticles, and the like.
  • the methyl group-modified inorganic nanoparticles can introduce methyl groups to the surface of the inorganic nanoparticles by means of surfactant treatment.
  • the morphology of the polymer elastomer is a cross-linked network
  • the inorganic nanoparticles are dispersed in the mesh of the cross-linked network composed of the polymer elastomer to support the cross-linked network
  • the cross-linked network It is formed by chemical linking of polymer elastomers.
  • the particle size of the inorganic nanoparticles may be about 20 nm to 100 nm.
  • the proportion of inorganic nanoparticles in the spacer column may be about 0.5 wt % to 5 wt %.
  • the thickness of the spacer pillars 25 may be about 1.0 ⁇ m to 1.5 ⁇ m.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • the manufacturing process of the display substrate includes the following operations.
  • a substrate is formed on a glass carrier.
  • forming the substrate on the glass carrier may include: coating a first flexible material film on the glass carrier 1, and forming a first flexible layer after curing to form a film; when the first flexible layer is away from the glass A second flexible material film is coated on the surface of one side of the carrier board, and a second flexible layer is formed after curing into a film; a third flexible material film is coated on the surface of the second flexible layer away from the glass carrier side, and cured to form a film Then, a third flexible layer is formed, and a flexible substrate is formed on the glass carrier.
  • the substrate includes a stacked first flexible layer, a second flexible layer and a third flexible layer.
  • the first flexible layer, the second flexible layer, and the third flexible layer may be of the same material, or may be of different materials.
  • the material of the first flexible layer, the second flexible layer and the third flexible layer may include polyimide (PI).
  • forming the substrate on the glass carrier 1 may include: firstly coating a first flexible material film on the glass carrier, and then curing it into a film to form a first flexible layer; A first inorganic material film is deposited on the layer to form a first inorganic layer covering the first flexible layer; then a second flexible material film is coated on the first inorganic layer, and a second flexible layer is formed after curing into a film; A second inorganic material film is deposited on the flexible layer to form a second inorganic layer covering the second flexible layer, and a flexible substrate is formed on the glass carrier plate, the substrate includes a stacked first flexible layer, a first inorganic layer, and a second flexible layer and the second inorganic layer.
  • the material of the first flexible material film and the second flexible material film may be polyimide (PI), polyethylene terephthalate (PET), pressure sensitive adhesive (PSA) or a
  • PI polyimide
  • PET polyethylene terephthalate
  • PSA pressure sensitive adhesive
  • the surface-treated polymer soft film and other materials, the first and second inorganic material films can be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, the first inorganic layer and the second inorganic layer may be referred to as a first barrier layer and a second barrier layer.
  • forming the substrate on the glass carrier plate 1 may include: firstly coating a first flexible material film on the glass carrier plate, forming a first flexible layer after curing into a film; depositing a first inorganic material film on the layer to form a first inorganic layer covering the first flexible layer; then depositing an amorphous silicon film on the first inorganic layer to form an amorphous silicon layer covering the first inorganic layer; A second flexible material film is coated on the silicon layer, and a second flexible layer is formed after curing into a film; then a second inorganic material film is deposited on the second flexible layer to form a second inorganic layer covering the second flexible layer, and a second flexible layer is formed on the glass carrier.
  • the plate forms a flexible substrate including a stacked first flexible layer, a first inorganic layer, a semiconductor layer, a second flexible layer and a second inorganic layer.
  • the material of the semiconductor layer may be amorphous silicon (a-si).
  • the substrate may be a rigid substrate.
  • the driving structure layer may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Three sub-pixels are illustrated in FIG. 6 , and the driving structure layer of each sub-pixel is composed of a transistor 101 and a storage capacitor 102 example to illustrate.
  • the preparation process of the driving structure layer may include:
  • a first insulating film and a semiconductor layer film are sequentially deposited on the substrate 10 , and the semiconductor layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10 and a semiconductor layer disposed on the first insulating layer 11
  • the pattern of the semiconductor layer includes at least an active layer disposed in each sub-pixel.
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 12 covering the pattern of the semiconductor layer, and a first insulating layer 12 disposed on the second insulating layer 12
  • a metal layer pattern, the first metal layer pattern at least includes a gate electrode and a first capacitor electrode arranged in each sub-pixel.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 13 covering the first metal layer, and a third insulating layer 13 disposed on the third insulating layer 13
  • Two metal layer patterns, the second metal layer pattern at least includes a second capacitor electrode disposed in each sub-pixel, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a pattern of a fourth insulating layer 14 covering the second metal layer.
  • the fourth insulating layer 14 is provided with a plurality of via patterns, a plurality of The via hole pattern includes at least two first via holes arranged in each sub-pixel, the positions of the two first via holes correspond to the two ends of the active layer respectively, and the fourth insulating layer in the two first via holes 14.
  • the third insulating layer 13 and the second insulating layer 12 are etched away to expose the surface of the active layer.
  • the third metal layer pattern at least includes a source electrode disposed in each sub-pixel
  • the source electrode and the drain electrode are respectively connected with the active layer of the sub-pixel through the first via hole, so that a conductive channel is formed between the source electrode and the drain electrode.
  • a flat film is coated to form a flat (PLN) layer 15 covering the entire substrate 10, and a via pattern is formed on the flat layer 15 through a patterning process, and the via pattern at least includes a second sub-pixel disposed in each sub-pixel.
  • the flat layer 15 in the second via hole is removed, exposing the surface of the drain electrode.
  • the surface of the flat layer 15 on the side away from the substrate 10 is a flat surface, and the flattening layer can be made of resin or other materials.
  • the formed structure includes: the substrate 10 disposed on the glass carrier 1 , and the driving structure layer 103 disposed on the substrate 10 , as shown in FIG. 6 .
  • the active layer, gate electrode, source electrode and drain electrode in each sub-pixel form a transistor 101
  • the first capacitor electrode and the second capacitor electrode form a storage capacitor 102 .
  • the transistor may be a driving transistor in a pixel driving circuit
  • the driving transistor may be a thin film transistor.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the flat layer type adopts organic material, such as resin, etc.
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene or polythiophene hexathiophene
  • forming the anode pattern may include: depositing a conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the conductive thin film through a patterning process, and forming a conductive layer pattern, the conductive layer pattern at least including being disposed in each sub-pixel
  • the anode 21 is connected to the drain electrode of the first transistor 101 through the second via hole, as shown in FIG. 7 .
  • the conductive film may use a single layer of transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or the conductive film may use a composite layer of metal material and transparent conductive material, such as Ag /ITO, Ag/IZO or ITO/Ag/ITO, etc.
  • the thickness of the metal material in the composite layer can be about 80nm to 100nm
  • the thickness of the transparent conductive material in the composite layer can be about 5nm to 20nm, so that the average thickness of the anode in the visible light region
  • the reflectivity is about 85% to 95%.
  • a pixel definition layer pattern is formed.
  • forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, masking and developing the pixel definition film through a patterning process to form a pixel definition (PDL) layer 22.
  • PDL pixel definition
  • a pixel opening is formed on the pixel definition layer 22, and the pixel definition film in the pixel opening is developed to expose the surface of the anode 21, as shown in FIG. 8 .
  • the thickness of the pixel definition layer may be about 1 ⁇ m to 1.5 ⁇ m.
  • the shape of the pixel opening may be a square, a rectangle, a circle, an ellipse, or a hexagon, etc., which may be set according to actual needs, which is not limited in the present disclosure.
  • the pixel definition film may be a material such as polyimide, acrylic, or polyethylene terephthalate.
  • a spacer column pattern is formed.
  • forming the spacer column pattern may include: coating a spacer film on the substrate on which the aforementioned pattern is formed, and patterning the spacer film through a patterning process to form a spacer column 25 pattern, the spacer The pillars 25 are disposed on the surface of the pixel definition layer 22 away from the substrate, and the orthographic projection of the spacer pillars 25 on the substrate is within the range of the orthographic projection of the pixel definition layer 22 on the substrate, as shown in FIG. 9 .
  • At least one pixel unit including R sub-pixels, G sub-pixels and B sub-pixels may be provided with at least one spacer column.
  • a plurality of spacer pillars can be evenly distributed, and in the frame area, a plurality of spacer pillars can be arranged in the area within the boundary of the encapsulation layer, and no spacer pillars are arranged in the area outside the boundary of the encapsulation layer.
  • the material of the spacer column may include polymeric elastomers and inorganic nanoparticles.
  • the material of the polymer elastomer can include polyurethane, polysiloxane or liquid crystal block polymer, etc.
  • the inorganic nanoparticles can be methyl-modified inorganic nanoparticles, and the methyl-modified inorganic nanoparticles can include methyl-modified inorganic silica nanoparticles , methyl-modified inorganic zinc oxide nanoparticles or methyl-modified inorganic zirconia nanoparticles, etc.
  • the morphology of the polymer elastomer is a cross-linked network formed by chemical connection, and the inorganic nanoparticles are dispersed in the mesh of the cross-linked network composed of the polymer elastomer to support the cross-linked network.
  • the molecular weight of the polymeric elastomer may be in the order of millions to tens of millions
  • the refractive index of the polymeric elastomer may be in the range of 1.5 to 1.7
  • the mesh diameter of the cross-linked network may be in the range of 0.5 ⁇ m to 1.7 ⁇ m. 2.0 ⁇ m.
  • the methyl group-modified inorganic nanoparticles can introduce methyl groups to the surface of the inorganic nanoparticles by means of surfactant treatment.
  • the diameter of the inorganic nanoparticles may be about 20 nm to 100 nm.
  • the specific gravity of the inorganic nanoparticles may be about 0.5 wt % to 5 wt % of the spacer column, and the inorganic nanoparticles may be uniformly distributed in the polymer elastomer.
  • the shape of the spacer column can be square, rectangular, circular, elliptical, hexagonal, or the like.
  • the width of the spacer column may be about 5 ⁇ m to 10 ⁇ m.
  • the height of the spacer column may be about 1 ⁇ m to 1.5 ⁇ m.
  • the cross-sectional shape of the spacer column may be a trapezoid, and the base angle of the trapezoid may be about 40° to 60°.
  • the spacer film coating and patterning process may be performed as follows. First, the polymer elastomer, inorganic nanoparticles and photosensitive agent are mixed to form a sol, and then the sol is uniformly coated on the substrate formed with the aforementioned pattern to form a spacer film, and then a spacer column mask is used to perform the spacer film. After exposure and development, the spacer pillar pattern is formed through a localized UV curing process.
  • the spacer post mask includes a light-transmitting area and an opaque area
  • the photosensitive agent is a negative photosensitive agent.
  • the spacer film corresponding to the position of the light-transmitting area of the spacer column mask forms a fully exposed area
  • the spacer film corresponding to the position of the opaque area of the spacer column mask forms an unexposed area. area.
  • the spacer film in the fully exposed area is retained to form a spacer column pattern, and the spacer film in the unexposed area is completely removed.
  • Forming a pattern of the organic light-emitting layer may include: disposing an evaporation mask on the substrate on which the aforementioned pattern is formed, forming the pattern of the organic light emitting layer 13 through an evaporation process, the organic light emitting layer 23 and the anode in the pixel opening 21 connections, as shown in Figure 10.
  • the organic light-emitting layer may include an emitting layer (Emitting Layer, referred to as EML), and any one or more of the following: a hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer (HTL), Electron Block Layer (EBL), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer, referred to as EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • HBL Hole Block Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the light emitting layers of different sub-pixels are different. For example, a red sub-pixel includes a red light-emitting layer, a green sub-pixel includes a green light-emitting layer, and a blue sub-pixel includes a blue light-emitting layer.
  • the organic light-emitting layer may be formed by using a fine metal mask (FMM, Fine Metal Mask) and an open mask (Open Mask) evaporation process, or by using an inkjet printing process.
  • FMM fine metal mask
  • Open Mask open mask
  • the organic light-emitting layers of a plurality of sub-pixels illustrated in the drawings are mutually isolated structures, in the exemplary embodiment, in order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer A common layer may be used for the layers, and a common layer may be used for the electron injection layer and the electron transport layer on the other side of the light-emitting layer.
  • any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), However, isolation is achieved by the surface step difference of the formed film layer or by means of surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer and electron transport layer corresponding to adjacent sub-pixels may be isolated.
  • the organic light-emitting layer may be prepared by the following preparation method. After the isolation column is prepared, the hole injection layer and the hole transport layer are sequentially evaporated using an open mask, and the common layer of the hole injection layer and the hole transport layer is formed on the display substrate, that is, the hole injection layer and the hole transport layer are formed on the display substrate. The hole injection layer is connected, and the hole transport layers of all sub-pixels are connected. The area of each of the hole injection layer and the hole transport layer is approximately the same, and the thickness thereof is different.
  • the electron blocking layer and the red light-emitting layer, the electron blocking layer and the green light-emitting layer, and the electron blocking layer and the blue light-emitting layer were respectively evaporated on different sub-pixels using a fine metal mask.
  • the light-emitting layers may have a small amount of overlap (eg, the overlapping portion occupies less than 10% of the area of the respective light-emitting layer patterns), or may be isolated.
  • the hole blocking layer, the electron transport layer and the electron injection layer are sequentially evaporated using an open mask to form a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate, that is, the common layer of all sub-pixels is formed.
  • the hole blocking layers are connected, the electron transport layers of all sub-pixels are connected, and the electron injection layers of all sub-pixels are connected.
  • the orthographic projection of one or more of the hole injection layer, hole transport layer, hole blocking layer, electron transport layer, electron injection layer, and cathode on the substrate is continuous.
  • at least one of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the cathode of at least one row or column of subpixels is connected.
  • at least one of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the cathode of the plurality of subpixels is connected.
  • the orthographic projection of the light emitting layer on the substrate is located within the range of the orthographic projection of the hole blocking layer on the substrate In this case, the area of the hole blocking layer is larger than that of the light emitting layer. Since the hole blocking layer is a common layer, the orthographic projection of the hole blocking layer on the substrate at least includes the orthographic projection of the light-emitting regions of the two sub-pixels on the substrate. In an exemplary embodiment, the orthographic projection of the light-emitting layer of at least part of the sub-pixels on the substrate overlaps with the orthographic projection of the pixel driving circuit driving on the substrate.
  • the electron blocking layer can act as a microcavity adjusting layer between the hole transport layer and the light emitting layer, so that the thickness of the organic light emitting layer between the cathode and the anode can be adjusted to meet the optical path requirement of the optical microresonator. Designed for optimal light intensity and color.
  • the light emitting layer may include a host material and a dopant material doped in the host material, and the doping ratio of the guest material in the light emitting layer is 1% to 20%.
  • the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light; ”, which effectively improves the fluorescence quenching caused by the collision between the molecules of the light-emitting layer and the guest materials and the collision between the energies, and improves the luminous efficiency and device life.
  • the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage.
  • the host material and the guest material can be co-evaporated through a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the evaporation rate of the guest material can be controlled during the evaporation process. to control the doping ratio, or to control the doping ratio by controlling the evaporation rate ratio of the host material and the guest material.
  • the hole injection layer may employ inorganic oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide , tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or p-type dopants and hole transport material dopants of strong electron withdrawing systems may be employed.
  • the thickness of the hole injection layer may be about 5 nm to 20 nm.
  • the hole transport layer may adopt a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan Wait.
  • the thickness of the hole transport layer may be about 60 nm to 150 nm.
  • the electron blocking layer may use an aromatic amine compound with hole transport properties, and its substituent may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan, or the like.
  • the thickness of the electron blocking layer may be about 5 nm to 20 nm.
  • the light-emitting layer may include a light-emitting host material and a light-emitting guest material.
  • the light-emitting host material may adopt a bipolar single host, or may adopt a double host formed by blending a hole-type host and an electron-type host.
  • As the light-emitting guest material a phosphorescent material, a fluorescent material, a delayed fluorescent material, or the like can be used.
  • the thickness of the light emitting layer may be about 10 nm to 25 nm.
  • the hole blocking layer and the electron transport layer may employ an aromatic heterocyclic compound such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazophenanthridine derivatives and other imidazole derivatives; pyrimidines Derivatives, triazine derivatives and other azine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives and other compounds containing a nitrogen-containing six-membered ring structure (also including phosphine oxides on the heterocyclic ring) Substituent compounds) etc.
  • the thickness of the hole blocking layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.
  • the electron injection layer may adopt alkali metals or metals, such as materials such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals Wait.
  • the electron injection layer may have a thickness of about 0.5 nm to 2 nm.
  • performing damage repair on the surface of the spacer column may include: on the substrate formed with the aforementioned pattern, irradiating the spacer column with ultraviolet light to eliminate the surface damage of the spacer column.
  • OLED display devices Since organic materials easily react with water and oxygen, OLED display devices have very high requirements for packaging. After years of development, the existing thin-film encapsulation methods can basically meet the overall requirements of flexible OLEDs for water vapor and oxygen permeability, and have the characteristics of lightness, thinness, and easy bending. However, in actual production, there is still a problem of sub-pixel packaging failure, which reduces the yield. The study found that the sub-pixel encapsulation failure in actual production was caused by the surface damage of the spacer column. Since the organic light-emitting layer needs to be evaporated onto the display substrate through a fine metal mask, spacer columns are formed on the display substrate to support the fine metal mask.
  • the process of evaporating the organic light-emitting layer by using a fine metal mask includes: firstly aligning the fine metal mask with the first sub-pixel and placing it against the surface of the spacer column, and then vapor-depositing the first sub-pixel in the first sub-pixel. Color light-emitting layer, after the evaporation is completed, the fine metal mask is separated from the spacer column. Then, the fine metal mask is aligned with the second sub-pixel and placed on the surface of the spacer column, and the second color light-emitting layer is evaporated in the second sub-pixel. After the evaporation is completed, the fine metal mask is separated from the spacer. column.
  • the fine metal mask is aligned with the third sub-pixel and placed on the surface of the spacer column, and the third color light-emitting layer is evaporated in the third sub-pixel. After the evaporation is completed, the fine metal mask is separated from the spacer column.
  • FIG. 11 is a schematic diagram of sharp protrusions generated on the surface of the septum column. As shown in FIG. 11, due to the multiple friction between the fine metal mask and the spacer column during the alignment process before evaporation and the separation process after evaporation, the surface of the spacer column is damaged, so that the spacer column 25 The surface produces some sharp projections 26 . Actual measurements show that the height of the sharp protrusions can reach 0.5 ⁇ m to 1 ⁇ m.
  • these sharp protrusions are located on the top of the spacer column, that is, on the side of the spacer column facing the encapsulation layer formed subsequently, these sharp protrusions are easy to pierce the encapsulation layer, allowing water and oxygen to penetrate into the organic light-emitting device through the cracks. layer, resulting in package failure.
  • FIG. 12 is a schematic diagram after repairing the surface damage of the spacer column according to an exemplary embodiment of the present disclosure.
  • the damage repair process on the surface of the spacer column may be performed in the following manner. First, set the spacer column mask of the patterned spacer column on the display substrate. The alignment method of the spacer column mask is the same as that of the patterned spacer column, that is, the spacer column mask The position of the light-transmitting area in the plate corresponds to the position of the spacer column in the display substrate. Subsequently, ultraviolet light is used for irradiation, and the ultraviolet light is irradiated to the spacer column through the light-transmitting area of the spacer column mask.
  • the convex part is in an expanded state, and the flat part is in a contracted state, so the convexity on the surface of the spacer column changes from sharp to gentle, and the height is high.
  • the height h of the gentle protrusion can be reduced to less than 0.2 ⁇ m, and the surface damage repair of the spacer column is realized, as shown in FIG. 12 .
  • the irradiation intensity of the ultraviolet light may be about 5 mW/cm 2 to 20 mW/cm 2
  • the irradiation time of the ultraviolet light may be about 100 seconds to 300 seconds.
  • a cathode pattern is formed.
  • forming the cathode pattern may include: on the substrate on which the aforementioned pattern is formed, forming a cathode 24 pattern through an evaporation process, and the cathode 24 is connected to the organic light emitting layer 23 , as shown in FIG. 13 .
  • the cathodes 24 of the plurality of sub-pixels have a planar integral structure, and the cathodes 24 wrap the surfaces of the spacer pillars 25 .
  • the cathode may be a metal material, which may be magnesium (Mg), silver (Ag), or aluminum (Al), or an alloy material, such as an alloy of Mg:Ag, with a ratio of about Mg:Ag 9:1 to 1:9, the thickness of the cathode may be about 10 nm to 20 nm.
  • the pattern of the light emitting structure layer 104 is prepared on the driving structure layer 103 , as shown in FIG. 13 .
  • the anode 21 , the organic light-emitting layer 23 and the cathode 24 in the light-emitting structure layer 104 constitute an OLED light-emitting element
  • the organic light-emitting layer 23 is arranged between the anode 21 and the cathode 24
  • holes and electrons are respectively formed by the anode 21 .
  • the cathode 24 is injected into the organic light-emitting layer 23, and when electrons and holes meet in the organic light-emitting layer 23, the electrons and holes recombine to generate excitons.
  • the organic light-emitting layer 23 emits light of corresponding gray scale.
  • the forming of the encapsulation structure layer may include: depositing a first inorganic thin film using an open mask to form the first encapsulation layer 31 . Subsequently, an organic material is inkjet printed on the first encapsulation layer by an inkjet printing process, and the second encapsulation layer 32 is formed after curing to form a film. Subsequently, a second inorganic thin film is deposited using an open mask to form a third encapsulation layer 33 , as shown in FIG. 14 .
  • the first encapsulation layer and the third encapsulation layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multi-layer or composite layer, the second encapsulation layer can be made of resin material.
  • the encapsulation structure layer 105 may include a stacked first encapsulation layer 31, a second encapsulation layer 32 and a third encapsulation layer 33 to form a stacked structure of inorganic material/organic material/inorganic material, and the organic material layer is arranged on the two inorganic materials. Between the layers, it can be ensured that the external water vapor cannot enter the light emitting structure layer.
  • the thickness of the first encapsulation layer may be approximately 800 nm to 1200 nm
  • the thickness of the second encapsulation layer may be approximately 6000 nm to 10000 nm
  • the thickness of the third encapsulation layer may be approximately 600 nm to 800 nm.
  • a touch structure layer may be formed on the package structure layer, and the touch structure layer may include a touch electrode layer, or a touch electrode layer and a touch insulation layer.
  • the preparation process of the display substrate may further include processes such as peeling off the glass carrier 1 , attaching the back film, cutting, etc., which are not limited in the present disclosure.
  • the present disclosure adopts the spacer column including the polymer elastomer and the inorganic nanoparticles, and performs the repairing treatment on the spacer column after evaporating the light-emitting layer , effectively repairing the surface damage of the spacer column caused by the fine metal mask, so that the protrusion on the surface of the spacer column changes from sharp to gentle, and the height of the protrusion is greatly reduced, avoiding the protrusion piercing the packaging layer, thus avoiding The package failure is effectively guaranteed, the problem of sub-pixel package failure is eliminated, and the yield rate is improved.
  • part of the light emitted by the organic light emitting layer may be incident on the encapsulation layer through the spacer column and then exit.
  • the spacer column is usually made of an organic material with a higher refractive index. According to the optical principle, when light is incident from an optically denser medium with a larger refractive index to an optically rarer medium with a smaller refractive index, if the incident angle is greater than the total reflection angle at the interface between the optically denser medium and the optically rarer medium, total emission will occur.
  • the transmission direction of the light in the spacer column can be changed through the refraction and/or reflection of the light by the inorganic nanoparticles, the total reflection of the light at the interface of the spacer column is eliminated, and the effective The light output efficiency is improved, and the luminous brightness is effectively increased.
  • external water and oxygen may penetrate into the organic light-emitting layer through the spacer column.
  • the spacer column is usually made of an organic material, and the water and oxygen permeability is high, so the ability to block water and oxygen is weak.
  • the transistors in the driving structure layer may be a top gate structure, or may be a bottom gate structure, may be a single gate structure, or may be a double gate structure.
  • the substrate may be a glass substrate, which is not limited in the present disclosure.
  • FIG. 15 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a sub-pixel in the OLED display substrate.
  • the display substrate may include a driving circuit layer 103 disposed on the substrate 10 , a light emitting structure layer 104 disposed on the side of the driving circuit layer 103 away from the substrate 10 , and a light emitting structure layer 104 disposed away from the substrate 10
  • the package structure layer 105 on one side.
  • the structures of the driving circuit layer 103 and the encapsulation structure layer 105 in the display substrate of this exemplary embodiment are the same as those of the previous embodiments, the difference is that the pixels in the light emitting structure layer 104 of this exemplary embodiment are
  • the definition layer 22 and the spacer column 25 are made of the same material and can be formed simultaneously through the same patterning process. As shown in FIG.
  • the light emitting structure layer 104 may include an anode 21 , a pixel definition layer 22 , an organic light emitting layer 23 , a cathode 24 and a spacer column 25
  • the pixel definition layer 22 is provided with a pixel opening exposing the anode 21
  • the organic light emitting layer 23 is arranged between the anode 21 and the cathode 24
  • the spacer column 25 is arranged on the pixel definition layer 22
  • the material of the pixel definition layer 22 and the spacer column 25 may include polymer elastomer and inorganic nanoparticles, that is, the pixel definition layer 22 Same material as septum column 25 .
  • the materials and parameters of the polymer elastomer and the inorganic nanoparticles may be the same as those in the previous embodiments, and will not be repeated here.
  • This exemplary embodiment shows that in the preparation process of the substrate, the processes of forming the substrate, forming the driving structure layer, forming the anode, forming the organic light-emitting layer, repairing the damage to the spacer column, forming the cathode and forming the packaging structure layer can be similar to the previous embodiments. The same, the difference is that the pixel definition layer and the spacer column can be formed simultaneously by one patterning process in this exemplary embodiment.
  • the following processes may be used to simultaneously form the pixel definition layer and the spacer column using one patterning process.
  • the polymer elastomer, the inorganic nanoparticles and the photosensitizer are first mixed to form a sol, and then the sol is uniformly coated on the substrate forming the aforementioned pattern to form a pixel definition film. Subsequently, the pixel-defining film is exposed using a gray-tone mask, and after development, a fully exposed area, a partially exposed area and an unexposed area are formed.
  • the pixel-defining film in the fully exposed area is retained to form a spacer column pattern, and the partially exposed area Part of the thickness of the pixel-defining film is removed to form a pixel-defining layer pattern, and the pixel-defining film in the unexposed area is completely removed to form a pixel opening pattern.
  • the gray-tone mask when repairing damage to the spacer column, is first set on the display substrate, and the position of the light-transmitting area (completely exposed area) of the gray-tone mask is the same as the spacer column.
  • the position of the reticle corresponds to the corresponding position, and then irradiated with ultraviolet light equipment, and the ultraviolet light is irradiated to the spacer column through the light-transmitting area of the gray tone mask, so as to realize the surface damage repair of the spacer column.
  • the exemplary embodiment of the present disclosure effectively repairs the spacer column caused by the fine metal mask by adopting the spacer column including the polymer elastomer and the inorganic nanoparticles, and performing the repairing treatment on the spacer column after evaporating the light-emitting layer.
  • the surface damage makes the protrusion on the surface of the spacer column change from sharp to gentle, and the height of the protrusion is greatly reduced, which prevents the protrusion from piercing the packaging layer, thus avoiding packaging failure, effectively ensuring the packaging effect, and eliminating sub-pixels.
  • the problem of package failure improves the yield.
  • part of the light emitted by the organic light emitting layer will be incident on the encapsulation layer through the pixel definition layer and then exit.
  • the pixel definition layer usually adopts an organic material with a higher refractive index. According to the optical principle, when light is incident from an optically denser medium with a larger refractive index to an optically rarer medium with a smaller refractive index, if the incident angle is greater than the total reflection angle at the interface between the optically denser medium and the optically rarer medium, total emission will occur.
  • the transmission direction of light in the pixel definition layer can be changed through the refraction and/or reflection of light by the inorganic nanoparticles, and the transmission of light at the interface of the pixel definition layer can be eliminated. Total reflection, which effectively improves the light output efficiency and effectively increases the luminous brightness.
  • external water and oxygen may penetrate into the organic light emitting layer through the pixel definition layer.
  • the pixel definition layer is usually made of organic materials, and the water and oxygen permeability is high, so the ability to block water and oxygen is weak.
  • the pixel definition layer and the spacer column including the inorganic nanoparticles since the inorganic nanoparticles have a strong ability to block water and oxygen, the ability of the pixel definition layer and the spacer column to block water and oxygen is effectively improved, and the external water and oxygen are reduced.
  • the probability of oxygen permeating into the organic light-emitting layer through the pixel definition layer and the spacer column effectively increases the service life of the display substrate.
  • the present disclosure also provides a preparation method of a display substrate.
  • the manufacturing method of the display substrate may include:
  • a pixel definition layer and a spacer column are formed on the driving structure layer, the spacer column is disposed on the surface of the pixel definition layer on the side away from the driving structure layer, and the spacer column is on the positive side of the substrate.
  • the projection is within the range of the orthographic projection of the pixel definition layer on the substrate;
  • the surface of the spacer column on the side away from the driving structure layer has protrusions, and the height of the protrusions is less than 0.2 ⁇ m.
  • the material of the spacer column includes a polymer elastomer and nanoparticles
  • the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology
  • the mesh diameter of the cross-linked network is 0.5 ⁇ m to 2.0 ⁇ m; the repairing treatment of the spacer column may include:
  • the spacer column is irradiated with ultraviolet light, and the polymer elastomer undergoes expansion and contraction of the cross-linked network under ultraviolet light irradiation, so that the protrusion on the surface of the spacer column changes from sharp to gentle, and the The height of the protrusions is less than 0.2 ⁇ m.
  • the irradiation intensity of the ultraviolet light may be about 5 mW/cm 2 to 20 mW/cm 2
  • the irradiation time of the ultraviolet light may be about 100 seconds to 300 seconds.
  • forming a pixel definition layer and a spacer column on the driving structure layer may include: forming a pixel definition layer on the driving structure layer; using a spacer column mask to form a pixel definition layer on the pixel definition layer A septum column is formed on it;
  • Irradiating the spacer column with ultraviolet light may include: arranging the spacer column mask on the display substrate, irradiating with ultraviolet light equipment, and the ultraviolet light passing through the transparent surface of the spacer column mask. An area of light impinges on the spacer column.
  • forming the pixel definition layer and the spacer column on the driving structure layer may include: using a gray-tone mask to form the pixel definition layer and the spacer column on the driving structure layer through the same patterning process post;
  • Irradiating the spacer column with ultraviolet light includes: arranging the gray-tone mask on the display substrate, irradiating with ultraviolet light equipment, and irradiating the ultraviolet light through the light-transmitting area of the gray-tone mask onto the septum column.
  • the spacer column including the polymer elastomer and the inorganic nanoparticles is used, and the spacer column is repaired after the luminescent layer is evaporated, so that the encapsulation effect is effectively guaranteed, and the light output efficiency is effectively improved. , effectively increasing the service life of the display substrate.
  • the preparation method of the present disclosure has less process improvement, high compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, a car monitor, a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括设置在驱动结构层上的像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述的凸起高度小于0.2μm。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，简称OLED)作为一种新型的平板显示逐渐受到更多的关注。OLED为主动发光元件，具有亮度高、色彩饱和、超薄、广视角、较低耗电、极高反应速度和可弯曲等优点，能够较好地满足用户个性化的需求。随着显示技术的不断发展，以OLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一种显示基板，包括设置在驱动结构层上的像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述的凸起高度小于0.2μm。
在示例性实施方式中，所述隔垫柱的材料包括聚合物弹性体和纳米颗粒，所述隔垫柱中纳米颗粒占比为0.5wt％至5wt％。
在示例性实施方式中，所述纳米颗粒的直径为20nm至100nm。
在示例性实施方式中，所述纳米颗粒包括甲基修饰无机纳米颗粒。
在示例性实施方式中，所述甲基修饰无机纳米颗粒包括甲基修饰无机氧 化硅纳米颗粒、甲基修饰无机氧化锌纳米颗粒和甲基修饰无机氧化锆纳米颗粒中的至少一种。
在示例性实施方式中，所述聚合物弹性体包括聚氨酯、聚硅氧烷和液晶嵌段聚合物中的至少一种，所述聚合物弹性体的形貌为通过化学连接形成的交联网络，所述交联网络的网孔直径为0.5μm至2.0μm。
在示例性实施方式中，所述隔垫柱的高度为1μm至1.5μm。
在示例性实施方式中，所述发光结构层还包括像素定义层，所述隔垫柱设置在所述像素定义层远离基底的一侧，所述像素定义层和隔垫柱的材料相同。
在示例性实施方式中，所述隔垫柱和像素定义层为一体结构。
一种显示装置，包括前述的显示基板。
一种显示基板的制备方法，包括：
在驱动结构层上形成像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；
采用精细金属掩模版蒸镀有机发光层；
对所述隔垫柱进行修复处理，所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述凸起的高度小于0.2μm。
在示例性实施方式中，所述隔垫柱的材料包括聚合物弹性体和纳米颗粒，所述聚合物弹性体包括聚氨酯、聚硅氧烷和液晶嵌段聚合物中的至少一种，形貌为通过化学连接形成的交联网络，所述交联网络的网孔直径为0.5μm至2.0μm；对所述隔垫柱进行修复处理，包括：
对所述隔垫柱进行紫外光照射，所述聚合物弹性体在紫外光照射下发生交联网络的扩张与收缩，使所述隔垫柱表面的凸起由尖锐变为平缓，且所述凸起的高度小于0.2μm。
在示例性实施方式中，所述紫外光的照射强度为5mW/cm 2至20mW/cm 2，所述紫外光的照射时间为100秒至300秒。
在示例性实施方式中，
在驱动结构层上形成像素定义层和隔垫柱，包括：在所述驱动结构层上形成像素定义层；采用隔垫柱掩膜版，在所述像素定义层上形成隔垫柱；
对所述隔垫柱进行紫外光照射，包括：将所述隔垫柱掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述隔垫柱掩膜版的透光区域照射到所述隔垫柱上。
在示例性实施方式中，
在驱动结构层上形成像素定义层和隔垫柱，包括：采用灰色调掩膜版，通过同一次图案化工艺在在所述驱动结构层上形成像素定义层和隔垫柱；
对所述隔垫柱进行紫外光照射，包括：将所述灰色调掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述灰色调掩膜版的透光区域照射到所述隔垫柱上。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种OLED显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种像素驱动电路的等效电路示意图；
图4为一种像素驱动电路的工作时序图；
图5为本公开示例性实施例一种显示基板的剖面结构示意图；
图6为本公开示例性实施例形成驱动结构层图案后的示意图；
图7为本公开示例性实施例形成阳极图案后的示意图；
图8为本公开示例性实施例形成像素定义层图案后的示意图；
图9为本公开示例性实施例形成隔垫柱图案后的示意图；
图10为本公开示例性实施例形成有机发光层图案后的示意图；
图11为隔垫柱表面产生尖锐凸起的示意图；
图12为本公开示例性实施例隔垫柱表面损伤修复后的示意图；
图13为本公开示例性实施例形成阴极图案后的示意图；
图14为本公开示例性实施例形成封装结构层图案后的示意图；
图15为本公开示例性实施例另一种显示基板的剖面结构示意图。
附图标记说明:
1—玻璃载板；          10—基底；             21—阳极；
22—像素定义层；       23—有机发光层；       24—阴极；
25—隔垫柱；           26—凸起；             31—第一封装层；
32—第二封装层；       33—第三封装层；       101—晶体管；
102—存储电容；        103—驱动结构层。      104—发光结构层；
105—封装结构层。
具体实施方式
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，可能夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的任意一个实现方式并不一定限定于图中所示尺寸，附图中部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的任意一个实现方式不局限于附图所示的形状或数值 等。
本文中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本文中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述实施方式和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系可根据描述的构成要素的方向进行适当地改变。因此，不局限于在文中说明的词句，根据情况可以适当地更换。
在本文中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本文中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(或称漏电极端子、漏区域或漏电极)与源电极(或称源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本文中，沟道区域是指电流主要流过的区域。
在本文中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本文中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其 它功能元件等。
在本文中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本文中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本文中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种OLED显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉 冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij。每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括显示区域和位于显示区域外围的边框区域。如图2所示，显示基板的显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图3为一种像素驱动电路的等效电路示意图。如图3所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、 1个存储电容C1和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C1的第一端与第一电源线VDD连接，存储电容C1的第二端与第二节点N2连接，即存储电容C1的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C1的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体 管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图4为一种像素驱动电路的工作时序图。下面通过图3示例的像素驱动电路的工作过程说明本公开示例性实施例，图3中的像素驱动电路包括7个 晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C1和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C1进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C1的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C1，存储电容C1的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E 的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图5为本公开示例性实施例一种显示基板的剖面结构示意图，示意了OLED显示基板中一个子像素的结构。如图5所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层103、设置在驱动电路层103远离基底10一侧的发光结构层104以及设置在发光结构层104远离基底10一侧的封装结构层105。在示例性实施方式中，驱动电路层103可以包括晶体管101和存储电容102。在示例性实施方式中，发光结构层104是使有机材料发光的发光器件，发光结构层104可以包括阳极21、像素定义层22、有机发光层23、阴极24和隔垫柱25，像素定义层22设置有暴露出阳极21的像素开口，有机发光层23设置在阳极21和阴极24之间，隔垫柱25设置在像素定义层22远离基底10一侧的表面上，且隔垫柱25在基底上的正投影位于像素定义层22在基底上的正投影的范围之内。在示例性实施方式中，隔垫柱(Photo Spacer，简称PS)25配置为支撑蒸镀有机发光材料使用的精细金属掩模版或者开放式掩膜版。封装结构层105可以包括设置在发光结构层104远离基底一侧的第一封装层、设置在第一封装层远离基底一侧的第二封装层和设置在第二封装层远离基底一侧的第三封装层，有机材料的第二封装层设置在无机材料的第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料的叠层结构。
在示例性实施方式中，隔垫柱25的材料可以包括聚合物弹性体和纳米颗 粒。所述聚合物弹性体的材料可以包括聚氨酯、聚硅氧烷或液晶嵌段聚合物等，所述纳米颗粒可以为无机纳米颗粒，所述无机纳米颗粒可以为甲基修饰无机纳米颗粒，甲基修饰无机纳米颗粒可以包括甲基修饰无机氧化硅纳米颗粒、甲基修饰无机氧化锌纳米颗粒或甲基修饰无机氧化锆纳米颗粒等。
在示例性实施方式中，甲基修饰无机纳米颗粒可以通过表面活性剂的处理方式将甲基引入到无机纳米颗粒的表面。
在示例性实施方式中，所述聚合物弹性体的形貌为交联网络，所述无机纳米颗粒分散在聚合物弹性体组成的交联网络的网孔中以支撑交联网络，交联网络是聚合物弹性体通过化学连接形成的。
在示例性实施方式中，无机纳米颗粒的粒径可以约为20nm至100nm。
在示例性实施方式中，隔垫柱中无机纳米颗粒占比可以约为0.5wt％至5wt％。
在示例性实施方式中，隔垫柱25的的厚度可以约为1.0μm至1.5μm。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，显示基板的制备过程包括如下操作。
(1)在玻璃载板上形成基底。在一种示例性实施方式中，在玻璃载板上形成基底可以包括：在玻璃载板1上涂覆第一柔性材料薄膜，固化成膜后形成第一柔性层；在第一柔性层远离玻璃载板一侧的表面上涂覆第二柔性材料薄膜，固化成膜后形成第二柔性层；在第二柔性层远离玻璃载板一侧的表面上涂覆第三柔性材料薄膜，固化成膜后形成第三柔性层，在玻璃载板上形成柔性的基底，基底包括叠设的第一柔性层、第二柔性层和第三柔性层。在示例性实施方式中，第一柔性层、第二柔性层和第三柔性层可以采用相同的材料，或者可以采用不同的材料。在一些可能的实现方式中，第一柔性层、第二柔性层和第三柔性层的材料可以包括聚酰亚胺(PI)。
在另一种示例性实施方式中，在玻璃载板1上形成基底可以包括：先在玻璃载板上涂覆第一柔性材料薄膜，固化成膜后形成第一柔性层；随后在第一柔性层上沉积第一无机材料薄膜，形成覆盖第一柔性层的第一无机层；然后在第一无机层上涂覆第二柔性材料薄膜，固化成膜后形成第二柔性层；然后在第二柔性层上沉积第二无机材料薄膜，形成覆盖第二柔性层的第二无机层，在玻璃载板形成柔性的基底，基底包括叠设的第一柔性层、第一无机层、第二柔性层和第二无机层。在示例性实施方式中，第一柔性材料薄膜和第二柔性材料薄膜的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)、压敏胶(PSA)或经表面处理的聚合物软膜等材料，第一、第二无机材料薄膜的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一无机层和第二无机层可以称之第一阻挡(Barrier)层和第二阻挡层。
在又一种示例性实施方式中，在玻璃载板1上形成基底可以包括：先在玻璃载板上涂覆第一柔性材料薄膜，固化成膜后形成第一柔性层；随后在第一柔性层上沉积第一无机材料薄膜，形成覆盖第一柔性层的第一无机层；然后在第一无机层上沉积非晶硅薄膜，形成覆盖第一无机层的非晶硅层；然后在非晶硅层上涂覆第二柔性材料薄膜，固化成膜后形成第二柔性层；然后在第二柔性层上沉积第二无机材料薄膜，形成覆盖第二柔性层的第二无机层，在玻璃载板形成柔性的基底，基底包括叠设的第一柔性层、第一无机层、半导体层、第二柔性层和第二无机层。在示例性实施方式中，半导体层的材料 可以采用非晶硅(a-si)。
在示例性实施方式中，基底可以是刚性基底。
(2)在基底上形成驱动结构层图案，如图6所示。在示例性实施方式中，驱动结构层可以包括构成像素驱动电路的多个晶体管和存储电容，图6中示意了三个子像素，每个子像素的驱动结构层以一个晶体管101和一个存储电容102为例进行示意。在示例性实施方式中，驱动结构层的制备过程可以包括：
在基底10上依次沉积第一绝缘薄膜和半导体层薄膜，通过图案化工艺对半导体层薄膜进行构图，形成覆盖整个基底10的第一绝缘层11，以及设置在第一绝缘层11上的半导体层图案，半导体层图案至少包括设置在每个子像素内的有源层。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行构图，形成覆盖半导体层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一金属层图案，第一金属层图案至少包括设置在每个子像素内的栅电极和第一电容电极。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行构图，形成覆盖第一金属层的第三绝缘层13，以及设置在第三绝缘层13上的第二金属层图案，第二金属层图案至少包括设置在每个子像素内的第二电容电极，第二电容电极的位置与第一电容电极的位置相对应。
随后，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行构图，形成覆盖第二金属层的第四绝缘层14图案，第四绝缘层14上开设有多个过孔图案，多个过孔图案至少包括设置在每个子像素内的两个第一过孔，两个第一过孔的位置分别有源层的两端位置相对应，两个第一过孔内的第四绝缘层14、第三绝缘层13和第二绝缘层12被刻蚀掉，暴露出有源层的表面。
随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行构图，在第四绝缘层14上形成第三金属层图案，第三金属层图案至少包括设置在每个子像素内的源电极和漏电极，源电极和漏电极分别通过第一过孔与本子 像素的有源层连接，使源电极和漏电极之间形成导电沟道。
随后，涂覆一层平坦薄膜，形成覆盖整个基底10的平坦(PLN)层15，通过图案化工艺在平坦层15上形成过孔图案，过孔图案至少包括设置在每个子像素内的第二过孔，第二过孔内的平坦层15被去掉，暴露出漏电极的表面。在示例性实施方式中，平坦层15远离基底10一侧的表面为平直的表面，平坦化层可以采用树脂等材料。
至此，所形成的结构包括：设置在玻璃载板1上的基底10，以及设置在基底10上驱动结构层103，如图6所示。每个子像素中的有源层、栅电极、源电极和漏电极组成晶体管101，第一电容电极和第二电容电极组成存储电容102。在一示例性实施方式中，晶体管可以是像素驱动电路中的驱动晶体管，驱动晶体管可以是薄膜晶体管。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。平坦层类采用有机材料，如树脂等。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者是多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
(3)形成阳极图案。在示例性实施方式中，形成阳极图案可以包括：在形成前述图案的基底上沉积导电薄膜，通过图案化工艺对导电薄膜进行构图，形成导电层图案，导电层图案至少包括设置在每个子像素内的阳极21，阳极21通过第二过孔与第一晶体管101的漏电极连接，如图7所示。
在示例性实施方式中，导电薄膜可以采用单层的透明导电材料，如氧化 铟锡(ITO)或氧化铟锌(IZO)，或者导电薄膜可以采用复合层的金属材料和透明导电材料，如Ag/ITO、Ag/IZO或者ITO/Ag/ITO等，复合层中金属材料的厚度可以约为80nm至100nm，复合层中透明导电材料的厚度可以约为5nm至20nm，使阳极在可见光区的平均反射率约为85％～95％。
(4)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行掩膜曝光和显影，形成像素定义(PDL)层22，在每个子像素内，像素定义层22上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出阳极21的表面，如图8所示。
在示例性实施方式中，像素定义层的厚度可以约为1μm至1.5μm。
在示例性实施方式中，在平行于基底的平面内，像素开口的形状可以是正方形、矩形、圆形、椭圆形或六边形等，可以根据实际需要设置，本公开在此不做限定。在示例性实施方式中，像素定义薄膜可以采用聚酰亚胺、亚力克或聚对苯二甲酸乙二醇酯等材料。
(6)形成隔垫柱图案。在示例性实施方式中，形成隔垫柱图案可以包括：在形成前述图案的基底上涂覆隔垫薄膜，通过图案化工艺对隔垫薄膜进行图案化处理，形成隔垫柱25图案，隔垫柱25设置在像素定义层22远离基底一侧的表面上，隔垫柱25在基底上的正投影位于像素定义层22在基底上的正投影的范围之内，如图9所示。
在示例性实施方式中，对于显示基板上的多个像素单元，至少一个包含R子像素、G子像素和B子像素的像素单元中可以设置至少一个隔垫柱。在显示区域，多个隔垫柱可以均匀分布，在边框区域，多个隔垫柱可以设置在封装层边界以内的区域，封装层边界以外的区域没有设置隔垫柱。
在示例性实施方式中，隔垫柱的材料可以包括聚合物弹性体和无机纳米颗粒。聚合物弹性体的材料可以包括聚氨酯、聚硅氧烷或液晶嵌段聚合物等，无机纳米颗粒可以为甲基修饰无机纳米颗粒，甲基修饰无机纳米颗粒可以包括甲基修饰无机氧化硅纳米颗粒、甲基修饰无机氧化锌纳米颗粒或甲基修饰无机氧化锆纳米颗粒等。聚合物弹性体的形貌为通过化学连接形成的交 联网络，无机纳米颗粒分散在聚合物弹性体组成的交联网络的网孔中以支撑交联网络。
在示例性实施方式中，聚合物弹性体的分子量可以约为百万至千万级，聚合物弹性体的折射率可以约为1.5至1.7，交联网络的网孔直径可以约为0.5μm至2.0μm。
在示例性实施方式中，甲基修饰无机纳米颗粒可以通过表面活性剂的处理方式将甲基引入到无机纳米颗粒的表面。
在示例性实施方式中，无机纳米颗粒的直径可以约为20nm至100nm。
在示例性实施方式中，无机纳米颗粒所占比重可以约为隔垫柱的0.5wt％至5wt％，无机纳米颗粒在聚合物弹性体中可以是均匀分布。
在平行于基底的平面内，隔垫柱的形状可以是正方形、矩形、圆形、椭圆形或六边形等。对于矩形状的隔垫柱，隔垫柱的宽度可以约为5μm至10μm。
在示例性实施方式中，隔垫柱的高度可以约为1μm至1.5μm。
在垂直于基底的平面内，隔垫柱的截面形状可以是梯形，梯形的底角可以约为40°至60°。
在示例性实施方式中，涂覆隔垫薄膜和图案化工艺可以采用如下方式。首先，将聚合物弹性体、无机纳米颗粒和感光剂混合后形成溶胶，然后将溶胶均匀涂布在形成前述图案的基底上形成隔垫薄膜，随后采用隔垫柱掩膜版对隔垫薄膜进行曝光和显影后，通过局部紫外光固化过程形成隔垫柱图案。
在示例性实施方式中，隔垫柱掩膜版包括透光区域和不透光区域，感光剂采用负性感光剂。对隔垫薄膜曝光后，与隔垫柱掩膜版的透光区域位置对应的隔垫薄膜形成完全曝光区域，与隔垫柱掩膜版的不透光区域位置对应的隔垫薄膜形成未曝光区域。显影后，完全曝光区域的隔垫薄膜被保留，形成隔垫柱图案，未曝光区域的隔垫薄膜被完全去除。
(7)形成有机发光层图案。在示例性实施方式中，形成有机发光层图案可以包括：在形成前述图案的基底上设置蒸镀掩膜版，通过蒸镀工艺形成有 机发光层13图案，有机发光层23与像素开口内的阳极21连接，如图10所示。
在示例性实施方式中，有机发光层可以包括发光层(Emitting Layer，简称EML)，以及如下任意一层或多层：空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，不同子像素的发光层不同。例如，红色子像素包括红色发光层，绿色子像素包括绿色发光层，蓝色子像素包括蓝色发光层。
在示例性实施方式中，有机发光层可以采用精细金属掩模版(FMM，Fine Metal Mask)和开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨打印工艺制备形成。虽然附图中示意的多个子像素的有机发光层是相互隔离的结构，但在示例性实施方式中，为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在示例性实施方式中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，但通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。
在示例性实施方式中，可以采用如下制备方法制备有机发光层。在制备完成隔离柱后，先采用开放式掩膜版依次蒸镀空穴注入层和空穴传输层，在显示基板上形成空穴注入层和空穴传输层的共通层，即所有子像素的空穴注入层是连通的，所有子像素的空穴传输层是连通的。空穴注入层和空穴传输层各自的面积大致是相同的，厚度不同。随后，采用精细金属掩模版在不同的子像素分别蒸镀电子阻挡层和红色发光层、电子阻挡层和绿色发光层、以及电子阻挡层和蓝色发光层，相邻子像素的电子阻挡层和发光层是可以有少量的交叠(例如，交叠部分占各自发光层图案的面积小于10％)，或者可以 是隔离的。随后，采用开放式掩膜版依次蒸镀空穴阻挡层、电子传输层和电子注入层，在显示基板上形成空穴阻挡层、电子传输层和电子注入层的共通层，即所有子像素的空穴阻挡层是连通的，所有子像素的电子传输层是连通的，所有子像素电子注入层的是连通的。
在示例性实施方式中，空穴注入层、空穴传输层、空穴阻挡层、电子传输层、电子注入层和阴极中的一层或多层在基底上的正投影是连续的。在一些示例中，至少一行或一列的子像素的空穴注入层、空穴传输层、空穴阻挡层、电子传输层、电子注入层和阴极中的至少一层是连通的。在一些示例中，多个子像素的空穴注入层、空穴传输层、空穴阻挡层、电子传输层、电子注入层和阴极中的至少一层是连通的。
在示例性实施方式中，由于空穴阻挡层是共通层，而不同子像素的发光层是隔离的，因而发光层在基板上的正投影位于空穴阻挡层在基板上的正投影的范围之内，空穴阻挡层的面积大于发光层的面积。由于空穴阻挡层是共通层，因而空穴阻挡层在基板上的正投影至少包括两个子像素的发光区域在基板上的正投影。在示例性实施方式中，至少部分子像素的发光层在基板上的正投影与像素驱动电路驱动在基板上的正投影有交叠。
在示例性实施方式中，电子阻挡层可以作为空穴传输层和发光层之间的微腔调节层，使得阴极和阳极之间的有机发光层的厚度可以按照满足光学微谐振腔的光程要求设计，以获得最优的出光强度和颜色。
在示例性实施方式中，发光层可以包括主体(Host)材料和掺杂在主体材料中的客体(Dopant)材料，发光层客体材料的掺杂比例为1％至20％。在该掺杂比例范围内，一方面发光层主体材料可将激子能量有效转移给发光层客体材料来激发发光层客体材料发光，另一方面发光层主体材料对发光层客体材料进行了“稀释”，有效改善了发光层客体材料分子间相互碰撞、以及能量间相互碰撞引起的荧光淬灭，提高了发光效率和器件寿命。在示例性实施方式中，掺杂比例是指客体材料的质量与发光层的质量之比，即质量百分比。在示例性实施方式中，可以通过多源蒸镀工艺共同蒸镀主体材料和客体材料，使主体材料和客体材料均匀分散在发光层中，可以在蒸镀过程中通过控制客体材料的蒸镀速率来调控掺杂比例，或者通过控制主体材料和客体材 料的蒸镀速率比来调控掺杂比例。
在示例性实施方式中，空穴注入层可以采用无机的氧化物，如钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物或锰氧化物，或者可以采用强吸电子体系的p型掺杂剂和空穴传输材料的掺杂物。在示例性实施方式中，空穴注入层的厚度可以约为5nm至20nm。
在示例性实施方式中，空穴传输层可以采用空穴迁移率较高的材料，如芳胺类化合物，其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中，空穴传输层的厚度可以约为60nm至150nm。
在示例性实施方式中，电子阻挡层可以采用具有空穴传输特性的芳胺类化合物，其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中，电子阻挡层的厚度可以约为5nm至20nm。
在示例性实施方式中，发光层可以包括发光主体材料和发光客体材料。发光主体材料可以采用双极性单主体，或者可以采用由空穴型主体和电子型主体共混形成的双主体。发光客体材料可以采用磷光材料、荧光材料、延迟荧光材料等。在示例性实施方式中，发光层的厚度可以约为10nm至25nm。
在示例性实施方式中，空穴阻挡层和电子传输层可以采用芳族杂环化合物，例如苯并咪唑衍生物、咪唑并吡啶衍生物、苯并咪唑并菲啶衍生物等咪唑衍生物；嘧啶衍生物、三嗪衍生物等嗪衍生物；喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等包含含氮六元环结构的化合物(也包括在杂环上具有氧化膦系的取代基的化合物)等。在示例性实施方式中，空穴阻挡层的厚度可以约为5nm至15nm，电子传输层的厚度可以约为20nm至50nm。
在示例性实施方式中，电子注入层可以采用碱金属或者金属，例如氟化锂(LiF)、镱(Yb)、镁(Mg)或钙(Ca)等材料，或者这些碱金属或者金属的化合物等。在示例性实施方式中，电子注入层的厚度可以约为0.5nm至2nm。
(8)对隔垫柱的表面进行损伤修复。在示例性实施方式中，对隔垫柱的表面进行损伤修复可以包括：在形成前述图案的基底上，对隔垫柱进行紫外 光照射，消除隔垫柱的表面损伤。
由于有机材料易与水氧反应，因此OLED显示装置对封装有非常高的要求。经过多年的发展，现有薄膜封装方式已经能够基本满足柔性OLED整体有关水汽和氧气穿透率的要求，且具有轻薄、易弯折等特点。但实际生产中，仍然存在子像素封装失效的问题，降低了良品率。研究发现，实际生产中出现子像素封装失效，是由于隔垫柱存在表面损伤导致的。由于有机发光层需要通过精细金属掩模版蒸镀到显示基板上，因而显示基板上会制作隔垫柱来支撑精细金属掩模版。通常，采用精细金属掩模版蒸镀有机发光层的工艺包括：先将精细金属掩模版与第一子像素对位并靠设在隔垫柱的表面上，在第一子像素中蒸镀第一颜色发光层，蒸镀完成后使精细金属掩模版离开隔垫柱。然后将精细金属掩模版与第二子像素对位并靠设在隔垫柱的表面上，在第二子像素中蒸镀第二颜色发光层，蒸镀完成后使精细金属掩模版离开隔垫柱。然后将精细金属掩模版与第三子像素对位并靠设在隔垫柱的表面上，在第三子像素中蒸镀第三颜色发光层，蒸镀完成后使精细金属掩模版离开隔垫柱。
图11为隔垫柱表面产生尖锐凸起的示意图。如图11所示，由于在蒸镀前的对位过程和蒸镀后的分离过程中，精细金属掩模版与隔垫柱存在多次摩擦，造成隔垫柱表面损伤，从而使隔垫柱25的表面产生一些尖锐的凸起26。实际测量表明，尖锐凸起的高度可以达到0.5μm至1μm。由于这些尖锐的凸起位于隔垫柱的顶部，即位于隔垫柱朝向后续形成的封装层的一侧，因而这些尖锐的凸起容易刺破封装层，使得水氧通过破口渗透到有机发光层，导致封装失效。
图12为本公开示例性实施例隔垫柱表面损伤修复后的示意图。在示例性实施方式中，对隔垫柱的表面进行损伤修复工艺可以采用如下方式。首先，将之前图案化隔垫柱的隔垫柱掩膜版设置在显示基板上，隔垫柱掩膜版的对位方式与图案化隔垫柱的对位方式相同，即隔垫柱掩膜版中透光区域的位置与显示基板中隔垫柱的位置对应。随后，采用紫外光设备进行照射，紫外光透过隔垫柱掩膜版的透光区域照射到隔垫柱。由于聚合物弹性体在紫外光照射下会发生交联网络的扩张与收缩，凸起部分为扩张态，平面部分为收缩态，因而使得隔垫柱表面的凸起由尖锐变为平缓，且高度降低，平缓的凸起的高 度h可以降低到小于0.2μm，实现了隔垫柱的表面损伤修复，如图12所示。
在示例性实施方式中，紫外光的照射强度可以约为5mW/cm 2至20mW/cm 2，紫外光的照射时间可以约为100秒至300秒。
(9)形成阴极图案。在示例性实施方式中，形成阴极图案可以包括：在形成前述图案的基底上，通过蒸镀工艺形成阴极24图案，阴极24与有机发光层23连接，如图13所示。
在示例性实施方式中，多个子像素的阴极24为面状的一体结构，且阴极24包裹隔垫柱25的表面。
在示例性实施方式中，阴极可以采用金属材料，金属材料可以采用镁(Mg)、银(Ag)或铝(Al)，或者采用合金材料，如Mg:Ag的合金，Mg:Ag比例约为9:1至1:9，阴极的厚度可以约为10nm至20nm。
至此，在驱动结构层103上制备完成发光结构层104图案，如图13所示。在示例性实施方式中，发光结构层104中的阳极21、有机发光层23和阴极24构成OLED发光元件，有机发光层23设置在阳极21和阴极24之间，空穴、电子分别由阳极21、阴极24注入至有机发光层23，当电子和空穴在有机发光层23中相遇时，电子和空穴复合从而产生激子(exciton)，在从激发态转变为基态的同时，这些激子发光，有机发光层23出射相应灰度的光线。
(9)形成封装结构层。在示例性实施方式中，在形成封装结构层可以包括：采用开放式掩膜版沉积第一无机薄膜，形成第一封装层31。随后，采用喷墨打印工艺在第一封装层上喷墨打印有机材料，固化成膜后形成第二封装层32。随后，采用开放式掩膜版沉积第二无机薄膜，形成第三封装层33，如图14所示。在示例性实施例中，第一封装层和第三封装层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第二封装层可以采用树脂材料。
至此，在发光结构层104上制备完成封装结构层105图案，如图14所示。封装结构层105可以包括叠设的第一封装层31、第二封装层32和第三封装层33，形成无机材料/有机材料/无机材料的叠层结构，有机材料层设置 在两个无机材料层之间，可以保证外界水汽无法进入发光结构层。在示例性实施例中，第一封装层的厚度可以约为800nm至1200nm，第二封装层的厚度可以约为6000nm至10000nm，第三封装层的厚度可以约为600nm至800nm。
在示例性实施方式中，制备完成封装结构层后，可以在封装结构层上形成触摸结构层(TSP)，触摸结构层可以包括触控电极层，或者包括触控电极层和触控绝缘层。在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程还可以包括剥离玻璃载板1、贴附背膜、切割等工艺，本公开在此不做限定。
通过本公开示例性实施例所示结构及其制备过程可以看出，本公开通过采用包括聚合物弹性体和无机纳米颗粒的隔垫柱，且在蒸镀发光层之后对隔垫柱进行修复处理，有效修复了因精细金属掩模版造成的隔垫柱表面损伤，使得隔垫柱表面的凸起由尖锐变为平缓，且凸起高度大幅度降低，避免了凸起刺破封装层，因而避免了封装失效，有效保证了封装效果，消除了子像素封装失效的问题，提高了良品率。
在示例性实施方式中，有机发光层发出的部分光线会经过隔垫柱入射至封装层后出射。一种显示基板中，隔垫柱通常采用折射率较高的有机材料。根据光学原理，当光线由折射率较大的光密介质入射到折射率较小的光疏介质时，如果入射角大于光密介质与光疏介质界面的全反射角，则会发生全发射。这样，隔垫柱内部的部分光线会在隔垫柱界面发生全反射，使光线限制在隔垫柱内，造成光损耗，降低了光输出效率和发光亮度。本公开通过采用包括无机纳米颗粒的隔垫柱，通过无机纳米颗粒对光线的折射和/或反射，可以改变隔垫柱内光线的传输方向，消除了光线在隔垫柱界面的全反射，有效提高了光输出效率，有效增加了发光亮度。
在示例性实施方式中，外界水氧可能通过隔垫柱渗透到有机发光层。一种显示基板中，隔垫柱通常采用有机材料，水氧渗透率较高，因而阻隔水氧的能力较弱。本公开通过采用包括无机纳米颗粒的隔垫柱，由于无机纳米颗粒阻隔水氧的能力较强，因而有效提高了隔垫柱阻隔水氧的能力，降低了外界水氧通过隔垫柱渗透到有机发光层的几率，有效增加了显示基板的使用寿 命。
本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺。例如，驱动结构层中的晶体管可以是顶栅结构，或者可以是底栅结构，可以是单栅结构，或者可以是双栅结构。又如，驱动结构层和发光结构层中还可以设置其它膜层结构、电极结构或引线结构。再如，基底可以是玻璃基底，本公开在此不做限定。
图15为本公开示例性实施例另一种显示基板的剖面结构示意图，示意了OLED显示基板中一个子像素的结构。在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层103、设置在驱动电路层103远离基底10一侧的发光结构层104以及设置在发光结构层104远离基底10一侧的封装结构层105。在示例性实施方式中，本示例性实施例显示基板中的驱动电路层103和封装结构层105的结构与前述实施例相同，所不同的是，本示例性实施例发光结构层104中的像素定义层22和隔垫柱25采用相同的材料，可以通过同一次图案化工艺同时下形成。如图15所示，发光结构层104可以包括阳极21、像素定义层22、有机发光层23、阴极24和隔垫柱25，像素定义层22设置有暴露出阳极21的像素开口，有机发光层23设置在阳极21和阴极24之间，隔垫柱25设置在像素定义层22上，像素定义层22和隔垫柱25的材料可以包括聚合物弹性体和无机纳米颗粒，即像素定义层22和隔垫柱25的材料相同。
在示例性实施方式中，聚合物弹性体和无机纳米颗粒的材料和参数可以与前述实施例相同，这里不再赘述。
本示例性实施例显示基板的制备过程中，形成基底、形成驱动结构层、形成阳极、形成有机发光层、对隔垫柱进行损伤修复、形成阴极和形成封装结构层的过程可以与前述实施例相同，所不同的是，本示例性实施例形成像素定义层和隔垫柱可以采用一次图案化工艺同时形成。
在示例性实施方式中，采用一次图案化工艺同时形成像素定义层和隔垫柱可以采用如下工艺。先将聚合物弹性体、无机纳米颗粒和感光剂混合后形成溶胶，然后将溶胶均匀涂布在形成前述图案的基底上形成像素定义薄膜。 随后，采用灰色调掩膜版对像素定义薄膜进行曝光，显影后形成完全曝光区域、部分曝光区域和未曝光区域，完全曝光区域的像素定义薄膜被保留，形成隔垫柱图案，部分曝光区域的像素定义薄膜被去除部分厚度，形成像素定义层图案，未曝光区域的像素定义薄膜被完全去除，形成像素开口图案。
在示例性实施方式中，对隔垫柱进行损伤修复时，先将该灰色调掩膜版设置在显示基板上，灰色调掩膜版的透光区域(完全曝光区域)的位置与隔垫柱的位置对应，然后采用紫外光设备进行照射，紫外光透过灰色调掩膜版的透光区域照射到隔垫柱，实现隔垫柱的表面损伤修复。
本公开示例性实施例通过采用包括聚合物弹性体和无机纳米颗粒的隔垫柱，且在蒸镀发光层之后对隔垫柱进行修复处理，有效修复了因精细金属掩模版造成的隔垫柱表面损伤，使得隔垫柱表面的凸起由尖锐变为平缓，且凸起高度大幅度降低，避免了凸起刺破封装层，因而避免了封装失效，有效保证了封装效果，消除了子像素封装失效的问题，提高了良品率。
在示例性实施方式中，有机发光层发出的部分光线会经过像素定义层入射至封装层后出射。一种显示基板中，像素定义层通常采用折射率较高的有机材料。根据光学原理，当光线由折射率较大的光密介质入射到折射率较小的光疏介质时，如果入射角大于光密介质与光疏介质界面的全反射角，则会发生全发射。这样，像素定义层内部的部分光线会在像素定义层界面发生全反射，使光线限制在像素定义层内，造成光损耗，降低了光输出效率和发光亮度。本公开通过采用包括无机纳米颗粒的像素定义层和隔垫柱，通过无机纳米颗粒对光线的折射和/或反射，可以改变像素定义层内光线的传输方向，消除了光线在像素定义层界面的全反射，有效提高了光输出效率，有效增加了发光亮度。
在示例性实施方式中，外界水氧可能通过像素定义层渗透到有机发光层。一种显示基板中，像素定义层通常采用有机材料，水氧渗透率较高，因而阻隔水氧的能力较弱。本公开通过采用包括无机纳米颗粒的像素定义层和隔垫柱，由于无机纳米颗粒阻隔水氧的能力较强，因而有效提高了像素定义层和隔垫柱阻隔水氧的能力，降低了外界水氧通过像素定义层和隔垫柱渗透到有机发光层的几率，有效增加了显示基板的使用寿命。
本公开还提供了一种显示基板的制备方法。在示例性实施方式中，显示基板的制备方法可以包括：
S1、在驱动结构层上形成像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；
S2、采用精细金属掩模版蒸镀有机发光层；
S3、对所述隔垫柱进行修复处理，所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述凸起的高度小于0.2μm。
在示例性实施方式中，所述隔垫柱的材料包括聚合物弹性体和纳米颗粒，所述聚合物弹性体包括聚氨酯、聚硅氧烷和液晶嵌段聚合物中的至少一种，形貌为通过化学连接形成的交联网络，所述交联网络的网孔直径为0.5μm至2.0μm；对所述隔垫柱进行修复处理，可以包括：
对所述隔垫柱进行紫外光照射，所述聚合物弹性体在紫外光照射下发生交联网络的扩张与收缩，使所述隔垫柱表面的凸起由尖锐变为平缓，且所述凸起的高度小于0.2μm。
在示例性实施方式中，所述紫外光的照射强度可以约为5mW/cm 2至20mW/cm 2，所述紫外光的照射时间可以约为100秒至300秒。
在示例性实施方式中，在驱动结构层上形成像素定义层和隔垫柱，可以包括：在所述驱动结构层上形成像素定义层；采用隔垫柱掩膜版，在所述像素定义层上形成隔垫柱；
对所述隔垫柱进行紫外光照射，可以包括：将所述隔垫柱掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述隔垫柱掩膜版的透光区域照射到所述隔垫柱上。
在示例性实施方式中，在驱动结构层上形成像素定义层和隔垫柱，可以包括：采用灰色调掩膜版，通过同一次图案化工艺在所述驱动结构层上形成像素定义层和隔垫柱；
对所述隔垫柱进行紫外光照射，包括：将所述灰色调掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述灰色调掩膜版的透光区 域照射到所述隔垫柱上。
本公开显示基板的制备方法通过采用包括聚合物弹性体和无机纳米颗粒的隔垫柱，且在蒸镀发光层之后对隔垫柱进行修复处理，有效保证了封装效果，有效提高了光输出效率，有效增加了显示基板的使用寿命。本公开制备方法对工艺改进较小，兼容性高，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开还提供了一种显示装置，包括前述的显示基板。显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、车载显示器、智能手表、智能手环等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种显示基板，包括设置在驱动结构层上的像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述的凸起高度小于0.2μm。
  2. 根据权利要求1所述的显示基板，其中，所述隔垫柱的材料包括聚合物弹性体和纳米颗粒，所述隔垫柱中纳米颗粒占比为0.5wt％至5wt％。
  3. 根据权利要求2所述的显示基板，其中，所述纳米颗粒的直径为20nm至100nm。
  4. 根据权利要求2所述的显示基板，其中，所述纳米颗粒包括甲基修饰无机纳米颗粒。
  5. 根据权利要求4所述的显示基板，其中，所述甲基修饰无机纳米颗粒包括甲基修饰无机氧化硅纳米颗粒、甲基修饰无机氧化锌纳米颗粒和甲基修饰无机氧化锆纳米颗粒中的至少一种。
  6. 根据权利要求2至5任一项所述的显示基板，其中，所述聚合物弹性体包括聚氨酯、聚硅氧烷和液晶嵌段聚合物中的至少一种，所述聚合物弹性体的形貌为通过化学连接形成的交联网络，所述交联网络的网孔直径为0.5μm至2.0μm。
  7. 根据权利要求1至5任一项所述的显示基板，其中，所述隔垫柱的高度为1μm至1.5μm。
  8. 根据权利要求1至5任一项所述的显示基板，其中，所述像素定义层和隔垫柱的材料相同。
  9. 根据权利要求1至5任一项所述的显示基板，其中，所述隔垫柱和像素定义层为一体结构。
  10. 一种显示装置，包括权利要求1至9任一项所述的显示基板。
  11. 一种显示基板的制备方法，包括：
    在驱动结构层上形成像素定义层和隔垫柱，所述隔垫柱设置在所述像素定义层远离所述驱动结构层一侧的表面，且所述隔垫柱在基底上的正投影位于所述像素定义层在基底上的正投影的范围之内；
    采用精细金属掩模版蒸镀有机发光层；
    对所述隔垫柱进行修复处理，所述隔垫柱远离所述驱动结构层一侧的表面具有凸起，所述凸起的高度小于0.2μm。
  12. 根据权利要求11所述的制备方法，其中，所述隔垫柱的材料包括聚合物弹性体和纳米颗粒，所述聚合物弹性体包括聚氨酯、聚硅氧烷和液晶嵌段聚合物中的至少一种，形貌为通过化学连接形成的交联网络，所述交联网络的网孔直径为0.5μm至2.0μm；对所述隔垫柱进行修复处理，包括：
    对所述隔垫柱进行紫外光照射，所述聚合物弹性体在紫外光照射下发生交联网络的扩张与收缩，使所述隔垫柱表面的凸起由尖锐变为平缓，且所述凸起的高度小于0.2μm。
  13. 根据权利要求12所述的制备方法，其中，所述紫外光的照射强度为5mW/cm 2至20mW/cm 2，所述紫外光的照射时间为100秒至300秒。
  14. 根据权利要求12所述的制备方法，其中，
    在驱动结构层上形成像素定义层和隔垫柱，包括：在所述驱动结构层上形成像素定义层；采用隔垫柱掩膜版，在所述像素定义层上形成隔垫柱；
    对所述隔垫柱进行紫外光照射，包括：将所述隔垫柱掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述隔垫柱掩膜版的透光区域照射到所述隔垫柱上。
  15. 根据权利要求12所述的制备方法，其中，
    在驱动结构层上形成像素定义层和隔垫柱，包括：采用灰色调掩膜版，通过同一次图案化工艺在在所述驱动结构层上形成像素定义层和隔垫柱；
    对所述隔垫柱进行紫外光照射，包括：将所述灰色调掩膜版设置在显示基板上，采用紫外光设备进行照射，紫外光透过所述灰色调掩膜版的透光区域照射到所述隔垫柱上。
PCT/CN2021/081888 2021-03-19 2021-03-19 显示基板及其制备方法、显示装置 WO2022193316A1 (zh)

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