WO2022262329A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022262329A1
WO2022262329A1 PCT/CN2022/080153 CN2022080153W WO2022262329A1 WO 2022262329 A1 WO2022262329 A1 WO 2022262329A1 CN 2022080153 W CN2022080153 W CN 2022080153W WO 2022262329 A1 WO2022262329 A1 WO 2022262329A1
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WIPO (PCT)
Prior art keywords
layer
area
edge
partition
hole
Prior art date
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PCT/CN2022/080153
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English (en)
French (fr)
Inventor
张子予
曹方旭
Original Assignee
京东方科技集团股份有限公司
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Priority to US18/032,555 priority Critical patent/US20230389375A1/en
Publication of WO2022262329A1 publication Critical patent/WO2022262329A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present disclosure relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • Flexible Display which use OLED as a light-emitting device and are signal-controlled by Thin Film Transistor (TFT for short), have become mainstream products in the display field.
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, including a display area and a frame area located on at least one side of the display area, the display area and the frame area include at least one stretch hole;
  • the stretch hole includes a hole area and a partition area surrounding the stretching hole, the partition area is provided with a first partition structure surrounding the hole area;
  • the first partition structure includes a first partition layer surrounding the hole area and is arranged on the The first cover layer on the first partition layer, the first partition layer is provided with partition grooves surrounding the hole area, the first cover layer is provided with partition holes surrounding the hole area, and the partition
  • the hole communicates with the partition groove;
  • the first covering layer located around the partition hole has a protrusion relative to the side wall of the partition groove, and the protrusion and the side wall of the partition groove form a sunken structure.
  • the frame area includes a circuit area, a power line area and an edge area arranged in sequence along a direction away from the display area, and the power line area includes at least one stretching hole;
  • the power line area includes at least one insulating layer on the base and a power line on the at least one insulating layer; the first isolation layer in the first isolation structure covers the The power line is close to the edge of the hole area on the side of the hole area.
  • the first covering layer is not in direct contact with the power line.
  • the first covering layer on the side away from the hole area in the first partition structure is laid on the power line.
  • the orthographic projection of the power line on the plane of the display substrate and the orthographic projection of the first covering layer on the plane of the display substrate overlap at most.
  • the first edge and/or the second edge of the power line is a folded line, and the first edge is a distance between the power line and the display area.
  • side edge, the second edge is the edge of the side of the power line close to the display area.
  • the orthographic projection of the first edge and/or the second edge on the plane of the display substrate does not overlap with the orthographic projection of the stretching hole on the plane of the display substrate.
  • a second partition structure is provided on a side of the first edge away from the display area, and the second partition structure includes a second partition layer extending along the first edge and a The second covering layer on the second partition layer, the second partition layer is provided with partition grooves extending along the first edge, and the second covering layer is provided with partition grooves extending along the first edge.
  • An extended partition hole, the partition hole communicates with the partition groove; the second covering layer located around the partition hole has a protrusion relative to the side wall of the partition groove, and the protrusion and the side wall of the partition groove Form an indentation structure.
  • the second isolation layer in the second isolation structure covers the first edge of the power line.
  • the second covering layer is not in direct contact with the power line.
  • the second covering layer on the side of the second partition structure close to the display area is set on the power line.
  • the power line area further includes a connection electrode and a first isolation dam surrounding the hole area, the connection electrode is disposed on the power line, and the first isolation dam is disposed on the A side of the first partition structure away from the hole area, and a side of the first blocking dam away from the hole area covers an edge of the connection electrode on a side close to the hole area.
  • the power line area further includes a connection electrode and a second isolation dam extending along the first edge, and the second isolation dam is arranged at the second isolation structure close to the display area
  • the side of the second barrier dam close to the display area covers the edge of the connecting electrode on the side close to the first edge.
  • it further includes a third covering layer disposed above the first covering layer and/or the second covering layer, the third covering layer covers at least the first covering layer and/or the second covering layer , and the partition groove.
  • an edge of the first cover layer remote from the aperture area is substantially flush with an edge of the third cover layer remote from the aperture area; and/or the second cover layer is remote from the aperture area
  • the edge of and the edge of the third covering layer away from the hole area are substantially flush.
  • the power line area further includes a connection electrode, the connection electrode is arranged on the power line, and the side of the connection electrode close to the hole area covers the side where the power line is laid.
  • the edge of the first covering layer, the side of the connecting electrode close to the first edge covers the edge of the first covering layer on which the power line is laid.
  • the power line area further includes a first isolation dam surrounding the hole area, the first isolation dam is arranged on a side of the first isolation structure away from the hole area, the The side of the first partition dam close to the hole area is arranged on the first covering layer, and the side of the first partition dam away from the hole area covers the edge of the connecting electrode on the side close to the hole area .
  • the orthographic projection of the edge of the connection electrode close to the hole area on the display substrate plane is within the range of the orthographic projection of the first barrier dam on the display substrate plane and/or, the orthographic projection of the edge of the first covering layer away from the hole area on the display substrate plane is within the range of the orthographic projection of the first partition dam on the display substrate plane within.
  • the power line area further includes a second isolation dam extending along the first edge, and the second isolation dam is arranged on a side of the second isolation structure close to the display area
  • the side of the second barrier dam away from the display area is disposed on the second cover layer, and the side of the second barrier dam close to the display area covers the side of the connection electrode close to the first edge the edge of.
  • the orthographic projection of the edge of the connection electrode away from the display area on the display substrate plane is within the range of the orthographic projection of the second barrier dam on the display substrate plane, And/or, the orthographic projection of the edge of the second cover layer close to the display area on the plane of the display substrate is within the range of the orthographic projection of the second barrier dam on the plane of the display substrate.
  • the orthographic projection of the connecting electrode on the plane of the display substrate and the orthographic projection of the first covering layer on the plane of the display substrate have at least a first partial overlap;
  • the orthographic projection on the display substrate plane and the orthographic projection of the second covering layer on the display substrate plane have at least a second partial overlap.
  • the first part is overlapped within the range of the orthographic projection of the first partition dam on the display substrate plane, and the second part is overlapped by the second partition dam on the display substrate. within the range of the orthographic projection on the plane.
  • the power line area further includes a cathode, which is disposed on the connection electrode and wraps around the first isolation dam and the second isolation dam.
  • the display area includes a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on the driving circuit layer; the first isolation layer and the second isolation layer are connected with the driving circuit layer
  • the flat layer is set on the same layer, and the first barrier dam and the second barrier dam are set on the same layer as the pixel definition layer in the light emitting structure layer.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • FIG. 1 is a schematic structural view of a display substrate
  • FIG. 2 is a schematic structural view of a display substrate
  • Fig. 3 is a schematic plan view of a display area
  • FIG. 4 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit
  • FIG. 5 is a working timing diagram of a pixel driving circuit
  • FIG. 6 is a schematic plan view showing a frame region in a substrate
  • FIG. 7a and 7b are schematic cross-sectional structure diagrams of a display substrate according to an exemplary embodiment of the present disclosure
  • FIGS. 8a to 8c are schematic diagrams of an embodiment of the present disclosure after forming patterns such as a driving structure layer;
  • FIGS. 9a to 9c are schematic diagrams of an embodiment of the present disclosure after forming a partition layer pattern
  • 10a to 10f are schematic diagrams of an embodiment of the present disclosure after forming a partition groove pattern
  • FIG. 11a to 11c are schematic diagrams of an embodiment of the present disclosure after forming a connecting electrode pattern
  • 12a to 12c are schematic diagrams of an embodiment of the present disclosure after forming a partition dam pattern
  • FIG. 13a to 13c are schematic diagrams of an organic light-emitting layer pattern formed in an embodiment of the present disclosure.
  • 14a to 14c are schematic diagrams of forming a cathode pattern according to an embodiment of the present disclosure.
  • 15a to 15c are schematic diagrams of forming an optical coupling layer pattern according to an embodiment of the present disclosure.
  • 16a to 16c are schematic diagrams of an encapsulation layer pattern formed according to an embodiment of the present disclosure.
  • 17a and 17b are schematic cross-sectional structure diagrams of another display substrate according to an embodiment of the present disclosure.
  • 18a to 18b are another schematic diagram of the present disclosure after forming a partition groove pattern
  • 19a to 19b are another schematic diagrams of the present disclosure after forming a third inorganic layer pattern
  • 20a to 20b are another schematic diagrams of the present disclosure after forming a connecting electrode pattern
  • 21a to 21b are another schematic diagrams of the present disclosure after forming partition dam patterns.
  • 21 the second active layer
  • 22 the second gate electrode
  • 23 the second source electrode
  • 73 pixel definition layer
  • 74 first partition dam
  • 75 second partition dam
  • 76 organic light-emitting layer
  • 77 cathode
  • 78 optical coupling layer
  • 81 the first encapsulation layer
  • 82 the second encapsulation layer
  • 83 the third encapsulation layer
  • 101 the first transistor
  • 102 the first storage capacitor
  • 200 the binding area
  • 201 the second transistor
  • 202 the second storage capacitor
  • 300 the frame area
  • 301 circuit area
  • 302 power line area
  • 303 edge area
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver.
  • a clock signal suitable for the specification of the light emission signal driver, an emission stop signal, etc. may be supplied to the light emission signal driver.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • the lighting signal driver may generate emission signals to be supplied to the lighting signal lines E1, E2, E3, . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission signal driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signal in a manner of sequentially transmitting the light emitting stop signal provided in the form of off-level pulses to the next-stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scanning signal line, and a corresponding light emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 on one side of the display area 100 , and a frame area 300 on the other side of the display area 100 .
  • the display area 100 may include a plurality of sub-pixels arranged regularly, the sub-pixels may include a pixel drive circuit and a light emitting device, the bonding area 200 may include a bonding circuit for connecting signal lines to an external driving device, and the frame area 300 may include a gate driver circuit. circuit and a second power supply line VSS for transmitting voltage signals to a plurality of sub-pixels.
  • the flexible display substrate can adopt an island bridge structure.
  • the island bridge structure is to arrange the light-emitting device in the pixel island area, the hole area including microholes is set between the pixel islands, and the connection line is set between the pixel islands and the connection between the hole areas. bridge area.
  • the deformation mainly occurs in the hole area and the connecting bridge area, and the light-emitting devices in the pixel island area basically maintain their shape, which can ensure that the light-emitting devices in the pixel island area will not be damaged.
  • FIG. 3 is a schematic plan view of a display area.
  • the display area of the display substrate may include a plurality of pixel islands arranged in a matrix, and the pixel island may include at least one pixel unit P, and the pixel unit P may include a first sub-pixel P1 that emits light of a first color. , a second sub-pixel P2 that emits light of the second color, and a third sub-pixel P3 that emits light of the third color, and the sub-pixels may include a pixel driving circuit and a light emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light emitting signal line Under the control of the line, it receives the data voltage transmitted by the data signal line, and outputs a corresponding current to the light emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting devices are configured to respond to the current output by the pixel driving circuit of the sub-pixel and emit corresponding Brightness of light.
  • the first subpixel P1 may be a red (R) subpixel
  • the second subpixel P2 may be a green (G) subpixel
  • the third subpixel P3 may be a blue (B) subpixel
  • the pixel unit P may include four sub-pixels, such as a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • a shape of a sub-pixel in a pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three light-emitting units can be arranged horizontally, vertically or squarely; when the pixel unit includes four sub-pixels, the four light-emitting units can be arranged horizontally, vertically or squarely (Square ) arrangement, the disclosure is not limited here.
  • the display area may include a plurality of stretch holes 500 disposed between pixel islands, the stretch holes 500 configured to increase a deformable amount of the display substrate.
  • the base and structural film layer in the stretching hole 500 are completely removed to form a through-hole structure, or the base and structural film layer in the stretching hole 500 are partially removed to form a blind hole structure .
  • the shape of the stretching hole may include any one or more of the following: "I" shape, "T” shape, "L” shape and "H” shape, which are not discussed in this disclosure. limited.
  • a plurality of stretching holes may be provided in the frame area, and the arrangement of the stretching holes in the frame area may be similar to the arrangement of the stretching holes in the display area.
  • the pixel driving circuit may have a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T2C.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7), 1 storage capacitor C and 7 signal lines (the first scanning signal line S1, the second scanning signal line S2 , light emitting signal line E, data signal line D, initial signal line INIT, first power line VDD and second power line VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, and the initial signal line INIT extend in the horizontal direction
  • the second power line VSS, the first power line VDD, and the data signal line D extends in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4.
  • the pixel driving circuit in FIG. signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), 7 transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • the display substrate in a plane perpendicular to the display substrate, may include a driving structure layer disposed on the substrate, a light emitting structure layer disposed on the driving structure layer, and an encapsulation layer disposed on the light emitting element, the driving The structural layer includes a pixel driving circuit, the light emitting structural layer includes a light emitting device, and the light emitting device is connected with the pixel driving circuit.
  • FIG. 6 is a schematic plan view showing a frame area in a substrate, which is an enlarged view of area E in FIG. 2 .
  • the frame area 300 may include a circuit area 301 , a power line area 302 and an edge area 303 arranged in sequence along a direction away from the display area.
  • the circuit area 301 may include a gate driver on array (GOA for short), and the gate driver circuit is connected to the first scan line and the second scan line of a plurality of sub-pixels in the display area.
  • the power line area 302 may include a power line 310 connected to the second power line VSS of a plurality of sub-pixels in the display area.
  • the edge area 303 may include crack dams and cutting grooves, the crack dams include a plurality of cracks arranged on the composite insulating layer, and the plurality of cracks are configured to reduce the stress on the display area and the circuit area during the cutting process, so as to avoid affecting the display area and the circuit area.
  • the film layer structure of the circuit area cuts off the transmission of cracks to the display area and the circuit area.
  • the cutting groove includes a groove provided on the composite insulating layer, and the cutting groove is configured such that after all the film layers of the display substrate are prepared, the cutting equipment respectively cuts along the cutting groove.
  • the circuit area 301 and the power line area 302 may not overlap, or may partially overlap, which is not limited in the present disclosure.
  • the low voltage required by the pixel driving circuit in multiple sub-pixels in the display area is introduced from the bonding pad of the bonding area, enters the frame area after passing through the bonding area, and is delivered to the The second power supply line VSS of each pixel driving circuit. Since there is a certain impedance in the power line, there is a voltage drop in the voltage signal transmission, so the width of the power line is larger to improve the uniformity of display brightness.
  • a plurality of drawing holes 500 may be provided in the circuit area 301 , the power line area 302 and the edge area 303 .
  • the plurality of stretching holes 500 in each zone may include stretching holes in a first direction and stretching holes in a second direction.
  • the stretching holes in the first direction are strip-shaped holes extending along the first direction X
  • the stretching holes in the second direction are The hole is a bar-shaped hole extending along the second direction Y, and the first direction X crosses the second direction Y.
  • the stretching holes in the first direction and the stretching holes in the second direction are arranged alternately, and the stretching holes in the first direction are arranged between the two stretching holes in the second direction, or, The stretching holes in the second direction are arranged between the two stretching holes in the first direction.
  • the stretching holes in the first direction and the stretching holes in the second direction are arranged alternately, the stretching holes in the first direction are arranged between two stretching holes in the second direction, or the stretching holes in the second direction are arranged Between two first direction extruded holes.
  • the power line 310 of the power line area 302 has a folded line first edge 311 and/or a folded line second edge 312, and the first edge 311 is the edge of the power line 310 on the side away from the display area.
  • the second edge 312 is the edge of the side of the power line 310 close to the display area.
  • the orthographic projection of the first edge 311 and/or the second edge 312 on the plane of the display substrate does not overlap with the orthographic projection of the stretching hole 500 on the plane of the display substrate.
  • the first edge may include a plurality of first straight lines and a plurality of first fold lines, and the first straight lines and first fold lines are alternately arranged and connected to each other to form a fold-line-shaped first edge.
  • the second edge may include a plurality of second straight lines and a plurality of second fold lines, the second straight lines and the second fold lines are arranged alternately and connected with each other to form a fold line-shaped second edge.
  • the first straight line and the second straight line may be parallel to the second direction Y, and the first fold line is a fold line protruding toward a direction away from the display area or toward a direction close to the display area relative to the first straight line.
  • the second fold line is a fold line protruding toward a direction away from the display area or a fold line concave toward a direction close to the display area relative to the second straight line.
  • the first fold line or the second fold line may include a first line segment, a second line segment and a third line segment connected in sequence, and the first line segment may be deflected by a first angle, the third line segment may be deflected by a second angle relative to the first straight line or the second straight line.
  • the second line segment may be parallel to the second direction Y
  • the first line segment and the third line segment may be arranged symmetrically with respect to the center line of the second line segment
  • the center line of the second line segment is along the first direction The line that extends X and bisects the second line segment.
  • the stretching holes in the first direction and the stretching holes in the second direction may be respectively arranged on both sides of the first straight line, and the stretching holes in the first direction and the stretching holes in the second direction may be respectively arranged on the second side of the first straight line. Both sides of the second line segment.
  • one stretching hole in the first direction is set on the side of the first straight line away from the display area, and the other stretching hole in the second direction
  • the stretching hole is arranged on the side of the first straight line close to the display area.
  • One stretching hole in the second direction is set on the side of the second line segment away from the display area, and the other stretching hole in the first direction is set on the side of the second line segment close to the display area.
  • the orthographic projection and stretching of the first edge 311 and/or the second edge 312 on the display substrate plane do not overlap, and the edge of the power line avoids the stretching hole, which not only prevents the edge of the power line from affecting the stress distribution of the stretching hole, but also effectively avoids the stretching caused by the stretching hole.
  • the edge peeling of the power line caused by the deformation prevents package failure caused by the formation of water and oxygen channels due to the peeling of the edge of the power line.
  • Figure 7a and Figure 7b are schematic cross-sectional structure diagrams of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 7a illustrates the cross-sectional structure at the junction of the circuit area 301 and the power line area 302, which is a cross-sectional view along the B-B direction in Figure 6, and
  • Figure 7b The cross-sectional structure of the junction of the power line area 302 and the edge area 303 is shown, which is a cross-sectional view along the line C-C in FIG. 6 .
  • the stretching hole may include a hole region 50 and a partition region 51 surrounding the hole region 50 , the partition region 51 being provided with a first partition structure surrounding the hole region 50 .
  • the first isolation structure includes a first isolation layer 60 surrounding the hole area 50 and a first inorganic layer 96 disposed on the first isolation layer 60, and the first isolation layer 60 is provided with a surrounding hole In the partition groove 61 of the region 50, a partition hole surrounding the hole region 50 is provided on the first inorganic layer 96, and the partition hole communicates with the partition groove.
  • the first inorganic layer 96 located around the partition hole has a protrusion relative to the side wall of the partition groove 61 , and the protrusion and the side wall of the partition groove form an indented structure.
  • the first inorganic layer serves as the first covering layer of the present disclosure.
  • the first covering layer may be made of a metal material, or other materials having a different etching rate from that of the first isolation layer (organic material), which is not limited in this disclosure.
  • the power line region 302 may include a composite insulating layer disposed on the substrate 10 and a power line 310 disposed on the composite insulating layer.
  • the composite insulating layer may include a stacked first insulating layer 91 , a second insulating layer 91 , a third insulating layer 93 and a fourth insulating layer 94 .
  • the first isolation layer 60 in the first isolation structure covers the hole area edge 313 on the side of the power line 310 close to the hole area 50 , and the first inorganic layer on the side away from the hole area 50 in the first isolation structure 96 is built on the power line 310 .
  • the power line area 302 may include a connection electrode 72, which is disposed on a side of the power line 310 away from the substrate, and connected to the power line 310 by overlapping.
  • the side of the connection electrode 72 close to the hole area 50 covers the edge of the first inorganic layer 96, which is the first inorganic layer 96 built on the power line 310 in the first isolation structure, and the edge is the first inorganic layer 96.
  • the power line area 302 may include a first isolation dam 74 .
  • the first isolation dam 74 is an annular body surrounding the hole area 50 , and is disposed on a side of the first isolation structure away from the hole area 50 .
  • the first isolation dam 74 is disposed on the first inorganic layer 96 on the side close to the hole area 50.
  • the first inorganic layer 96 is the first inorganic layer 96 built on the power line 310 in the first isolation structure.
  • the first isolation dam The side 74 away from the hole area 50 covers the edge of the connecting electrode 72 on the side close to the hole area 50 .
  • the power line area 302 may include a cathode 77, the cathode 77 is disposed on the side of the connection electrode 72 away from the base, connected to the connection electrode 72 by overlapping, and the cathode 77 wraps the first barrier dam 74, that is The cathode 77 covers the entire exposed surface of the first dam 74 .
  • a second isolation structure may be provided on the side of the first edge 311 of the power line 310 away from the display area, and the second isolation structure includes a second isolation layer 70 extending along the first edge 311 and a The second inorganic layer 97 on the second isolation layer 70, the second isolation layer 70 is provided with an isolation groove 61 extending along the first edge 311, and the second inorganic layer 97 is provided with an isolation hole extending along the first edge 311 , the partition hole communicates with the partition slot.
  • the second inorganic layer 97 located around the partition hole has a protrusion relative to the side wall of the partition groove 61 , and the protrusion and the side wall of the partition groove form an indented structure.
  • the second inorganic layer 97 serves as the second covering layer of the present disclosure.
  • the second covering layer may be made of a metal material, or other materials having a different etching rate from that of the second isolation layer (organic material), which is not limited in this disclosure.
  • the second isolation layer 70 in the second isolation structure covers the first edge 311 of the power line 310 , and the second inorganic layer 97 on the side near the display area in the second isolation structure is built on the power line 310 .
  • the side of the connecting electrode 72 close to the first edge 311 covers the edge of the second inorganic layer 97, which is the second inorganic layer built on the power line 310 in the second isolation structure. 97, the edge is the edge of the side of the second inorganic layer 97 close to the display area.
  • the power line area 302 may include a second isolation dam 75, which is a linear body extending along the first edge 311, and is arranged on a side of the second isolation structure close to the display area.
  • the second isolation dam 75 is disposed on the second inorganic layer 97 on the side away from the display area, and the second inorganic layer 97 is the second inorganic layer 97 built on the power line 310 in the second isolation structure, and the second isolation dam
  • the side 75 close to the display area covers the edge of the connecting electrode 72 close to the first edge 311 .
  • the cathode 77 wraps around the second dam 75 , that is, the cathode 77 covers the entire exposed surface of the second dam 75 .
  • the inner wall of the hole region 50 includes a base segment, an organic material segment, and an inorganic material segment in a plane perpendicular to the display substrate.
  • the display region may include a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on the driving circuit layer.
  • the first isolation layer 60 and the second isolation layer 70 can be arranged in the same layer as the flat layer in the driving circuit layer, and the first isolation dam 74 and the second isolation dam 75 can be arranged in the same layer as the pixel definition layer in the light emitting structure layer.
  • the first inorganic layer and the second inorganic layer are provided in the same layer, and are provided in the same layer as one insulating layer in the display region.
  • a third inorganic layer is further disposed on the first inorganic layer and/or the second inorganic layer, and the third inorganic layer covers the first partition structure and/or the second partition structure.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of B's orthographic projection.
  • a manufacturing process of a display substrate according to an exemplary embodiment of the present disclosure may include the following operations.
  • the substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the material of the first flexible material layer and the second flexible material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the first inorganic material
  • the material of layer and the second inorganic material layer can adopt silicon nitride (SiNx) or silicon oxide (SiOx) etc., be used to improve the anti-water and oxygen ability of substrate, the first inorganic material layer and the second inorganic material layer can be called barrier (Barrier) layer or buffer (Buffer) layer.
  • its preparation process may include: first coating a layer of polyimide on the glass carrier 1, and forming a first layer of polyimide after curing to form a film.
  • Flexible (PI1) layer then deposit a layer of barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then coat a layer of polyimide on the first barrier layer , forming a second flexible (PI2) layer after curing into a film; then depositing a layer of barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and completing the preparation of the substrate.
  • an amorphous silicon (a-si) layer may be disposed between the first barrier layer and the second inorganic material layer, and the substrate may include a first flexible material layer stacked on a glass carrier, a first Inorganic material layer, semiconductor layer, second flexible material layer and second inorganic material layer.
  • inorganic holes may be formed on the first barrier layer through a patterning process, and positions of the inorganic holes may correspond to positions of through holes formed subsequently. After this process, the display area, the circuit area 301 , the power line area 302 and the edge area 303 all include the substrate.
  • the driving structure layer of the display region may include the first transistor 101 and the first storage capacitor 102 constituting the pixel driving circuit
  • the circuit structure layer of the circuit region 301 may include the second transistor 201 constituting the gate driving circuit.
  • the power structure layer of the power line area 302 may include a composite insulating layer disposed on the substrate and the power line 310 disposed on the composite insulating layer
  • the edge structure layer of the edge area 303 may include a composite insulating layer.
  • the composite insulating layer may include a plurality of stacked inorganic insulating layers.
  • the process of preparing the pattern of the driving structure layer in the display area, the circuit structure layer in the circuit area, the power supply structure layer in the power line area, and the edge structure layer in the edge area may include:
  • the semiconductor layer pattern at least includes the first active layer 11 located in the display area and the second active layer 21 located in the circuit area 301 .
  • the semiconductor film in the power line area 302 and the edge area 303 is etched away, and the power line area 302 and the edge area 303 include the substrate 10 disposed on the glass carrier 1 and the first substrate 10 disposed on the substrate 10. insulating layer 91 .
  • the second insulating film and the first metal film are deposited in sequence, and the first metal film is patterned by a patterning process to form a second insulating layer 92 covering the pattern of the semiconductor layer, and a first insulating layer disposed on the second insulating layer 92
  • a metal layer pattern, the first metal layer pattern at least includes the first gate electrode 12 and the first capacitor electrode 31 located in the display area, and the second gate electrode 22 and the second capacitor electrode 41 located in the circuit area 301 .
  • the first metal thin film in the power line area 302 and the edge area 303 is etched away, the power line area 302 and the edge area 303 include the substrate 10, and the first insulating layer 91 and the first insulating layer 91 stacked on the substrate 10 Two insulating layers 92 .
  • a third insulating film and a second metal film are deposited in sequence, and the second metal film is patterned by a patterning process to form a third insulating layer 93 covering the pattern of the first metal layer, and be disposed on the third insulating layer 93
  • the second metal layer pattern, the second metal layer pattern at least includes the third capacitor electrode 32 located in the display area and the fourth capacitor electrode 42 located in the circuit area 301, the position of the third capacitor electrode 32 and the position of the first capacitor electrode 31
  • the position of the fourth capacitor electrode 42 corresponds to the position of the second capacitor electrode 41 .
  • the second metal thin film in the power line area 302 and the edge area 303 is etched away.
  • the power line area 302 and the edge area 303 include the substrate 10, and the first insulating layer 91 and the first insulating layer 91 stacked on the substrate 10.
  • the second insulating layer 92 and the third insulating layer 93 are examples of the second metal film.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 94 covering the pattern of the second metal layer.
  • a plurality of via holes and a plurality of vias are opened on the fourth insulating layer 94. through hole.
  • the plurality of via holes may include a first active via hole located in the display area and a second active via hole located in the circuit area 301, the fourth insulating layer 94 inside the first active via hole and the second active via hole, The third insulating layer 93 and the second insulating layer 92 are etched away, the first active via hole exposes the source region and the drain region at both ends of the first active layer 11, and the second active via hole exposes the second The source region and the drain region at both ends of the active layer 21 .
  • a plurality of through holes are respectively located in the display area, the circuit area 301, the power line area 302 and the edge area 303, and the fourth insulating layer 94, the third insulating layer 93, and the second insulating layer 92 in the plurality of through holes (hole area 50) , the first insulating layer 91 and the substrate 10 are removed, exposing the surface of the glass substrate 1 .
  • the power line region 302 and the edge region 303 include the substrate 10 and the composite insulating layer disposed on the substrate 10, the through holes penetrate the substrate 10 and the composite insulating layer, and the composite insulating layer includes the stacked first insulating layer 91 , the second insulating layer 92 , the third insulating layer 93 and the fourth insulating layer 94 .
  • the third metal layer pattern at least includes: the first source located in the display area The electrode 13 and the first drain electrode 14, the second source electrode 23 and the second drain electrode 24 located in the circuit area 301, and the power line 310 located in the power line area 302, as shown in Figure 8a, Figure 8b and Figure 8c, the figure 8a shows the cross-sectional structure of pixel islands and stretch holes in the display area, which is a cross-sectional view of A-A in FIG. 3 , FIG. 8b is a cross-sectional view of B-B in FIG. 6 , and FIG. 8c is a cross-sectional view of C-C in FIG. 6 .
  • the first active layer 11, the first gate electrode 12, the first source electrode 13 and the first drain electrode 14 constitute the first transistor 101 of the pixel driving circuit
  • the second active layer 21, the second The gate electrode 22, the second source electrode 23 and the second drain electrode 24 form the second transistor 201 of the gate drive circuit
  • the first capacitor electrode 31 and the third capacitor electrode 32 form the first storage capacitor 102 of the pixel drive circuit
  • the second The capacitor electrode 41 and the fourth capacitor electrode 42 form the second storage capacitor 202 of the gate driving circuit.
  • the first transistor 101 may be a driving transistor in a pixel driving circuit
  • the second transistor 201 may be a switching transistor in a gate driving circuit.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may use silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Any one or more, can be single layer, multilayer or composite layer.
  • the first insulating layer may be called a buffer layer
  • the second and third insulating layers may be called (GI) layers
  • the fourth insulating layer may be called an interlayer insulating (ILD) layer.
  • the first metal film, the second metal film and the third metal film can adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) any one or More, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) any one or More, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , Hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • Hexathiophene polythiophene and other materials
  • the stretch aperture may include an aperture region (ie, through hole) 50 and a barrier region 51 surrounding the aperture region 50 .
  • the hole area 50 exposes the surface of the glass substrate 1
  • the isolation area 51 exposes the surface of the fourth insulating layer 94 .
  • the hole area 50 exposes the surface of the glass substrate 1, the area of the isolation area 51 close to the hole area 50 exposes the surface of the fourth insulating layer 94, and the area of the isolation area 51 away from the hole area 50 exposes the power line. 310 surface.
  • the etching of the via hole includes etching the inorganic material layer and the organic material layer, and the etching rate of the organic material is higher than the etching rate of the inorganic material, so that the sidewall of the via hole A step is formed, and the diameter of the substrate through hole on the substrate expands a certain distance relative to the insulation through hole on the composite insulating layer.
  • the composite insulating layer around the insulating through hole on the side close to the through-base hole has a protrusion relative to the side wall of the through-base hole on the side close to the insulating through hole, and the protrusion and the side wall of the through-hole on the base form an indented structure, that is, a
  • the composite insulation in the inner walls of the zone has an "eave" structure that protrudes from the base.
  • the aperture of the substrate through hole is larger than the aperture of the insulation via hole, and the orthographic projection of the outline of the insulation via hole (on the side near the substrate through hole) on the glass substrate is located at (near the side of the insulation via hole) )
  • the outline of the through-substrate hole is within the range of the orthographic projection on the glass substrate.
  • forming the pattern of the flat layer and the isolation layer may include: coating a flat film on the substrate forming the aforementioned pattern, and patterning the flat film through a patterning process to form the flat layer 95 and the first isolation layer 60 And the pattern of the second partition layer 70, as shown in Figure 9a, Figure 9b and Figure 9c, Figure 9a is a sectional view of A-A in Figure 3, Figure 9b is a sectional view of B-B in Figure 6, Figure 9c is a sectional view of C-C in Figure 6 cutaway view.
  • the flat film may use an organic material such as resin or the like.
  • a planarization layer 95 is formed in the display area and the circuit area 301 .
  • An anode via hole is opened on the flat layer 95 of the display area, and the flat film in the anode via hole is removed to expose the surface of the first drain electrode of the first transistor 101, and the anode via hole is configured so that the subsequently formed anode passes through the via hole The hole is connected with the first transistor 101 .
  • the driving structure layer in the display region includes a planarization layer 95 .
  • the flat layer 95 of the circuit area 301 extends to the power line area 302 in a direction away from the display area, and covers the second edge 312 of the power line 310 near the display area.
  • the first isolation layer 60 is formed around each hole area 50 in the display area, the circuit area 301 , the power line area 302 and the edge area 303 in a ring shape surrounding the hole area 50 .
  • the second isolation layer 70 is formed on the side of the first edge 311 of the power line 310 away from the display area, and is in the shape of a folded line extending along the first edge 311 .
  • the flat film on the side of the ring-shaped first isolation layer 60 close to the hole area 50 is removed to form a first opening K1, which exposes the hole area 50 and
  • a first opening K1 which exposes the hole area 50
  • the flat film on the side of the first isolation layer 60 away from the hole area 50 is removed, and a ring-shaped second opening K2 is formed between the first isolation layer 60 and the flat layer 95 , the second opening K2 exposes the surface of the fourth insulating layer 94 .
  • the flat film on the side of the ring-shaped first isolation layer 60 close to the hole area 50 is removed to form the first opening K1, and the side of the first isolation layer 60 away from the hole area 50 is removed.
  • the flat film is removed to form a third opening K3 , which exposes the surface of the power line 310 , and the third opening K3 is configured to connect the subsequently formed connection electrode to the power line 310 through the opening.
  • the side of the first isolation layer 60 away from the hole area 50 covers the hole area edge 313 of the power line 310 , and the hole area edge 313 is the edge of the power line 310 in the power line area 302 near the hole area 50 .
  • the first width L1 of the first isolation layer 60 covering the power line 310 may be greater than or equal to 2 ⁇ m, that is, the edge of the first isolation layer 60 on the side away from the hole area 50 and the edge 313 of the hole area of the power line 310 The distance between them can be greater than or equal to 2 ⁇ m, so that the edge of the hole area of the power line is completely covered by the first isolation layer 60 to prevent the peeling failure of the edge of the hole area of the power line.
  • the flat film on the side of the folded line-shaped second isolation layer 70 close to the display area is removed to form a third opening K3, which exposes the power line 310, and the side of the second isolation layer 70 close to the display area covers the first edge 311 of the power line 310, and the flat film on the side of the second isolation layer 70 away from the display area is removed.
  • the first width L1 of the second isolation layer 70 covering the power line 310 may be greater than or equal to 2 ⁇ m, that is, the distance between the edge of the second isolation layer 70 near the display area and the first edge 311 of the power line 310 The distance between them may be greater than or equal to 2 ⁇ m, so that the first edge of the power line is completely covered by the second isolation layer 70 to prevent the peeling failure of the first edge of the power line.
  • the flat film on the side of the ring-shaped first blocking layer 60 close to the hole area 50 is removed to form the first opening K1, and the flat film on the side away from the hole area 50 is removed.
  • a second opening K2 is formed between the first isolation layer 60 and the second isolation layer 70 and between adjacent first isolation layers 60 .
  • the cross-sectional shape of the first partition layer 60 and the second partition layer 70 can be trapezoidal, and the width of the partition layer on the side away from the base is smaller than the width of the partition layer on the side close to the substrate. width.
  • the edge area 303 includes the base 10, a composite insulating layer disposed on the base 10, and a first isolation layer 60 disposed on the composite insulating layer.
  • the edge area 303 is provided with a plurality of hole areas 50 penetrating through the base 10 and the composite insulating layer.
  • a blocking layer 60 is in the shape of a ring surrounding the hole area 50 .
  • forming the isolation groove pattern may include: depositing an inorganic material thin film on the substrate forming the aforementioned pattern, patterning the inorganic material thin film through a patterning process, and forming a first inorganic material covering the surface of the first isolation layer 60.
  • the inorganic material film can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single-layer, multi-layer or composite layer.
  • the process of forming the first inorganic layer, the second inorganic layer, and the isolation groove may include: depositing an inorganic material film on the substrate forming the aforementioned pattern, the inorganic material film completely covering the first isolation layer 60 and the second isolation layer 60 .
  • the upper surface and the side surface of the partition layer 70, the upper surface refers to the surface of the trapezoidal partition layer away from the base, and the side surface is the surface of the hypotenuse of the trapezoidal partition layer.
  • an etching process is used to etch the inorganic material film in the fully exposed area to form a first inorganic layer 96 that completely wraps the outer surface of the first isolation layer 60, a second inorganic layer 97 that completely wraps the outer surface of the second isolation layer 70, and
  • the partition holes respectively arranged on the first inorganic layer 96 and the second inorganic layer 97 are respectively located on the upper surfaces of the first partition layer 60 and the second partition layer 70, and the partition holes respectively expose the first partition layer 60 and part of the upper surface of the second isolation layer 70 .
  • the first isolation layer 60 and the second isolation layer 70 exposed in the isolation hole are etched continuously, and the isolation grooves formed on the first isolation layer 60 and the second isolation layer 70 respectively, the isolation hole and the isolation groove communicate with each other .
  • a dry etching process may be used for etching, and a gas with a large organic/inorganic etching ratio, such as O 2 , CF 4 , CHF 3 , etc., may be used. Since the organic/inorganic etching ratio is large, that is, the etching rate of the organic material is greater than the etching rate of the inorganic material, so when the first isolation layer 60 and the second isolation layer 70 of the organic material are etched, the isolation layer exists Laterally etched, the isolation groove on the isolation layer expands a certain distance relative to the isolation hole, forming an isolation groove 61 with a side-etched structure.
  • a gas with a large organic/inorganic etching ratio such as O 2 , CF 4 , CHF 3 , etc.
  • the first inorganic layer and the second inorganic layer located around the partition hole have protrusions relative to the side wall of the partition groove, and the protrusion and the side wall of the partition groove (near the partition hole) form an inner wall. trap structure.
  • the cross-sectional shape of the partition groove in a plane perpendicular to the base, is an inverted trapezoid, and the width of the opening on the side of the partition groove away from the base is greater than the width of the bottom opening of the partition groove near the base.
  • the sides of the inverted trapezoidal partition groove may be arc-shaped.
  • the side of the lower opening of the partition groove away from the hole area should ensure that the edge 313 of the hole area of the power line 310 does not leak out, and the second gap between the side of the lower opening away from the hole area and the edge of the hole area of the power line
  • the width L2 may be greater than or equal to 1 ⁇ m, so that the edge of the hole area of the power line is completely covered by the first isolation layer, preventing the peeling failure of the edge of the hole area of the power line.
  • the side of the lower opening of the partition groove close to the display area should ensure that the first edge 311 of the power line 310 does not leak out, and the second width L2 between the side of the lower opening close to the display area and the first edge can be greater than or equal to 1 ⁇ m, so that the first edge of the power line is completely covered by the second isolation layer, preventing peeling failure of the first edge of the power line.
  • the aperture of the partition hole is smaller than the aperture of the opening on the partition groove, and the orthographic projection of the partition hole on the base is within the range of the orthographic projection of the opening on the partition groove on the substrate.
  • the first inorganic layer 96 wrapping the outer surface of the first partition layer 60 and the second inorganic layer 97 wrapping the outer surface of the second partition layer 70 have edges protruding from the opening on the partition groove 61 to form an "eaves" structure, and the partition groove 61
  • the orthographic projection of the outline of the upper opening on the substrate is within the range of the orthographic projections of the first inorganic layer 96 and the second inorganic layer 97 on the substrate.
  • the width of the first inorganic layer 96 and the second inorganic layer 97 protruding from the opening edge of the isolation groove may be about 1 ⁇ m to 3 ⁇ m, that is, the isolation groove is expanded by 1 ⁇ m to 3 ⁇ m relative to the isolation hole.
  • the groove 61 constitutes a first isolation structure, and the first isolation structure is formed in the isolation area 51 surrounding the hole area 50 , and is an annular isolation structure surrounding the hole area 50 .
  • the second isolation layer 70 , the second inorganic layer 97 covering the second isolation layer 70 , the isolation holes provided on the second inorganic layer 97 , and the isolation grooves 61 provided on the second isolation layer 70 A second partition structure is formed.
  • the second partition structure is formed on the side of the first edge 311 away from the display area, and is a linear partition structure extending along the first edge 311 .
  • the first inorganic layer 96 on the side away from the hole area in the first isolation structure is built on the power line 310, and in the second isolation structure near the display area The second inorganic layer 97 on one side is built on the power line 310 .
  • the third width L3 of the first inorganic layer 96 and the second inorganic layer 97 on the power line 310 may be greater than or equal to 2 ⁇ m, and the first inorganic layer 96 and the first isolation layer between the power line 310 and the first isolation layer are improved.
  • the edge 313 of the hole area of the power line 310 is covered by the first isolation layer 60, and the first inorganic layer 96 covers the junction area between the first isolation layer 60 and the power line 310, so that the edge of the hole area of the power line is covered by double layers, It can effectively prevent the peeling failure at the edge of the power line hole area.
  • the first edge 311 of the power line 310 is covered by the second isolation layer 70, and the second inorganic layer 97 on the side close to the display area covers the junction area between the second isolation layer 70 and the power line 310, the first edge is covered by a double layer. The coating can effectively prevent the peeling failure of the first edge of the power cord.
  • the first partition structure and the second partition structure may include a third inorganic layer.
  • Forming the third inorganic layer pattern may include: depositing a thin film of inorganic material on the substrate forming the aforementioned pattern, patterning the thin film of inorganic material through a patterning process, and forming a layer covering the first inorganic layer 96, the second inorganic layer 97 and the isolation groove 61
  • the third inorganic layer 98 as shown in Figure 10d, Figure 10e and Figure 10f, Figure 10d is a cross-sectional view of A-A in Figure 3
  • Figure 10e is a cross-sectional view of B-B in Figure 6
  • Figure 10f is a cross-sectional view of C-C in Figure 6 cutaway view.
  • the third inorganic layer 98 serves as the third capping layer of the present disclosure.
  • the third covering layer may be made of a metal material, which is not limited in this disclosure.
  • the third inorganic layer 98 covers the first inorganic layer 96 and the second inorganic layer 97 , and covers the inner wall of the isolation groove 61 , It includes the side wall surface and the bottom surface covering the isolation groove 61 .
  • the complete wrapping of the inner wall of the partition groove by the third inorganic layer 98 ensures the integrity of the partition structure and the partition effect of the partition structure.
  • the third inorganic layer 98 may only cover the first inorganic layer and the isolation groove of the first isolation structure, or the third inorganic layer 98 may only cover the second inorganic layer and the isolation groove of the second isolation structure. Alternatively, the third inorganic layer 98 may simultaneously cover the first inorganic layer of the first isolation structure, the second inorganic layer of the second isolation structure, and the isolation groove.
  • the edge region 303 includes the substrate 10, the composite insulating layer disposed on the substrate 10 and the first isolation structure disposed on the composite insulating layer, and the edge region 303 is provided with a plurality of holes penetrating through the substrate 10 and the composite insulating layer In the region 50 , the first isolation structure is in the shape of a ring surrounding the hole region 50 .
  • forming the pattern of the anode and the connection electrode may include: depositing a conductive film on the substrate forming the aforementioned pattern, patterning the conductive film through a patterning process, and forming the pattern of the anode 71 and the connection electrode 72, as shown in Figure 11a , Figure 11b and Figure 11c, Figure 11a is a sectional view of A-A in Figure 3, Figure 11b is a sectional view of B-B in Figure 6, and Figure 11c is a sectional view of C-C in Figure 6.
  • the anode 71 is located on the planar layer 95 of the display area, and the anode 71 is connected to the first drain electrode of the first transistor 101 through an anode via hole.
  • the connection electrode 72 is located in the third opening K3 of the power line area 302 and overlaps the power line 310 exposed by the third opening K3 to realize the connection between the connection electrode 72 and the power line 310 .
  • the connection electrode 72 is configured to be connected to the subsequently formed cathode, so as to realize reliable connection of the cathode to the power line 310 through the connection electrode 72 .
  • the orthographic projection of the connection electrode 72 on the display substrate plane and the orthographic projection of the first inorganic layer 96 on the display substrate plane have at least a partial overlap.
  • the side of the connecting electrode 72 close to the hole area 50 covers the edge of the first inorganic layer 96 , the first inorganic layer 96 is the first inorganic layer 96 built on the power line 310 , and the edge is that the first inorganic layer 96 is away from the hole area. 50's edge.
  • the first inorganic layer 96 covers the first isolation layer 60, and the edge of the first inorganic layer 96 is covered by the connecting electrode 72, so that the hole area edge of the power line
  • the edges of the first inorganic layer and the first inorganic layer are sequentially coated, and the formed multiple coatings can effectively prevent the peeling failure of the edge of the power line hole area and the outer edge of the first partition structure.
  • the orthographic projection of the connection electrode 72 on the display substrate plane and the orthographic projection of the second inorganic layer 97 on the display substrate plane have at least a partial overlap.
  • the side of the connection electrode 72 away from the display area covers the edge of the second inorganic layer 97, which is the second inorganic layer 97 built on the power line 310, and the edge is the edge of the second inorganic layer 97 close to the display area. edge.
  • the second inorganic layer 97 covers the second isolation layer 70, and the edge of the second inorganic layer 97 is covered by the connection electrode 72, so that the first edge of the power line
  • the edges of the second inorganic layer and the second inorganic layer are coated in sequence, and the formed multiple coatings can effectively prevent the peeling failure of the first edge of the power line and the outer edge of the second partition structure.
  • the fourth width L4 of the connecting electrode 72 covering the first inorganic layer 96 and the second inorganic layer 97 can be designed according to actual needs, and the fourth width L4 can be greater than 0 but smaller than the third width L3.
  • the fourth width L4 may be about one quarter to one half of the third width L3.
  • the conductive film can be made of a metal material or a transparent conductive material, and the metal material can include any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • the transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the conductive thin film may be a single-layer structure, or a multi-layer composite structure, such as ITO/Al/ITO or the like.
  • forming the pixel definition layer and the barrier dam pattern may include: coating a pixel definition film on the substrate forming the aforementioned pattern, and patterning the pixel definition film by a patterning process to form the pixel definition layer 73, the second A partition dam 74 and a second partition dam 75 patterns, as shown in Figure 12a, Figure 12b and Figure 12c, Figure 12a is a sectional view of A-A direction in Figure 3, Figure 12b is a sectional view of B-B direction in Figure 6, and Figure 12c is a diagram Sectional view of C-C direction in 6.
  • the pixel definition layer 73 is formed in the display area, and a pixel opening is opened thereon, and the pixel definition layer in the pixel opening is removed to expose the surface of the anode 71 .
  • the spacer column pattern may be formed when the pixel definition layer is formed, and the spacer column is configured to support a mask (Mask) in a subsequent evaporation process.
  • the spacer column can be disposed outside the pixel opening, and the pixel definition layer and the spacer column pattern can be formed through the same patterning process through a half tone mask (Half Tone Mask).
  • Hyf Tone Mask half tone mask
  • the first partition dam 74 may be formed on the outer side of the first partition structure away from the hole area 50 , and is an annular dam surrounding the first partition structure.
  • the side of the first isolation dam 74 close to the hole area 50 is arranged on the first inorganic layer 96 of the first isolation structure on the side away from the hole area 50 , and the side of the first isolation dam 74 away from the hole area 50 is arranged on the connection electrode 72 , and completely cover the edge of the connection electrode 72 on the side close to the hole region 50 .
  • the fifth width L5 of the first blocking dam 74 covering the connecting electrode 72 may be greater than or equal to 1 ⁇ m, that is, the edge of the first blocking dam 74 on the side away from the hole area is the same as the edge of the connecting electrode 72 on the side close to the hole area.
  • the distance between the edges is greater than or equal to 1 ⁇ m, so that the edges of the connecting electrodes are completely covered by the first barrier dam 74 to prevent the peeling failure of the edges of the connecting electrodes.
  • the first barrier dam 74 can cover the edge of the connection electrode 72 on the side close to the hole area, or cover the edge of the first inorganic layer 96 on the side away from the hole area, or cover the connection electrode at the same time.
  • the orthographic projection of the edge of the connection electrode 72 on the substrate near the hole area is within the range of the orthographic projection of the first barrier dam 74 on the substrate, or the first inorganic layer 96 is far away from the hole area.
  • the orthographic projection of the edge of one side on the substrate is within the range of the orthographic projection of the first barrier dam 74 on the substrate, or the orthographic projection of the edge of the connecting electrode 72 on the substrate near the hole area and the first inorganic layer
  • the orthographic projections of the edge of 96 on the base away from the hole area are within the range of the orthographic projection of the first partition dam 74 on the base.
  • the partial overlap is within the range of the orthographic projection of the first barrier dam 74 on the substrate. Because the edge 313 of the hole area of the power line 310 is covered by the first isolation layer 60, the first inorganic layer 96 covers the first isolation layer 60, the edge of the first inorganic layer 96 is covered by the connection electrode 72, and the edge of the connection electrode 72 is covered by the second electrode 72.
  • a blocking dam 74 is covered, so that the edge of the hole area of the power line, the edge of the first inorganic layer and the edge of the connecting electrode are covered sequentially, and the formed multiple coatings can effectively prevent the edge of the hole area of the power line, the edge of the first inorganic layer and the connection electrode. The peeling failure of the electrode edge.
  • the first isolation dam may be disposed in the power line area to achieve multiple coatings on the edge of the film layer.
  • the first barrier dam can be set in the display area, the circuit area, the power line area and the edge area. The isolation effect of the first isolation structure in the circuit area and the edge area.
  • the first partition dam may be arranged on the side of the partition groove away from the hole area, at this time, on the inside close to the hole area and the outside away from the hole area, the first partition structure including the first partition dam has different heights.
  • the distance between the top surface of the first partition structure outside the hole area (the surface of the first partition dam away from the base) and the base is greater than the top surface of the first partition structure near the inside of the hole area (the first inorganic layer is away from The distance between the surface on one side of the base) and the base.
  • the first partition dam can be arranged on the side of the partition groove close to the hole area and the side away from the hole area at the same time, forming two annular dams surrounding the hole area 50 .
  • the second partition dam 75 may be formed on a side of the second partition structure close to the display area, and is a linear dam extending along the first edge 311 .
  • the side of the second isolation dam 75 away from the display area is disposed on the second inorganic layer 97 on the side of the second isolation structure close to the display area, and the side of the second isolation dam 75 close to the display area is disposed on the connecting electrode 72, and completely Cover the edge of the connection electrode 72 on the side away from the display area.
  • the fifth width L5 of the second isolation dam 75 covering the connection electrode 72 may be greater than or equal to 1 ⁇ m, that is, the edge of the second isolation dam 75 on the side close to the display area is the same as the edge of the connection electrode 72 on the side away from the display area.
  • the distance between the edges is greater than or equal to 1 ⁇ m, so that the edges of the connecting electrodes are completely covered by the second barrier dam 75 to prevent the peeling failure of the edges of the connecting electrodes.
  • the second barrier dam 75 can cover the edge of the connecting electrode 72 away from the display area, or cover the edge of the second inorganic layer 97 near the display area, or cover the connecting electrode at the same time.
  • the orthographic projection of the edge of the connecting electrode 72 away from the display area on the substrate is within the range of the orthographic projection of the second barrier dam 75 on the substrate, or the second inorganic layer 97 is close to the display area
  • the orthographic projection of the edge of one side on the substrate is located within the range of the orthographic projection of the second barrier dam 75 on the substrate, or the orthographic projection of the edge of the connection electrode 72 away from the side of the display area on the substrate and the second inorganic layer
  • the orthographic projections of the edge of 97 on the base near the side of the display area are all within the range of the orthographic projection of the second partition dam 75 on the base.
  • the partial overlap is within the range of the orthographic projection of the second barrier dam 75 on the substrate. Because the first edge 311 of the power supply line 310 is covered by the second isolation layer 70, the second inorganic layer 97 covers the second isolation layer 70, the edge of the second inorganic layer 97 is covered by the connection electrode 72, and the edge of the connection electrode 72 is covered by the first electrode 72.
  • Two partition dams 75 cover, so that the first edge of the power line, the second inorganic layer edge and the edge of the connecting electrode are coated sequentially, and the formed multiple coatings can effectively prevent the first edge of the power line, the second inorganic layer edge and the Peeling failure at the edge of the connecting electrode.
  • the second partition dam may be disposed on a side of the second partition structure close to the display area, so as to realize multiple coatings on the edge of the film layer.
  • the second partition structure including the second partition dam has different heights.
  • the second partition dam can be arranged on the side of the second partition structure close to the display area and the side away from the display area at the same time, forming two linear dams extending along the first edge, While achieving multiple coatings on the edge of the film layer, the partition effect of the second partition structure is improved.
  • the pixel definition layer may use polyimide, acrylic, polyethylene terephthalate, or the like.
  • the shape of the pixel opening may be a triangle, a rectangle, a polygon, a circle, or an ellipse.
  • the cross-sectional shape of the pixel opening can be rectangular or trapezoidal, etc.
  • the cross-sectional shape of the first barrier dam 74 and the second barrier dam 75 can be trapezoidal, and the width of the side of the barrier dam away from the base is smaller than that of the partition wall. The width of the side of the dam near the base.
  • Forming an organic light-emitting layer pattern may include: forming a pattern of the organic light-emitting layer 76 by evaporation or inkjet printing on the substrate on which the aforementioned pattern is formed, as shown in FIG. 13a, FIG. 13b and FIG. 13c , FIG. 13a is a sectional view of A-A direction in FIG. 3 , FIG. 13b is a sectional view of B-B direction in FIG. 6 , and FIG. 13c is a sectional view of C-C direction in FIG. 6 .
  • the organic light emitting layer 76 may be formed only in the display area, and the organic light emitting layer 76 is connected to the anode 71 through the pixel opening.
  • the isolation groove 61 has a side-etched structure, and the first inorganic layer 96 and the second inorganic layer 97 have a "eaves" structure protruding from the opening on the isolation groove 61, the organic light-emitting layer in the display area 76 is disconnected at the "eaves" structure of the partition groove 61, and an organic light-emitting block is formed at the bottom of the partition groove 61, and the organic light-emitting block and the organic light-emitting layer 76 are separated from each other.
  • the organic light-emitting layer is disconnected by setting the partition groove, which can cut off the transmission channel of water and oxygen, and effectively block the intrusion of water and oxygen from the hole area.
  • the organic light-emitting layer 76 in the display area is disconnected at the "eaves" structure of the hole area 50, and An organic light-emitting block is formed on the glass carrier 1 at the bottom of the area 50 , and the organic light-emitting block is isolated from the organic light-emitting layer 76 .
  • an organic light-emitting block is formed at the bottom of the hole area of the display area, so that the subsequently formed inorganic encapsulation layer is formed on the organic light-emitting block. Since the organic light-emitting material is easily separated from the glass substrate, the display substrate and the glass carrier are effectively avoided. The case where the film layer cannot be peeled off during the peeling process.
  • the organic light-emitting layer 76 can be formed only in the display area through the design of the mask plate, or the organic light-emitting layer 76 can be formed in the display area, as well as the circuit area 301, the power line area 302 and the edge In any one or more regions in the region 303, the bottoms of the isolation grooves and the bottoms of the hole regions in these regions form an organic light-emitting block.
  • the organic light-emitting layer may include an light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole Blocking Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL).
  • EML Electron Injection Layer
  • the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (Fine Metal Mask, FMM for short) or an open mask (Open Mask), or by an inkjet process.
  • the organic light-emitting layer may be prepared using the following preparation method. Firstly, the hole injection layer and the hole transport layer are evaporated sequentially by using an open mask to form a common layer of the hole injection layer and the hole transport layer on the display substrate.
  • the electron blocking layer and the light-emitting layer of adjacent sub-pixels may have a small amount of overlap (for example, the overlapping portion accounts for less than 10% of the area of the respective light-emitting layer pattern), or may be isolated.
  • the hole blocking layer, the electron transport layer and the electron injection layer are evaporated sequentially by using an open mask to form a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.
  • the electron blocking layer can be used as a microcavity adjustment layer of the light-emitting device.
  • the thickness of the electron blocking layer By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and the anode can meet the design of the length of the microcavity.
  • the hole transport layer, the hole blocking layer or the electron transport layer in the organic light-emitting layer can be used as the microcavity adjustment layer of the light-emitting device, and the present disclosure is not limited here.
  • the light emitting layer may include a host (Host) material and a guest (Dopant) material doped in the host material, and the doping ratio of the guest material in the light emitting layer is 1% to 20%.
  • the host material of the light-emitting layer can effectively transfer the excitonic energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light; ", which effectively improves the fluorescence quenching caused by the collision between molecules of the guest material in the light-emitting layer and the collision between energy, and improves the luminous efficiency and device life.
  • the doping ratio refers to the ratio of the mass of the guest material to the mass of the light emitting layer, that is, the mass percentage.
  • the host material and the guest material can be co-evaporated by a multi-source evaporation process, so that the host material and the guest material can be uniformly dispersed in the light-emitting layer, and the evaporation rate of the guest material can be controlled during the evaporation process.
  • the thickness of the light emitting layer may be about 10 nm to 50 nm.
  • the hole injection layer can use inorganic oxides, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide , tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or a p-type dopant and a dopant of a hole transport material that can use a strong electron-withdrawing system.
  • the hole injection layer may have a thickness of about 5 nm to 20 nm.
  • the hole transport layer can use a material with higher hole mobility, such as an aromatic amine compound, and its substituent group can be carbazole, methylfluorene, spirofluorene , dibenzothiophene or furan, etc.
  • the hole transport layer may have a thickness of about 40 nm to 150 nm.
  • the hole blocking layer and the electron transport layer can use aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazopyridine derivatives; pyrimidine derivatives, triazine derivatives and other oxazine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives and other compounds containing nitrogen-containing six-membered ring structures (including those with phosphine oxide series on the heterocycle Substituent compounds), etc.
  • the hole blocking layer may have a thickness of about 5 nm to 15 nm
  • the electron transport layer may have a thickness of about 20 nm to 50 nm.
  • the electron injection layer can be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg) or calcium (Ca), or a compound of these alkali metals or metals. Wait.
  • the electron injection layer may have a thickness of about 0.5 nm to 2 nm.
  • forming the cathode pattern may include: forming a cathode 77 pattern by evaporation on the substrate on which the aforementioned pattern is formed, as shown in FIG. 14a, FIG. 14b and FIG. 14c, and FIG.
  • the sectional view of A-A direction, Fig. 14b is the sectional view of B-B direction in Fig. 6, and Fig. 14c is the sectional view of C-C direction in Fig. 6 .
  • the cathode may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one of the above metals Alloys made of one or more types.
  • the stretchable cathode 77 may be formed in the display area, the circuit area 301 and the power line area 302 , and may be a connected integral structure.
  • the cathode 77 in the display area is connected to the organic light-emitting layer 76 , so that the organic light-emitting layer 76 is connected to the anode 71 and the cathode 77 at the same time.
  • the cathode 77 of the power supply line area 302 is connected to the connection electrode 72 exposed by the third opening K3. Since the power supply line 310 is connected to the connection electrode 72 and the connection electrode 72 is connected to the cathode 77, the connection between the cathode 77 and the power supply line 310 is realized.
  • the isolation groove 61 is a side-etched structure, and the first inorganic layer 96 and the second inorganic layer 97 have a "eaves" structure protruding from the opening on the isolation groove 61, the display area, the circuit area 301 and the The cathode 77 in the power line area 302 is disconnected at the "eaves" structure of the partition groove 61, and a cathode block is formed at the bottom of the partition groove 61, and the cathode block and the cathode 77 are separated from each other.
  • the composite insulating layer on the inner wall of the hole area 50 has a "eaves" structure protruding from the base, the cathodes 77 in the display area, the circuit area 301 and the power line area 302 are in the "eaves" of the hole area 50.
  • the structure is disconnected, and a cathode block is formed on the glass carrier plate 1 at the bottom of the hole area 50, and the cathode block and the cathode 77 are separated from each other.
  • the partition groove to disconnect the cathode, the transmission channel of water and oxygen can be cut off, and the intrusion of water and oxygen from the hole area can be effectively blocked.
  • the cathode block in the display area, is disposed on the organic light emitting block at the bottom of the partition groove 61 and the bottom of the hole area 50 .
  • the cathode block In the circuit area 301 and the power line area 302 , the cathode block is arranged on the glass substrate 1 at the bottom of the isolation groove 61 and the bottom of the hole area 50 .
  • the cathode block is formed at the bottom of the hole area in the circuit area and the power line area, so that the subsequently formed inorganic packaging layer is formed on the cathode block. Since the cathode block formed by evaporation is easy to separate from the glass substrate, it effectively avoids display. The case where the film layer cannot be peeled off during the peeling process of the substrate and the glass carrier.
  • the cathode 77 of the monolithic structure completely wraps the first barrier dam 74 and the second barrier dam 75 . Because the edge 313 of the hole region of the power line 310 is covered by the first isolation layer 60, the first inorganic layer 96 covers the first isolation layer 60, the edge of the first inorganic layer 96 is covered by the connection electrode 72, and the edge of the connection electrode 72 is covered by the first The partition dam 74 is covered, and the first partition dam 74 is completely covered by the cathode 77, so that the edge of the hole area of the power line, the edge of the first inorganic layer, the edge of the connecting electrode and the first partition dam are sequentially coated, and the formed multiple coating
  • the stripping failure at the edge of the power line hole area, the edge of the first inorganic layer and the edge of the connecting electrode can be further prevented, and the smoothness of the structure surface can be ensured.
  • the second inorganic layer 97 covers the second isolation layer 70
  • the edge of the second inorganic layer 97 is covered by the connecting electrode 72
  • the edge of the connecting electrode 72 is covered by the second
  • the partition dam 75 is covered, and the second partition dam 75 is completely covered by the cathode 77, so that the first edge of the power line, the second inorganic layer edge, the connection electrode edge and the second partition dam are sequentially coated, and the formed multiple coating It can further prevent the peeling failure of the first edge of the power line, the edge of the second inorganic layer and the edge of the connecting electrode, and ensure the smoothness of the structure surface.
  • the cathode can be formed in the edge region 303 through the design of the mask plate, so that the bottom of the partition groove and the bottom of the hole region in the edge region form a cathode block.
  • forming the pattern of the optical coupling layer may include: forming the pattern of the optical coupling layer 78 by evaporation on the substrate on which the foregoing pattern is formed, as shown in FIG. 15a, FIG. 15b and FIG. 15c, and FIG. 15a is a diagram Figure 15b is a cross-sectional view of direction A-A in Figure 3, Figure 15b is a cross-sectional view of direction B-B in Figure 6, Figure 15c is a cross-sectional view of direction C-C in Figure 6.
  • the optical coupling layer 78 may be formed in the display area, the circuit area 301 , the power line area 302 and the edge area 303 , and may be a connected integral structure.
  • the optical coupling layer 78 is disposed on the cathode 77, and in the edge area 303, the optical coupling layer 78 is disposed on the composite insulating layer and the first isolation structure.
  • the isolation groove 61 has a side-etched structure, and the first inorganic layer 96 and the second inorganic layer 97 have a "eaves" structure protruding from the opening on the isolation groove 61, the optical coupling layer 78 is formed in the isolation groove. 61 is disconnected at the "eaves" structure, and an optical coupling block is formed at the bottom of the isolation groove 61, and the optical coupling block and the optical coupling layer 78 are isolated from each other.
  • the optical coupling layer 78 is disconnected at the "eaves" structure of the hole area 50, and at the bottom of the hole area 50
  • An optical coupling block is formed on the glass carrier 1 , and the optical coupling block is isolated from the optical coupling layer 78 .
  • the optical coupling block is disconnected by setting the partition groove, which can cut off the transmission channel of water and oxygen, and effectively block the intrusion of water and oxygen from the hole area.
  • the optical coupling block in the display area, the circuit area 301 and the power line area 302 , is disposed on the cathode block at the bottom of the isolation groove 61 and the hole area 50 .
  • the optical coupling block is disposed on the glass substrate 1 at the bottom of the isolation groove 61 and the bottom of the hole area 50 .
  • the optical coupling block is formed at the bottom of the hole area in the edge area, so that the subsequently formed inorganic encapsulation layer is formed on the optical coupling block. Since the optical coupling block formed by evaporation is easy to separate from the glass substrate, the display substrate is effectively avoided. The case where the film layer cannot be peeled off during the peeling process from the glass carrier.
  • the optical coupling layer in the edge region covers the edge of the first inorganic layer on the side away from the hole region, which can prevent the peeling failure of the edge of the first inorganic layer in the edge region to a certain extent.
  • the refractive index of the optical coupling layer may be greater than that of the cathode, which facilitates light extraction and increases light extraction efficiency.
  • the material of the optical coupling layer may be an organic material, or an inorganic material, or an organic material and an inorganic material, and may be a single layer, a multi-layer or a composite layer, which is not limited in this disclosure.
  • a light wave (electromagnetic wave) is incident on the interface between the metal and the dielectric
  • the free electrons on the metal surface oscillate collectively, and the electromagnetic wave is coupled with the free electrons on the metal surface to form a near-field that propagates along the metal surface
  • Electromagnetic waves if the oscillation frequency of electrons is consistent with the frequency of incident light waves, resonance will occur. In the resonance state, the energy of the electromagnetic field is effectively transformed into the collective vibration energy of free electrons on the metal surface. At this time, a special electromagnetic mode is formed. : The electromagnetic field is confined to a small range on the metal surface and is enhanced.
  • SPP Surface Plasmon Polariton
  • the light emitting structure layer includes an anode 71 , an organic light emitting layer 76 , a cathode 77 and an optical coupling layer 78 , and the organic light emitting layer 76 is disposed between the anode 71 and the cathode 77 .
  • forming the encapsulation layer pattern may include: using an open mask plate to deposit a first inorganic encapsulation film in a deposition manner on the substrate on which the aforementioned pattern is formed, in the display area, the circuit area 301, and the power line area 302 and the edge region 303 form the first encapsulation layer 81 .
  • the organic packaging material is printed by an inkjet printing process, the organic packaging material is patterned, the organic packaging material near the hole area and the hole area is removed, and after curing into a film, the display area, circuit area 301, power line area 302 and The edge region 303 forms the second encapsulation layer 82 .
  • FIG. 16a is a sectional view of A-A direction in FIG. 3
  • FIG. 16b is a sectional view of B-B direction in FIG. 6
  • FIG. 16c is a sectional view of C-C direction in FIG. 6 .
  • the first encapsulation layer 81 is disposed on the optical coupling layer 78, and covers the inner walls of the isolation groove 61 and the hole area 50, covering The optical coupling block at the bottom of the isolation groove 61 and the hole area 50 .
  • the first encapsulation layer 81 completely wraps the hole area and the partition groove to ensure the integrity of the package, not only effectively isolating the water and oxygen from the hole area, but also the partition groove forms a pinning point for the encapsulation layer, which can further prevent the peeling of the edge of the film layer invalidated.
  • the second encapsulation layer 82 is disposed on the first encapsulation layer 81 and completely fills the isolation groove 61 .
  • the second encapsulation layer 82 in the hole area and the area near the hole area is removed to expose the surface of the first encapsulation layer 81 .
  • the third encapsulation layer 83 is arranged on the second encapsulation layer 82 to form a laminated structure of inorganic material/organic material/inorganic material.
  • the third encapsulation layer 83 is arranged on On the first encapsulation layer 81 , a stacked structure of inorganic material/inorganic material is formed.
  • the stacked structure of inorganic materials/organic materials/inorganic materials in the area outside the hole area can ensure effective packaging, and the stacked structure of inorganic materials/inorganic materials in the hole area and the area near the hole area can further ensure the integrity of the package and effectively isolate the components from the hole area. of water and oxygen.
  • the first packaging film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be single-layer, multi-layer or
  • the composite layer can ensure that external water and oxygen cannot enter the light-emitting structure layer.
  • the organic encapsulation material can be made of a resin material, which plays the role of covering each film layer of the display substrate, so as to improve the structural stability and flatness.
  • the first encapsulation layer and the second encapsulation layer constitute an encapsulation layer.
  • a touch structure layer may be formed on the encapsulation layer, and the touch structure layer may include a touch electrode layer, or include a touch electrode layer and a touch insulation layer. It is not limited here.
  • the hole area can be etched through a patterning process, and the film layer at the bottom of the hole area can be etched away to form a through hole.
  • the etching process basically etches along the surface of the first encapsulation layer covering the inner wall of the through hole
  • the inner wall of the through hole formed by final etching may include a base segment, an organic material segment and an inorganic material segment, and the base segment, The organic material segments and the inorganic material segments are arranged along a direction from the substrate to the first encapsulation layer.
  • the base segment in the inner wall of the hole area of the display region, may include an inner wall formed by a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer, and the organic material segment
  • the inner wall formed by the organic material block, the cathode block and the optical coupling block may be included, and the inorganic material segment may be the inner wall formed by the first encapsulation layer.
  • the base segment in the inner wall of the hole area of the circuit area and the power line area, may include an inner wall formed of a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer
  • the organic material segment may include an inner wall formed by the cathode block and the optical coupling block
  • the inorganic material segment may include an inner wall formed by the first encapsulation layer.
  • the base segment in the inner wall of the hole area in the edge area, may include an inner wall formed by a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer, and the organic material segment
  • the inner wall may be formed by the optical coupling block, and the segment of inorganic material may be the inner wall formed by the first encapsulation layer.
  • the display substrate and the glass substrate can be peeled off by a laser lift-off process.
  • Exemplary embodiments of the present disclosure form an organic material in the hole region, and the subsequently formed first encapsulation layer is formed on the organic material.
  • the via hole by etching even if the first encapsulation layer at the bottom of the via hole is not completely etched away , part of the first encapsulation layer remains, but the remaining first encapsulation layer is set on the organic material. Since the adhesion between the organic material and the glass substrate is weak, the organic material is easy to bond with the glass substrate in the laser lift-off process. Separation effectively avoids the situation that the film layer cannot be peeled off during the peeling process of the display substrate and the glass carrier.
  • the preparation process of the display substrate may also include processes such as attaching a back film and cutting, which are not limited in this disclosure.
  • the exemplary embodiment of the present disclosure effectively avoids the peeling of the edge of the film layer by forming an edge multiple coating structure in the area where the edge of the power line is located, especially Stripping of the edge of the power cord.
  • the edge of the hole area and the first edge of the power line are covered by the partition layer, the partition layer is covered by the inorganic layer, the edge of the inorganic layer is covered by the connection electrode, the edge of the connection electrode is covered by the partition dam, and the partition dam Covered by the cathode, so that the edge of the power line, the edge of the inorganic layer, the edge of the connecting electrode and the partition dam are sequentially covered, the formed edge multiple coating structure can effectively avoid the peeling failure of the edge of the power line, the edge of the inorganic layer and the edge of the connecting electrode,
  • the stretchable edge structure is stable and reliable, avoiding the formation of water and oxygen transmission channels at the edge of the film layer, and effectively ensuring the packaging effect of the display substrate.
  • Exemplary embodiments of the present disclosure form an organic material in the hole area, so that the subsequently formed first encapsulation layer is disposed on the organic material, and the organic material can be separated from the glass substrate without damage, not only avoiding that the film layer of the display substrate cannot be separated from the glass substrate.
  • the substrate is separated, and the pulling cracks in the first encapsulation layer are avoided, effectively ensuring the encapsulation effect of the display substrate.
  • the exemplary embodiment of the present disclosure shows that the preparation process of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield rate.
  • Fig. 17a and Fig. 17b are schematic cross-sectional structure diagrams of another display substrate according to an exemplary embodiment of the present disclosure.
  • Fig. 17a illustrates a cross-sectional structure at the junction of the circuit area 301 and the power line area 302, which is a cross-sectional view along the B-B direction in Fig. 6 .
  • 17b shows the cross-sectional structure of the junction of the power line region 302 and the edge region 303, which is a cross-sectional view along the direction C-C in FIG. 6 .
  • the film layer structure of the display area, the composite insulating layer of the power line area, and the power line are substantially the same as those of the foregoing embodiments.
  • the first partition structure includes a first partition layer 60 surrounding the hole region 50 , a first inorganic layer 96 disposed on the first partition layer 60 , and a third inorganic layer 96 disposed on the first inorganic layer 96 .
  • layer 98 the first partition layer 60 is provided with partition grooves 61 surrounding the hole area 50 , the first inorganic layer 96 is provided with partition holes surrounding the hole region 50 , and the partition holes communicate with the partition grooves.
  • the first inorganic layer 96 located around the partition hole has a protrusion relative to the side wall of the partition groove 61, and the protrusion and the side wall of the partition groove form an indented structure.
  • the third inorganic layer 98 covers the first inorganic layer 96 and covers the partition. The inner wall of the groove 61.
  • the first isolation layer 60 in the first isolation structure covers the hole area edge 313 on the side of the power line 310 close to the hole area 50 , and the first inorganic layer on the side away from the hole area 50 in the first isolation structure 96 and the third inorganic layer 98 are not in direct contact with the power line 310, that is, the orthographic projections of the first inorganic layer 96 and the third inorganic layer 98 on the substrate do not overlap with the orthographic projection of the power line 310 on the substrate.
  • the side of the connection electrode 72 close to the hole area 50 is not in direct contact with the first inorganic layer 96 and the third inorganic layer 98 on the side away from the hole area 50 in the first isolation structure, and the first inorganic layer 96
  • the orthographic projection of the third inorganic layer 98 on the substrate and the orthographic projection of the connection electrode 72 on the substrate do not overlap.
  • the first isolation dam 74 is arranged on the side of the first isolation structure away from the hole area 50 , and the side of the first isolation dam 74 close to the hole area 50 covers the first inorganic layer 96 and the third inorganic layer 98 At the edge of the side away from the hole area 50 , the orthographic projections of the first inorganic layer 96 and the third inorganic layer 98 on the substrate overlap with the orthographic projections of the first blocking dam 74 on the substrate.
  • the side of the first barrier dam 74 away from the hole area 50 covers the edge of the connection electrode 72 near the hole area 50 , and the orthographic projection of the connection electrode 72 on the substrate overlaps with the orthographic projection of the first barrier dam 74 on the substrate.
  • the second partition structure includes a second partition layer 70 extending along the first edge 311 , a second inorganic layer 97 disposed on the second partition layer 70 , and a second inorganic layer 97 disposed on the second inorganic layer 97 .
  • the third inorganic layer 98, the second isolation layer 70 is provided with the isolation groove 61 extending along the first edge 311, the second inorganic layer 97 is provided with the isolation hole extending along the first edge 311, the isolation hole and the isolation groove connected.
  • the second inorganic layer 97 located around the partition hole has a protrusion relative to the side wall of the partition groove 61, and the protrusion and the side wall of the partition groove form an indented structure.
  • the third inorganic layer 98 covers the second inorganic layer 97 and covers the partition. The inner wall of the groove 61.
  • the second isolation layer 70 in the second isolation structure covers the first edge 311 of the power line 310, and the second inorganic layer 97 on the side near the display area in the second isolation structure is not directly connected to the power line 310.
  • the orthographic projections of the second inorganic layer 97 and the third inorganic layer 98 on the substrate do not overlap with the orthographic projection of the power line 310 on the substrate.
  • the side of the connection electrode 72 close to the first edge 311 is not in direct contact with the second inorganic layer 97 and the third inorganic layer 98 on the side close to the display area of the second isolation structure, and the second inorganic layer 97 and The orthographic projection of the third inorganic layer 98 on the substrate does not overlap with the orthographic projection of the connection electrode 72 on the substrate.
  • the second isolation dam 75 is arranged on the side of the second isolation structure close to the display area, and the side of the second isolation dam 75 away from the display area covers the second inorganic layer 97 and the third inorganic layer 98 Near the edge of one side of the display area, the orthographic projections of the second inorganic layer 97 and the third inorganic layer 98 on the substrate overlap with the orthographic projections of the second barrier dam 75 on the substrate.
  • the side of the second barrier dam 75 close to the display area covers the edge of the connection electrode 72 close to the first edge 311 , and the orthographic projection of the connection electrode 72 on the substrate overlaps with the orthographic projection of the second barrier dam 75 on the substrate.
  • the cathode 77 wraps the first partition dam 74 and the second partition dam 75 , that is, the cathode 77 covers all exposed surfaces of the first partition dam 74 and the second partition dam 75 .
  • the first isolation layer 60 and the second isolation layer 70 can be arranged in the same layer as the flat layer in the driving circuit layer, and the first isolation dam 74 and the second isolation dam 75 can be arranged in the same layer as the pixel in the light emitting structure layer.
  • the definition layers are set on the same layer, the first inorganic layer and the second inorganic layer are set on the same layer, and are set on the same layer as one insulating layer in the display area, and the third inorganic layer can be set on the same layer as another insulating layer in the display area.
  • another manufacturing process of a display substrate according to an exemplary embodiment of the present disclosure may include the following operations.
  • a partition groove pattern is formed.
  • forming the partition groove pattern may include: depositing a thin film of inorganic material on the substrate on which the aforementioned pattern is formed, and patterning the thin film of inorganic material through a patterning process to form a first part of the surface covering the first partition layer 60 .
  • the side of the first inorganic layer 96 close to the hole area 50 covers the surface of the first isolation layer 60 near the hole area 50
  • the side of the first inorganic layer 96 away from the hole area 50 is located on the surface of the first blocking layer 60 on the side away from the substrate, and part of the surface of the first blocking layer 60 away from the side of the hole area 50 is not covered by the first inorganic layer 96, Therefore, the side of the first inorganic layer 96 away from the hole region 50 is not directly connected to the power line 310 , and the orthographic projection of the first inorganic layer 96 on the substrate and the orthographic projection of the power line 310 on the substrate have no overlapping area.
  • the side of the second inorganic layer 97 away from the display area covers the surface of the second isolation layer 70 on the side away from the display area.
  • the side of the second inorganic layer 97 close to the display area is located on the surface of the second barrier layer 70 away from the substrate, and the part of the surface of the second barrier layer 70 close to the display area is not covered by the second inorganic layer 97, so the second inorganic
  • the side of the layer 97 close to the display area is not directly connected to the power line 310 , and the orthographic projection of the second inorganic layer 97 on the substrate and the orthographic projection of the power line 310 on the substrate have no overlapping area.
  • the first inorganic layer 96 of the first partition structure in the edge region 303 covers the outer surface of the first partition layer 60 .
  • the structure and process of forming the isolation groove with the undercut structure in the first isolation structure and the second isolation structure are similar to the foregoing exemplary embodiments.
  • forming the third inorganic layer pattern may include: depositing an inorganic material thin film on the substrate forming the aforementioned pattern, and patterning the inorganic material thin film through a patterning process to form a third inorganic layer 98 pattern, as shown in FIG. 19a and FIG. 19b, FIG. 19a is a sectional view of B-B direction in FIG. 6, and FIG. 19b is a sectional view of C-C direction in FIG. 6.
  • the third inorganic layer 98 is disposed on the side of the first inorganic layer 96 and the second inorganic layer 97 away from the substrate, and covers the inner wall of the partition groove 61, and covering the inner wall includes covering the side wall surface of the partition groove 61 and bottom surface. The complete wrapping of the inner wall of the partition groove by the third inorganic layer 98 ensures the integrity of the partition structure and the partition effect of the partition structure.
  • the side of the third inorganic layer 98 close to the hole area 50 covers the surface of the first inorganic layer 96 on the side close to the hole area 50
  • the side of the third inorganic layer 98 away from the hole area 50 is located on the surface of the first inorganic layer 96 away from the substrate, and the edge of the third inorganic layer 98 on the side away from the hole area 50 is the same as that of the first inorganic layer 96 away from the hole area.
  • the edge on one side of 50 is substantially flush, so that the side of the third inorganic layer 98 away from the hole area 50 is not directly connected to the power line 310, and the orthographic projection of the first inorganic layer 96 and the third inorganic layer 98 on the substrate is consistent with the power supply line.
  • the orthographic projection of line 310 onto the substrate has no overlapping regions.
  • the side of the third inorganic layer 98 away from the display area covers the surface of the second inorganic layer 97 on the side away from the display area, and the second The side of the third inorganic layer 98 close to the display area is located on the surface of the second inorganic layer 97 away from the substrate, and the edge of the third inorganic layer 98 close to the display area and the edge of the second inorganic layer 97 close to the display area It is substantially flat, so that the side of the third inorganic layer 98 close to the display area is not directly connected to the power line 310, and the orthographic projection of the second inorganic layer 97 and the third inorganic layer 98 on the substrate is the same as that of the power line 310 on the substrate. Orthographic projections have no overlapping areas.
  • the isolation hole and the third inorganic layer 98 disposed on the first inorganic layer 96 and covering the inner wall of the isolation groove form a first isolation structure, and the first isolation structure is formed in the isolation area 51 surrounding the hole area 50, which is the surrounding area of the hole area 50. Ring partition structure.
  • the partition hole and the third inorganic layer 98 disposed on the second inorganic layer 97 and covering the inner wall of the partition groove form a second partition structure.
  • the second partition structure is formed on the side of the first edge 311 away from the display area, along the first edge 311.
  • a linear partition structure extending from an edge 311 .
  • connection electrode pattern may include: depositing a conductive film on the substrate forming the aforementioned pattern, and patterning the conductive film through a patterning process to form the connection electrode pattern, as shown in FIG. 20a and FIG. 20b , Fig. 20a is a sectional view along the direction B-B in Fig. 6, and Fig. 20b is a sectional view along the direction C-C in Fig. 6 .
  • connection electrode 72 is disposed on a side of the power line area 302 away from the substrate, so as to realize the connection between the connection electrode 72 and the power line 310 .
  • the edge of the connection electrode 72 near the hole area 50 is spaced from the first partition structure by a certain distance, and the connection electrode 72 is not connected to the first partition layer 60, the first inorganic layer 96, and the third inorganic layer 98.
  • the orthographic projection of the connection electrode 72 on the substrate does not overlap with the orthographic projections of the first isolation layer 60 , the first inorganic layer 96 and the third inorganic layer 98 on the substrate in the first isolation structure.
  • the edge of the connection electrode 72 away from the display area is spaced from the second isolation structure by a certain distance, and the connection electrode 72 is not in contact with the second isolation layer 70, the second inorganic layer 97, and the third inorganic layer 98.
  • the orthographic projection of the connection electrode 72 on the substrate does not overlap with the orthographic projections of the second isolation layer 70 , the second inorganic layer 97 and the third inorganic layer 98 on the substrate in the second isolation structure.
  • forming the barrier dam pattern may include: coating a pixel-defining film on the substrate forming the aforementioned pattern, and patterning the pixel-defining film through a patterning process to form the first barrier dam 74 and the second barrier barrier 75 pattern, as shown in Figure 21a and Figure 21b, Figure 21a is a cross-sectional view of B-B in Figure 6, and Figure 21b is a cross-sectional view of C-C in Figure 6.
  • the first partition dam 74 may be formed on the outer side of the first partition structure away from the hole area 50 , and is an annular dam surrounding the first partition structure.
  • the side of the first partition dam 74 close to the hole area 50 is disposed on the third inorganic layer 98 on the side of the first partition structure away from the hole area 50 , and completely covers the first inorganic layer 96 and the third inorganic layer 98 away from the hole area 50 edge on one side.
  • the first blocking dam 74 is disposed on the connection electrode 72 at a side away from the hole area 50 , and completely covers the edge of the connection electrode 72 near the hole area 50 .
  • the first barrier dam 74 simultaneously covers the edge of the connection electrode 72 on the side close to the hole area, and the edges of the first inorganic layer 96 and the third inorganic layer 98 on the side away from the hole area.
  • the orthographic projection of the edge of the connection electrode 72 on the substrate near the hole area is within the range of the orthographic projection of the first barrier dam 74 on the substrate, and the first inorganic layer 96 and the third inorganic layer
  • the orthographic projection of the edge of 98 on the base away from the side of the hole area is within the range of the orthographic projection of the first partition dam 74 on the base.
  • the edge 313 of the hole region of the power supply line 310 is covered by the first blocking layer 60, and the edges of the first inorganic layer 96 and the third inorganic layer 98 and the edge of the connecting electrode 72 are covered by the first blocking dam 74, the holes of the power supply line The edge of the area, the edge of the first inorganic layer and the third inorganic layer, and the edge of the connecting electrode are covered, which can effectively prevent the peeling failure of the edge of the power line hole area, the edge of the first inorganic layer and the third inorganic layer, and the edge of the connecting electrode.
  • the second partition dam 75 may be formed on a side of the second partition structure close to the display area, and is a linear dam extending along the first edge 311 .
  • the second isolation dam 75 is arranged on the third inorganic layer 98 on the side of the second isolation structure close to the display area on the side away from the display area, and completely covers the second inorganic layer 97 and the third inorganic layer 98 on the side of the display area. edge.
  • the second isolation dam 75 is disposed on the connection electrode 72 at the side close to the display area, and completely covers the edge of the connection electrode 72 at the side away from the display area.
  • the second isolation dam 75 simultaneously covers the edge of the connecting electrode 72 away from the display area, and the edges of the second inorganic layer 97 and the third inorganic layer 98 near the display area.
  • the orthographic projection of the edge of the connection electrode 72 away from the display area on the substrate is within the range of the orthographic projection of the second barrier dam 75 on the substrate, and the second inorganic layer 97 and the third inorganic layer
  • the orthographic projection of the edge of 98 on the base near the side of the display area is within the range of the orthographic projection of the second partition dam 75 on the base.
  • the first edge 311 of the power supply line 310 is covered by the second isolation layer 70, and the edges of the second inorganic layer 97 and the third inorganic layer 98, and the edge of the connection electrode 72 are covered by the second isolation dam 75, so that the second isolation dam 75 of the power line
  • the first edge, the edge of the second inorganic layer, the edge of the third inorganic layer, and the edge of the connecting electrode are coated in sequence, which can effectively prevent the peeling failure of the first edge of the power line, the edge of the second inorganic layer, the third inorganic layer, and the edge of the connecting electrode .
  • Exemplary embodiments of the present disclosure form a covering structure of an isolation dam in the region where the edge of the power line is located, thereby effectively avoiding peeling of the edge of the film layer, especially the peeling of the edge of the power line.
  • the edge of the hole area and the first edge of the power line are covered by the isolation layer, and the edge of the inorganic layer and the edge of the connecting electrode are covered by the isolation dam, which can not only effectively prevent the edge of the power line, the edge of the inorganic layer and the connection
  • the peeling failure of the electrode edge, the stretchable edge structure is stable and reliable, avoiding the formation of water and oxygen transmission channels at the edge of the film layer, effectively ensuring the packaging effect of the display substrate, and by setting the inorganic layer without contact with the power line,
  • the inorganic layer is not in contact with the connecting electrodes, which can reduce the difficulty of the process and reduce the material residue caused by the difference in the film layer, effectively ensuring the process quality and improving the yield rate.
  • the preparation process of the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield.
  • the structure of the substrate shown in the exemplary embodiments of the present disclosure and the manufacturing process thereof are merely exemplary illustrations.
  • the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • a plurality of sequentially nested first partition structures may be arranged outside the hole area.
  • a plurality of second partition structures arranged in sequence may be provided on the side of the first edge away from the display area, which is not limited in this disclosure.
  • the present disclosure also provides a display device, including the display substrate of the foregoing embodiments.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

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Abstract

本公开提供了一种显示基板和显示装置。显示基板包括显示区域和位于所述显示区域至少一侧的边框区域，所述显示区域和边框区域包括至少一个拉伸孔；所述拉伸孔包括孔区和环绕所述拉伸孔的隔断区，所述隔断区设置有环绕所述孔区的第一隔断结构；所述第一隔断结构包括环绕所述孔区的第一隔断层和设置在所述第一隔断层上的第一无机层，所述第一隔断层上设置有环绕所述孔区的隔断槽，所述第一无机层上设置有环绕所述孔区的隔断孔，所述隔断孔和隔断槽连通；位于所述隔断孔周边的第一无机层相对于所述隔断槽的侧壁具有突出部，所述突出部和所述隔断槽的侧壁形成内陷结构。

Description

显示基板和显示装置
本申请要求于2021年6月17日提交中国专利局、申请号为202110671878.8、发明名称为“显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域和位于所述显示区域至少一侧的边框区域，所述显示区域和边框区域包括至少一个拉伸孔；所述拉伸孔包括孔区和环绕所述拉伸孔的隔断区，所述隔断区设置有环绕所述孔区的第一隔断结构；所述第一隔断结构包括环绕所述孔区的第一隔断层和设置在所述第一隔断层上的第一覆盖层，所述第一隔断层上设置有环绕所述孔区的隔断槽，所述第一覆盖层上设置有环绕所述孔区的隔断孔，所述隔断孔和隔断槽连通；位于所述隔断孔周边的第一覆盖层相对于所述隔断槽的侧壁具有突出部，所述突出部和所述隔断槽的侧壁形成内陷结构。
在示例性实施方式中，所述边框区域包括沿着远离所述显示区域方向依 次设置的电路区、电源线区和边缘区，所述电源线区包括至少一个拉伸孔；在垂直于所述基底的平面内，所述电源线区包括设置在基底上的至少一层绝缘层和设置在所述至少一层绝缘层上的电源线；所述第一隔断结构中的第一隔断层覆盖所述电源线靠近所述孔区一侧的孔区边缘。
在示例性实施方式中，所述第一覆盖层与所述电源线不直接接触。
在示例性实施方式中，所述第一隔断结构中远离所述孔区一侧的第一覆盖层搭设在所述电源线上。
在示例性实施方式中，所述电源线在所述显示基板平面上的正投影和所述第一覆盖层在所述显示基板平面上的正投影至多部分交叠。
在示例性实施方式中，在平行于所述基底的平面内，所述电源线的第一边缘和/或第二边缘为折线，所述第一边缘为所述电源线远离所述显示区域一侧的边缘，所述第二边缘为所述电源线靠近所述显示区域一侧的边缘。
在示例性实施方式中，所述第一边缘和/或第二边缘在所述显示基板平面上的正投影与所述拉伸孔在所述显示基板平面上的正投影不重叠。
在示例性实施方式中，所述第一边缘远离所述显示区域的一侧设置有第二隔断结构，所述第二隔断结构包括沿着所述第一边缘延伸的第二隔断层和设置在所述第二隔断层上的第二覆盖层，所述第二隔断层上设置有沿着所述第一边缘延伸的隔断槽，所述第二覆盖层上设置有沿着所述第一边缘延伸的隔断孔，所述隔断孔和隔断槽连通；位于所述隔断孔周边的第二覆盖层相对于所述隔断槽的侧壁具有突出部，所述突出部和所述隔断槽的侧壁形成内陷结构。
在示例性实施方式中，所述第二隔断结构中的第二隔断层覆盖所述电源线的第一边缘。
在示例性实施方式中，所述第二覆盖层与所述电源线不直接接触。
在示例性实施方式中，所述第二隔断结构中靠近所述显示区域一侧的第二覆盖层搭设在所述电源线上。
在示例性实施方式中，所述电源线区还包括连接电极和环绕所述孔区的 第一隔断坝，所述连接电极设置在所述电源线上，所述第一隔断坝设置在所述第一隔断结构远离所述孔区的一侧，所述第一隔断坝远离所述孔区的一侧覆盖所述连接电极靠近所述孔区一侧的边缘。
在示例性实施方式中，所述电源线区还包括连接电极和沿着所述第一边缘延伸的第二隔断坝，所述第二隔断坝设置在所述第二隔断结构靠近所述显示区域的一侧，所述第二隔断坝靠近显示区域的一侧覆盖所述连接电极靠近所述第一边缘一侧的边缘。
在示例性实施方式中，还包括设置在第一覆盖层和/或第二覆盖层上方的第三覆盖层，所述第三覆盖层至少覆盖所述第一覆盖层和/或第二覆盖层，以及所述隔断槽。
在示例性实施方式中，所述第一覆盖层远离所述孔区的边缘和第三覆盖层远离所述孔区的边缘基本齐平；和/或所述第二覆盖层远离所述孔区的边缘和第三覆盖层远离所述孔区的边缘基本齐平。
在示例性实施方式中，所述电源线区还包括连接电极，所述连接电极设置在所述电源线上，所述连接电极靠近所述孔区的一侧覆盖所述搭设所述电源线的所述第一覆盖层的边缘，所述连接电极靠近第一边缘的一侧覆盖所述搭设所述电源线的所述第一覆盖层的边缘。
在示例性实施方式中，所述电源线区还包括环绕所述孔区的第一隔断坝，所述第一隔断坝设置在所述第一隔断结构远离所述孔区的一侧，所述第一隔断坝靠近所述孔区的一侧设置在所述第一覆盖层上，所述第一隔断坝远离所述孔区的一侧覆盖所述连接电极靠近所述孔区一侧的边缘。
在示例性实施方式中，所述连接电极靠近所述孔区一侧的边缘在所述显示基板平面上的正投影位于所述第一隔断坝在所述显示基板平面上的正投影的范围之内，和/或，所述第一覆盖层远离所述孔区一侧的边缘在所述显示基板平面上的正投影位于所述第一隔断坝在所述显示基板平面上的正投影的范围之内。
在示例性实施方式中，所述电源线区还包括沿着所述第一边缘延伸的第二隔断坝，所述第二隔断坝设置在所述第二隔断结构靠近所述显示区域的一 侧，所述第二隔断坝远离所述显示区域的一侧设置在所述第二覆盖层上，所述第二隔断坝靠近显示区域的一侧覆盖所述连接电极靠近所述第一边缘一侧的边缘。
在示例性实施方式中，所述连接电极远离显示区域一侧的边缘在所述显示基板平面上的正投影位于所述第二隔断坝在所述显示基板平面上的正投影的范围之内，和/或，所述第二覆盖层靠近显示区域一侧的边缘在所述显示基板平面上的正投影位于所述第二隔断坝在所述显示基板平面上的正投影的范围之内。
在示例性实施方式中，所述连接电极在所述显示基板平面上的正投影和所述第一覆盖层在所述显示基板平面上的正投影至少具有第一部分交叠；所述连接电极在所述显示基板平面上的正投影和所述第二覆盖层在所述显示基板平面上的正投影至少具有第二部分交叠。
在示例性实施方式中，所述第一部分交叠位于第一隔断坝在所述显示基板平面上的正投影的范围之内，所述第二部分交叠位于第二隔断坝在所述显示基板平面上的正投影的范围之内。
在示例性实施方式中，所述电源线区还包括阴极，所述阴极设置在所述连接电极上，且包裹第一隔断坝和第二隔断坝。
在示例性实施方式中，所述显示区域包括设置在基底上的驱动电路层和设置在所述驱动电路层上的发光结构层；第一隔断层和第二隔断层与所述驱动电路层中的平坦层同层设置，第一隔断坝和第二隔断坝与所述发光结构层中的像素定义层同层设置。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是 示意说明本公开内容。
图1为一种显示基板的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示区域的平面结构示意图；
图4为一种OLED像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为一种显示基板中边框区域的平面结构示意图；
图7a和图7b为本公开示例性实施例一种显示基板的剖面结构示意图；
图8a至图8c为本公开实施例一种形成驱动结构层等图案后的示意图；
图9a至图9c为本公开实施例一种形成隔断层图案后的示意图；
图10a至图10f为本公开实施例一种形成隔断槽图案后的示意图；
图11a至图11c为本公开实施例一种形成连接电极图案后的示意图；
图12a至图12c为本公开实施例一种形成隔断坝图案后的示意图；
图13a至图13c为本公开实施例形成一种有机发光层图案后的示意图；
图14a至图14c为本公开实施例形成一种阴极图案后的示意图；
图15a至图15c为本公开实施例形成一种光学耦合层图案后的示意图；
图16a至图16c为本公开实施例形成一种封装层图案后的示意图；
图17a和图17b为本公开实施例另一种显示基板的剖面结构示意图；
图18a至图18b为本公开另一种形成隔断槽图案后的示意图；
图19a至图19b为本公开另一种形成第三无机层图案后的示意图；
图20a至图20b为本公开另一种形成连接电极图案后的示意图；
图21a至图21b为本公开另一种形成隔断坝图案后的示意图。
附图标记说明:
1—玻璃载板；     10—基底；      11—第一有源层；
12—第一栅电极；        13—第一源电极；        14—第一漏电极；
21—第二有源层；        22—第二栅电极；        23—第二源电极；
24—第二漏电极；        31—第一电容电极；      32—第三电容电极；
41—第二电容电极；      42—第四电容电极；      50—孔区；
51—隔断区；            60—第一隔断层；        61—隔断槽；
70—第二隔断层；        71—阳极；              72—连接电极；
73—像素定义层；        74—第一隔断坝；        75—第二隔断坝；
76—有机发光层；        77—阴极；              78—光学耦合层；
81—第一封装层；        82—第二封装层；        83—第三封装层；
91—第一绝缘层；        92—第二绝缘层；        93—第三绝缘层；
94—第四绝缘层；        95—平坦层；            96—第一无机层；
97—第二无机层；        98—第三无机层；        100—显示区域；
101—第一晶体管；       102—第一存储电容；     200—绑定区域；
201—第二晶体管；       202—第二存储电容；     300—边框区域；
301—电路区；           302—电源线区；         303—边缘区；
310—电源线；           311—第一边缘；         312—第二边缘；
313—孔区边缘；         500—拉伸孔。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产 生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij。每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2为一种显示基板的结构示意图。如图2所示，在示例性实施方式中，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边框区域300。显示区域100可以包括规则排列的多个子像素，子像素可以包括像素驱动电路和发光器件，绑定区域200可以包括将信号线连接至外部驱动装置的绑定电路，边框区域300可以包括栅极驱动电路和向多个子像素传输电压信号的第二电源线VSS。
目前，柔性OLED显示装置为单轴弯曲，屏幕变形量小，通过在显示基板上开设微孔的方式，可以提高显示基板的拉伸性能。柔性显示基板可以采用岛桥结构，岛桥结构是将发光器件设置在像素岛区，包括微孔的孔区设置在像素岛之间，连接线设置在像素岛之间以及孔区之间的连接桥区。施加外力拉伸显示基板时，形变主要发生在孔区和连接桥区，像素岛区的发光器件基本保持形状，可以保证像素岛区的发光器件不会受到破坏。
图3为一种显示区域的平面结构示意图。如图3所示，显示基板的显示区域可以包括以矩阵方式排布的多个像素岛，像素岛可以包括至少一个像素单元P，像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，子像素可以包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据 信号线传输的数据电压，向发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。在示例性实施方式中，第一子像素P1可以是红色(R)子像素，第二子像素P2可以是绿色(G)子像素，第三子像素P3可以是蓝色(B)子像素。在示例性实施方式中，像素单元P可以包括四个子像素，如红色子像素、绿色子像素、蓝色子像素和白色子像素。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个发光单元可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个发光单元可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
在示例性实施方式中，显示区域可以包括多个拉伸孔500，拉伸孔500设置在像素岛之间，拉伸孔500配置为增加显示基板的可变形量。在垂直于显示基板的平面上，拉伸孔500中的基底和结构膜层被全部去掉，形成通孔结构，或者，拉伸孔500中的基底和结构膜层被部分去掉，形成盲孔结构。在平行于显示基板的平面上，拉伸孔的形状可以包括如下任意一种或多种：“I”字形、“T”字形、“L”字形和“H”字形，本公开在此不做限定。
在示例性实施方式中，边框区域可以设置多个拉伸孔，边框区域中拉伸孔的设置方式与显示区域中拉伸孔的设置方式可以近似。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T2C等结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(第一扫描信号线S1、第二扫描信号线S2、发光信号线E、数据信号线D、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的 第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电 荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线 S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
在示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括设置在基底上的驱动结构层、设置在驱动结构层上的发光结构层以及设置在发光元件上的封装层，驱动结构层包括像素驱动电路，发光结构层包括发光器件，发光器件与像素驱动电路连接。
图6为一种显示基板中边框区域的平面结构示意图，为图2中E区域的放大图。如图6所示，在平行于显示基板的平面内，边框区域300可以包括沿着远离显示区域的方向依次设置的电路区301、电源线区302和边缘区303。在示例性实施方式中，电路区301可以包括栅极驱动电路(Gate Driver on Array，简称GOA)，栅极驱动电路与显示区域中多个子像素的第一扫描线和第二扫描线连接。电源线区302可以包括电源线310，电源线310与显示区域中多个子像素的第二电源线VSS连接。边缘区303可以包括裂缝坝和切割槽，裂缝坝包括在复合绝缘层上设置的多个裂缝，多个裂缝配置为在切割过程中减小显示区域和电路区的受力，避免影响显示区域和电路区的膜层结构，截断裂缝向显示区域和电路区方向传递。切割槽包括在复合绝缘层上设置的凹槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。在示例性实施方式中，电路区301和电源线区302可以不交叠，或者可以存在部分交叠，本公开在此不做限定。
在示例性实施方式中，显示区域多个子像素中像素驱动电路所需的低电压从绑定区域的绑定焊盘引入，经过绑定区域后进入边框区域，通过边框区域环形的电源线输送给每个像素驱动电路的第二电源线VSS。由于电源线存在一定的阻抗，电压信号传输存在压降，因此电源线的宽度较大，以提高显示亮度均一性。
在示例性实施方式中，电路区301、电源线区302和边缘区303中均可以设置多个拉伸孔500。每个区的多个拉伸孔500可以包括第一方向拉伸孔和第二方向拉伸孔，第一方向拉伸孔是沿着第一方向X延伸的条形状孔，第 二方向拉伸孔是沿着第二方向Y延伸的条形状孔，第一方向X与第二方向Y交叉。在示例性实施方式中，在第一方向X，第一方向拉伸孔和第二方向拉伸孔交替设置，第一方向拉伸孔设置在两个第二方向拉伸孔之间，或者，第二方向拉伸孔设置在两个第一方向拉伸孔之间。在第二方向Y，第一方向拉伸孔和第二方向拉伸孔交替设置，第一方向拉伸孔设置在两个第二方向拉伸孔之间，或者，第二方向拉伸孔设置在两个第一方向拉伸孔之间。
在示例性实施方式中，电源线区302的电源线310具有折线状的第一边缘311和/或折线状的第二边缘312，第一边缘311为电源线310远离显示区域一侧的边缘，第二边缘312为电源线310靠近显示区域一侧的边缘。在示例性实施方式中，第一边缘311和/或第二边缘312在显示基板平面上的正投影与拉伸孔500在显示基板平面上的正投影没有重叠。
在示例性实施方式中，第一边缘可以包括多个第一直线和多个第一折线，第一直线和第一折线交替设置且相互连接，形成折线状的第一边缘。第二边缘可以包括多个第二直线和多个第二折线，第二直线和第二折线交替设置且相互连接，形成折线状的第二边缘。
在示例性实施方式中，第一直线和第二直线可以与第二方向Y平行，第一折线是相对于第一直线向着远离显示区域的方向凸出的折线或者向着靠近显示区域的方向凹进的折线，第二折线是相对于第二直线向着远离显示区域的方向凸出的折线或者向着靠近显示区域的方向凹进的折线。
在示例性实施方式中，第一折线或第二折线可以包括依次连接的第一线段、第二线段和第三线段，第一线段可以相对于第一直线或第二直线偏转第一角度，第三线段可以相对于第一直线或第二直线偏转第二角度。
在示例性实施方式中，第二线段可以与第二方向Y平行，第一线段和第三线段可以相对于第二线段的中心线对称设置，第二线段的中心线是沿着第一方向X延伸且平分第二线段的直线。
在示例性实施方式中，第一方向拉伸孔和第二方向拉伸孔可以分别设置在第一直线的两侧，第一方向拉伸孔和第二方向拉伸孔可以分别设置在第二线段的两侧。例如，以第一折线相对于第一直线向着远离显示区域的方向凸 出的折线为例，一个第一方向拉伸孔设置在第一直线远离显示区域的一侧，另一个第二方向拉伸孔设置在第一直线靠近显示区域的一侧。一个第二方向拉伸孔设置在第二线段远离显示区域的一侧，另一个第一方向拉伸孔设置在第二线段靠近显示区域的一侧。
本公开示例性实施例通过将电源线310的第一边缘311和/或第二边缘312设置成折线状，第一边缘311和/或第二边缘312在显示基板平面上的正投影与拉伸孔500在显示基板平面上的正投影没有重叠，电源线边缘避开拉伸孔，不仅可以使得电源线边缘不会应影响到拉伸孔的应力分布，而且可以有效避免因拉伸孔拉伸变形导致的电源线边缘剥离，进而防止因电源线边缘剥离形成水氧通道导致的封装失效。
图7a和图7b为本公开示例性实施例一种显示基板的剖面结构示意图，图7a示意了电路区301和电源线区302交界处的剖面结构，为图6中B-B向的剖视图，图7b示意了电源线区302和边缘区303交界处的剖面结构，为图6中C-C向的剖视图。在示例性实施方式中，拉伸孔可以包括孔区50和环绕孔区50的隔断区51，隔断区51设置有环绕孔区50的第一隔断结构。在垂直于显示基板的平面内，第一隔断结构包括环绕孔区50的第一隔断层60和设置在第一隔断层60上的第一无机层96，第一隔断层60上设置有环绕孔区50的隔断槽61，第一无机层96上设置有环绕孔区50的隔断孔，隔断孔和隔断槽连通。位于隔断孔周边的第一无机层96相对于隔断槽61的侧壁具有突出部，突出部和隔断槽的侧壁形成内陷结构。
在示例性实施方式中，第一无机层作为本公开的第一覆盖层。在一些可能的示例性实施方式中，第一覆盖层可以采用金属材料，或者采用与第一隔断层(有机材料)具有不同刻蚀速率的其它材料，本公开在此不做限定。
在垂直于基底的平面内，电源线区302可以包括设置在基底10上的复合绝缘层和设置在复合绝缘层上的电源线310。在示例性实施方式中，复合绝缘层可以包括叠设的第一绝缘层91、第二绝缘层91、第三绝缘层93和第四绝缘层94。
在示例性实施方式中，第一隔断结构中的第一隔断层60覆盖电源线310靠近孔区50一侧的孔区边缘313，第一隔断结构中远离孔区50一侧的第一 无机层96搭设在电源线310上。
在示例性实施方式中，电源线区302可以包括连接电极72，连接电极72设置在电源线310远离基底的一侧，通过搭接方式与电源线310连接。连接电极72靠近孔区50的一侧覆盖第一无机层96的边缘，该第一无机层96是第一隔断结构中搭设在电源线310上的第一无机层96，该边缘是第一无机层96远离孔区50一侧的边缘。
在示例性实施方式中，电源线区302可以包括第一隔断坝74，第一隔断坝74为环绕孔区50的环形体，设置在第一隔断结构远离孔区50的一侧。第一隔断坝74靠近孔区50的一侧设置在第一无机层96上，该第一无机层96是第一隔断结构中搭设在电源线310上的第一无机层96，第一隔断坝74远离孔区50的一侧覆盖连接电极72靠近孔区50一侧的边缘。
在示例性实施方式中，电源线区302可以包括阴极77，阴极77设置在连接电极72远离基底的一侧，通过搭接方式与连接电极72连接，且阴极77包裹第一隔断坝74，即阴极77覆盖第一隔断坝74暴露出的全部表面。
在示例性实施方式中，电源线310的第一边缘311远离显示区域的一侧可以设置第二隔断结构，第二隔断结构包括沿着第一边缘311延伸的第二隔断层70和设置在第二隔断层70上的第二无机层97，第二隔断层70上设置有沿着第一边缘311延伸的隔断槽61，第二无机层97上设置有沿着第一边缘311延伸的隔断孔，隔断孔和隔断槽连通。位于隔断孔周边的第二无机层97相对于隔断槽61的侧壁具有突出部，突出部和隔断槽的侧壁形成内陷结构。
在示例性实施方式中，第二无机层97作为本公开的第二覆盖层。在一些可能的示例性实施方式中，第二覆盖层可以采用金属材料，或者采用与第二隔断层(有机材料)具有不同刻蚀速率的其它材料，本公开在此不做限定。
在示例性实施方式中，第二隔断结构中的第二隔断层70覆盖电源线310的第一边缘311，第二隔断结构中靠近显示区域一侧的第二无机层97搭设在电源线310上。
在示例性实施方式中，连接电极72靠近第一边缘311的一侧覆盖第二无 机层97的边缘，该第二无机层97是第二隔断结构中搭设在电源线310上的第二无机层97，该边缘是第二无机层97靠近显示区域一侧的边缘。
在示例性实施方式中，电源线区302可以包括第二隔断坝75，第二隔断坝75是沿着第一边缘311延伸的线形体，设置在所述第二隔断结构靠近显示区域的一侧，第二隔断坝75远离显示区域的一侧设置在第二无机层97上，该第二无机层97是第二隔断结构中搭设在电源线310上的第二无机层97，第二隔断坝75靠近显示区域的一侧覆盖连接电极72靠近第一边缘311一侧的边缘。
在示例性实施方式中，阴极77包裹第二隔断坝75，即阴极77覆盖第二隔断坝75暴露出的全部表面。
在示例性实施方式中，在垂直于显示基板的平面内，孔区50的内壁包括基底段、有机材料段和无机材料段。
在示例性实施方式中，显示区域可以包括设置在基底上的驱动电路层和设置在驱动电路层上的发光结构层。第一隔断层60和第二隔断层70可以与驱动电路层中的平坦层同层设置，第一隔断坝74和第二隔断坝75可以与发光结构层中的像素定义层同层设置。
在示例性实施方式中，第一无机层和第二无机层同层设置，且与所述显示区域中的一个绝缘层同层设置。
在示例性实施方式中，第一无机层和/或第二无机层上方还设置有第三无机层，所述第三无机层覆盖第一隔断结构和/或第二隔断结构。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在 整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，本公开示例性实施例一种显示基板的制备过程可以包括如下操作。
(11)在玻璃载板上制备基底。在示例性实施方式中，基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层。第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一无机材料层和第二无机材料层可以称为阻挡(Barrier)层或缓冲(Buffer)层。在示例性实施方式中，以叠层结构PI1/Barrier1/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。在示例性实施方式中，第一阻挡层和第二无机材料层之间可以设置非晶硅(a-si)层，基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。在示例性实施方式中，形成第一阻挡层过程中，可以通过图案化工艺在第一阻挡层上形成无机孔，无机孔的位置可以与后续形成的通孔的位置相对应。本次工艺后，显示区域、电路区301、电源线区302和边缘区303均包括基底。
(12)在基底10上制备显示区域的驱动结构层、电路区的电路结构层、 电源线区的电源结构层和边缘区的边缘结构层图案。在示例性实施方式中，显示区域的驱动结构层可以包括构成像素驱动电路的第一晶体管101和第一存储电容102，电路区301的电路结构层可以包括构成栅极驱动电路的第二晶体管201和第二存储电容202，电源线区302的电源结构层可以包括设置在基底上的复合绝缘层和设置在复合绝缘层上的电源线310，边缘区303的边缘结构层可以包括复合绝缘层。在示例性实施方式中，复合绝缘层可以包括多个叠设的无机绝缘层。
在示例性实施方式中，制备显示区域的驱动结构层、电路区的电路结构层、电源线区的电源结构层和边缘区的边缘结构层图案的过程可以包括：
在基底10上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，在基底10上形成第一绝缘层91，以及设置在第一绝缘层91上的半导体层图案，半导体层图案至少包括位于显示区域的第一有源层11和位于电路区301的第二有源层21。本次工艺后，电源线区302和边缘区303的半导体薄膜被刻蚀掉，电源线区302和边缘区303包括设置在玻璃载板1上的基底10，以及设置在基底10上的第一绝缘层91。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层92，以及设置在第二绝缘层92上的第一金属层图案，第一金属层图案至少包括位于显示区域的第一栅电极12和第一电容电极31，以及位于电路区301的第二栅电极22和第二电容电极41。本次工艺后，电源线区302和边缘区303的第一金属薄膜被刻蚀掉，电源线区302和边缘区303包括基底10，以及在基底10上叠设的第一绝缘层91和第二绝缘层92。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一金属层图案的第三绝缘层93，以及设置在第三绝缘层93上的第二金属层图案，第二金属层图案至少包括位于显示区域的第三电容电极32和位于电路区301的第四电容电极42，第三电容电极32的位置与第一电容电极31的位置相对应，第四电容电极42的位置与第二电容电极41的位置相对应。本次工艺后，电源线区302和边缘区303的第二金属薄膜被刻蚀掉，电源线区302和边缘区303包括基底10，以及在基底10 上叠设的第一绝缘层91、第二绝缘层92和第三绝缘层93。
随后，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二金属层图案的第四绝缘层94，第四绝缘层94上开设有多个过孔和多个通孔。多个过孔可以包括位于显示区域的第一有源过孔和位于电路区301的第二有源过孔，第一有源过孔和第二有源过孔内的第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，第一有源过孔暴露出第一有源层11两端的源极区域和漏极区域，第二有源过孔暴露出第二有源层21两端的源极区域和漏极区域。多个通孔分别位于显示区域、电路区301、电源线区302和边缘区303，多个通孔(孔区50)内的第四绝缘层94、第三绝缘层93、第二绝缘层92、第一绝缘层91和基底10被去掉，暴露出玻璃衬底1的表面。本次工艺后，电源线区302和边缘区303包括基底10，以及设置在基底10上的复合绝缘层，通孔贯通基底10和复合绝缘层，复合绝缘层包括叠设的第一绝缘层91、第二绝缘层92、第三绝缘层93和第四绝缘层94。
随后，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层94上形成第三金属层图案，第三金属层图案至少包括：位于显示区域的第一源电极13和第一漏电极14，位于电路区301的第二源电极23和第二漏电极24，以及位于电源线区302的电源线310，如图8a、图8b和图8c所示，图8a示意了显示区域中像素岛和拉伸孔的剖面结构，为图3中A-A向的剖视图，图8b为图6中B-B向的剖视图，图8c为图6中C-C向的剖视图。
至此，制备完成驱动结构层、电路结构层、电源结构层和边缘结构层图案。在示例性实施方式中，第一有源层11、第一栅电极12、第一源电极13和第一漏电极14组成像素驱动电路的第一晶体管101，第二有源层21、第二栅电极22、第二源电极23和第二漏电极24组成栅极驱动电路的第二晶体管201，第一电容电极31和第三电容电极32组成像素驱动电路的第一存储电容102，第二电容电极41和第四电容电极42组成栅极驱动电路的第二存储电容202。在示例性实施方式中，第一晶体管101可以是像素驱动电路中的驱动晶体管，第二晶体管201可以是栅极驱动电路中的开关晶体管。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝 缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲层，第二绝缘层和第三绝缘层可以称为(GI)层，第四绝缘层可以称为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在示例性实施方式中，拉伸孔可以包括孔区(即通孔)50和环绕孔区50的隔断区51。在显示区域、电路区301和边缘区303，孔区50暴露出玻璃衬底1的表面，隔断区51暴露出第四绝缘层94的表面。在电源线区302，孔区50暴露出玻璃衬底1的表面，隔断区51靠近孔区50的区域暴露出第四绝缘层94的表面，隔断区51远离孔区50的区域暴露出电源线310的表面。
在示例性实施方式中，由于通孔刻蚀中包括刻蚀无机材料层和有机材料层，而刻蚀有机材料的刻蚀速率大于刻蚀无机材料的刻蚀速率，因而使得通孔的侧壁形成台阶，基底上的基底通孔的孔径相对于复合绝缘层上的绝缘通孔外扩一段距离。靠近基底通孔一侧的绝缘通孔周边的复合绝缘层相对于靠近绝缘通孔一侧的基底通孔的侧壁具有突出部，突出部和基底通孔的侧壁形成内陷结构，即孔区内壁中的复合绝缘层具有凸出基底的“屋檐”结构。
在示例性实施方式中，基底通孔的孔径大于绝缘通孔的孔径，(靠近基底通孔一侧的)绝缘通孔的轮廓在玻璃衬底上的正投影位于(靠近绝缘通孔一侧的)基底通孔的轮廓在玻璃衬底上的正投影的范围之内。
(13)形成平坦层和隔断层图案。在示例性实施方式中，形成平坦层和隔断层图案可以包括：在形成前述图案的基底上涂覆平坦薄膜，通过图案化工艺对平坦薄膜进行图案化，形成平坦层95、第一隔断层60和第二隔断层70图案，如图9a、图9b和图9c所示，图9a为图3中A-A向的剖视图，图 9b为图6中B-B向的剖视图，图9c为图6中C-C向的剖视图。在示例性实施方式中，平坦薄膜可以采用有机材料，如树脂等。
在示例性实施方式中，平坦层95形成在显示区域和电路区301。显示区域的平坦层95上开设有阳极过孔，阳极过孔内的平坦薄膜被去掉，暴露出第一晶体管101的第一漏电极的表面，阳极过孔配置为使后续形成的阳极通过该过孔与第一晶体管101连接。在示例性实施方式中，显示区域中驱动结构层包括平坦层95。电路区301的平坦层95向着远离显示区域的方向延伸到电源线区302，并覆盖电源线310靠近显示区域一侧的第二边缘312。
在示例性实施方式中，第一隔断层60形成在显示区域、电路区301、电源线区302和边缘区303中各个孔区50的周围，为环绕孔区50的环形状。第二隔断层70形成在电源线310的第一边缘311远离显示区域的一侧，为沿着第一边缘311延伸的折线状。
在示例性实施方式中，在显示区域和电路区301，环形状第一隔断层60靠近孔区50一侧的平坦薄膜被去掉，形成第一开口K1，第一开口K1暴露出孔区50以及孔区50附近的第四绝缘层94的表面，第一隔断层60远离孔区50一侧的平坦薄膜被去掉，在第一隔断层60与平坦层95之间形成环形状的第二开口K2，第二开口K2暴露出第四绝缘层94的表面。
在示例性实施方式中，在电源线区302，环形状第一隔断层60靠近孔区50一侧的平坦薄膜被去掉，形成第一开口K1，第一隔断层60远离孔区50一侧的平坦薄膜被去掉，形成第三开口K3，第三开口K3暴露出电源线310的表面，第三开口K3配置为使后续形成的连接电极通过该开口与电源线310连接。第一隔断层60远离孔区50的一侧覆盖电源线310的孔区边缘313，孔区边缘313是电源线区302中电源线310靠近孔区50一侧的边缘。
在示例性实施方式中，第一隔断层60覆盖电源线310的第一宽度L1可以大于或等于2μm，即第一隔断层60远离孔区50一侧的边缘与电源线310的孔区边缘313之间的距离可以大于或等于2μm，使得电源线的孔区边缘被第一隔断层60完整包覆，防止电源线孔区边缘的剥离失效。
在示例性实施方式中，在电源线区302的第一边缘311，折线状第二隔 断层70靠近显示区域一侧的平坦薄膜被去掉，形成第三开口K3，第三开口K3暴露出电源线310的表面，且第二隔断层70靠近显示区域的一侧覆盖电源线310的第一边缘311，第二隔断层70远离显示区域一侧的平坦薄膜被去掉。
在示例性实施方式中，第二隔断层70覆盖电源线310的第一宽度L1可以大于或等于2μm，即第二隔断层70靠近显示区域一侧的边缘与电源线310的第一边缘311之间的距离可以大于或等于2μm，使得电源线的第一边缘被第二隔断层70完整包覆，防止电源线第一边缘的剥离失效。
在示例性实施方式中，在边缘区303，环形状第一隔断层60靠近孔区50一侧的平坦薄膜被去掉，形成第一开口K1，远离孔区50一侧的平坦薄膜被去掉，在第一隔断层60与第二隔断层70之间以及相邻的第一隔断层60之间形成第二开口K2。
在示例性实施方式中，在垂直于基底的平面内，第一隔断层60和第二隔断层70的剖面形状可以为梯形状，隔断层远离基底一侧的宽度小于隔断层靠近基底一侧的宽度。
本次工艺后，电源线区302中电源线310的边缘均被覆盖，电源线310远离显示区域一侧的第一边缘311被第二隔断层70覆盖，电源线310靠近显示区域一侧的第二边缘312被平坦层95覆盖，电源线310上拉伸孔的孔区边缘313被第一隔断层60覆盖。边缘区303包括基底10、设置在基底10上的复合绝缘层和设置在复合绝缘层上的第一隔断层60，边缘区303设置有多个贯通基底10和复合绝缘层的孔区50，第一隔断层60为环绕孔区50的环形状。
(14)形成隔断槽图案。在示例性实施方式中，形成隔断槽图案可以包括：在形成前述图案的基底上沉积无机材料薄膜，通过图案化工艺对无机材料薄膜进行图案化，形成覆盖第一隔断层60表面的第一无机层96、覆盖第二隔断层70表面的第二无机层97以及设置在第一隔断层60和第二隔断层70上的隔断槽61，如图10a、图10b和图10c所示，图10a为图3中A-A向的剖视图，图10b为图6中B-B向的剖视图，图10c为图6中C-C向的剖视图。在示例性实施方式中，无机材料薄膜可以采用硅氧化物(SiOx)、硅氮 化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
在示例性实施方式中，形成第一无机层、第二无机层和隔断槽的过程可以包括：在形成前述图案的基底上沉积无机材料薄膜，无机材料薄膜完全覆盖第一隔断层60和第二隔断层70的上表面和侧表面，上表面是指梯形状隔断层远离基底一侧的表面，侧表面是梯形状隔断层斜边的表面。然后在无机材料薄膜上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影后形成完全曝光区域和未曝光区域，完全曝光区域的光刻胶被去除，未曝光区域的光刻胶被保留。然后采用刻蚀工艺对完全曝光区域的无机材料薄膜进行刻蚀，形成完整包裹第一隔断层60外表面的第一无机层96、完整包裹第二隔断层70外表面的第二无机层97以及分别设置在第一无机层96和第二无机层97上的隔断孔，隔断孔分别位于第一隔断层60和第二隔断层70的上表面所在位置，隔断孔分别暴露出第一隔断层60和第二隔断层70的部分上表面。随后，对隔断孔内暴露出的第一隔断层60和第二隔断层70继续刻蚀，分别在第一隔断层60和第二隔断层70上形成的隔断槽，隔断孔和隔断槽相互连通。
在示例性实施方式中，可以采用干法刻蚀工艺进行刻蚀，且采用有机/无机刻蚀比较大的气体，如O 2、CF 4、CHF 3等。由于有机/无机刻蚀比较大，即刻蚀有机材料的刻蚀速率大于刻蚀无机材料的刻蚀速率，因而在刻蚀有机材料的第一隔断层60和第二隔断层70时，隔断层存在横向刻蚀，隔断层上的隔断槽相对于隔断孔外扩一段距离，形成具有侧蚀结构的隔断槽61。
在示例性实施方式中，位于隔断孔周边的第一无机层和第二无机层相对于隔断槽的侧壁具有突出部，突出部和隔断槽(靠近隔断孔一侧的)的侧壁形成内陷结构。
在示例性实施方式中，在垂直于基底的平面内，隔断槽的截面形状为倒梯形状，隔断槽远离基底一侧上开口的宽度大于隔断槽靠近基底一侧下开口的宽度。在示例性实施方式中，倒梯形状隔断槽的侧边可以为弧形。
在示例性实施方式中，隔断槽下开口远离孔区一侧应保证不漏出电源线310的孔区边缘313，且下开口远离孔区的一侧与电源线的孔区边缘之间的第二宽度L2可以大于或等于1μm，使得电源线的孔区边缘被第一隔断层完整 包覆，防止电源线孔区边缘的剥离失效。
在示例性实施方式中，隔断槽下开口靠近显示区域一侧应保证不漏出电源线310的第一边缘311，且下开口靠近显示区域的一侧与第一边缘之间的第二宽度L2可以大于或等于1μm，使得电源线的第一边缘被第二隔断层完整包覆，防止电源线第一边缘的剥离失效。
在示例性实施方式中，隔断孔的孔径小于隔断槽上开口的孔径，隔断孔在基底上的正投影位于隔断槽上开口在基底上的正投影的范围之内。包裹第一隔断层60外表面的第一无机层96和包裹第二隔断层70外表面的第二无机层97具有凸出隔断槽61上开口的边缘，形成一个“屋檐”结构，隔断槽61上开口的轮廓线在基底上的正投影位于第一无机层96和第二无机层97在基底上的正投影的范围之内。本公开中，通过设置带有“屋檐”结构的隔断槽61，可以有效隔断后续蒸镀的有机发光层、阴极和光学耦合层，有效阻断来自孔区的水氧入侵。
在示例性实施方式中，第一无机层96和第二无机层97具有凸出隔断槽上开口边缘的宽度可以约为1μm至3μm，即隔断槽相对于隔断孔外扩1μm至3μm。
在示例性实施方式中，第一隔断层60、覆盖第一隔断层60外表面的第一无机层96、设置在第一无机层96上的隔断孔以及设置在第一隔断层60上的隔断槽61组成第一隔断结构，第一隔断结构形成在环绕孔区50的隔断区51，为环绕孔区50的环形隔断结构。
在示例性实施方式中，第二隔断层70、覆盖第二隔断层70的第二无机层97、设置在第二无机层97上的隔断孔以及设置在第二隔断层70上的隔断槽61组成第二隔断结构，第二隔断结构形成在第一边缘311远离显示区域的一侧，为沿着第一边缘311延伸的线形隔断结构。
在示例性实施方式中，在电源线区302的第三开口K3内，第一隔断结构中远离孔区一侧的第一无机层96搭设在电源线310上，第二隔断结构中靠近显示区域一侧的第二无机层97搭设在电源线310上。
在示例性实施方式中，第一无机层96和第二无机层97搭设在电源线310 的第三宽度L3可以大于或等于2μm，提高电源线310与第一隔断层的第一无机层96和第二隔断层的第二无机层97之间的搭接效果。
由于电源线310的孔区边缘313被第一隔断层60覆盖，而第一无机层96覆盖第一隔断层60和电源线310交界的区域，使得电源线的孔区边缘被双层包覆，可以有效防止电源线孔区边缘的剥离失效。由于电源线310的第一边缘311被第二隔断层70覆盖，而靠近显示区域一侧的第二无机层97覆盖第二隔断层70和电源线310交界的区域，使得第一边缘被双层包覆，可以有效防止电源线第一边缘的剥离失效。
在示例性实施方式中，第一隔断结构和第二隔断结构可以包括第三无机层。形成第三无机层图案可以包括：在形成前述图案的基底上沉积无机材料薄膜，通过图案化工艺对无机材料薄膜进行图案化，形成覆盖第一无机层96、第二无机层97以及隔断槽61的第三无机层98，如图10d、图10e和图10f所示，图10d为图3中A-A向的剖视图，图10e为图6中B-B向的剖视图，图10f为图6中C-C向的剖视图。
在示例性实施方式中，第三无机层98作为本公开的第三覆盖层。在一些可能的示例性实施方式中，第三覆盖层可以采用金属材料，本公开在此不做限定。
在示例性实施方式中，在显示区域、电路区310、电源线区302和边缘区303，第三无机层98覆盖第一无机层96和第二无机层97，并覆盖隔断槽61的内壁，包括覆盖隔断槽61的侧壁表面和底部表面。第三无机层98对隔断槽内壁的完整包裹保证了隔断结构的完整性，可以保证隔断结构的隔断效果。
在示例性实施方式中，第三无机层98可以只覆盖第一隔断结构的第一无机层和隔断槽，或者，第三无机层98可以只覆盖第二隔断结构的第二无机层和隔断槽，或者，第三无机层98可以同时覆盖第一隔断结构的第一无机层、第二隔断结构的第二无机层以及隔断槽。
本次工艺后，边缘区303包括基底10、设置在基底10上的复合绝缘层和设置在复合绝缘层上的第一隔断结构，边缘区303设置有多个贯通基底10 和复合绝缘层的孔区50，第一隔断结构为环绕孔区50的环形状。
(15)形成阳极和连接电极图案。在示例性实施方式中，形成阳极和连接电极图案可以包括：在形成前述图案的基底上沉积导电薄膜，通过图案化工艺对导电薄膜进行图案化，形成阳极71和连接电极72图案，如图11a、图11b和图11c所示，图11a为图3中A-A向的剖视图，图11b为图6中B-B向的剖视图，图11c为图6中C-C向的剖视图。
在示例性实施方式中，阳极71位于显示区域的平坦层95上，阳极71通过阳极过孔与第一晶体管101的第一漏电极连接。连接电极72位于电源线区302的第三开口K3内，且与第三开口K3暴露出的电源线310搭接，实现连接电极72与电源线310的连接。在示例性实施方式中，连接电极72配置为与后续形成的阴极连接，实现阴极通过连接电极72与电源线310的可靠连接。
在示例性实施方式中，在电源线区302的第三开口K3内，连接电极72在显示基板平面上的正投影和第一无机层96在显示基板平面上的正投影至少具有部分交叠。连接电极72靠近孔区50的一侧覆盖第一无机层96的边缘，该第一无机层96是搭设在电源线310上的第一无机层96，该边缘是第一无机层96远离孔区50的边缘。由于电源线310的孔区边缘313被第一隔断层60覆盖，第一无机层96覆盖第一隔断层60，而第一无机层96的边缘被连接电极72覆盖，使得电源线的孔区边缘和第一无机层边缘被依次包覆，所形成的多重包覆可以有效防止电源线孔区边缘和第一隔断结构外侧边缘的剥离失效。
在示例性实施方式中，在电源线区302的第三开口K3内，连接电极72在显示基板平面上的正投影和第二无机层97在显示基板平面上的正投影至少具有部分交叠。连接电极72远离显示区域的一侧覆盖第二无机层97的边缘，该第二无机层97是搭设在电源线310上的第二无机层97，该边缘是第二无机层97靠近显示区域的边缘。由于电源线310的第一边缘311被第二隔断层70覆盖，第二无机层97覆盖第二隔断层70，而第二无机层97的边缘被连接电极72覆盖，使得电源线的第一边缘和第二无机层边缘被依次包覆，所形成的多重包覆可以有效防止电源线的第一边缘和第二隔断结构外侧边缘 的剥离失效。
在示例性实施方式中，连接电极72覆盖第一无机层96和第二无机层97的第四宽度L4可以根据实际需要设计，第四宽度L4可以大于0，但小于第三宽度L3。例如，第四宽度L4可以约为第三宽度L3的四分之一至二分之一。
在示例性实施方式中，导电薄膜可以采用金属材料或者透明导电材料，金属材料可以包括银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，透明导电材料可以包括氧化铟锡(ITO)或氧化铟锌(IZO)。在示例性实施方式中，导电薄膜可以是单层结构，或者是多层复合结构，如ITO/Al/ITO等。
(16)形成像素定义层和隔断坝图案。在示例性实施方式中，形成像素定义层和隔断坝图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层73、第一隔断坝74和第二隔断坝75图案，如图12a、图12b和图12c所示，图12a为图3中A-A向的剖视图，图12b为图6中B-B向的剖视图，图12c为图6中C-C向的剖视图。
在示例性实施方式中，像素定义层73形成在显示区域，其上开设有像素开口，像素开口内的像素定义层被去掉，暴露出阳极71的表面。在示例性实施方式中，可以在形成像素定义层时形成隔垫柱图案，隔垫柱配置为在后续蒸镀工艺中支撑掩膜板(Mask)。在示例性实施方式中，隔垫柱可以设置在像素开口的外侧，像素定义层和隔垫柱图案可以通过半色调掩膜版(Half Tone Mask)通过同一次图案化工艺形成，本公开在此不做限定。
在示例性实施方式中，第一隔断坝74可以形成在第一隔断结构远离孔区50的外侧，为环绕第一隔断结构的环形坝体。第一隔断坝74靠近孔区50的一侧设置在第一隔断结构远离孔区50一侧的第一无机层96上，第一隔断坝74远离孔区50的一侧设置在连接电极72上，且完全覆盖连接电极72靠近孔区50一侧的边缘。在示例性实施方式中，第一隔断坝74覆盖连接电极72的第五宽度L5可以大于或等于1μm，即第一隔断坝74远离孔区一侧的边缘与连接电极72靠近孔区一侧的边缘之间的距离大于或等于1μm，使得连接 电极的边缘被第一隔断坝74完整包覆，防止连接电极边缘的剥离失效。通过第五宽度L5的设置，可以使得第一隔断坝74覆盖住连接电极72靠近孔区一侧的边缘，或者覆盖住第一无机层96远离孔区一侧的边缘，或者同时覆盖住连接电极72靠近孔区一侧的边缘和第一无机层96远离孔区一侧的边缘。在示例性实施方式中，连接电极72靠近孔区一侧的边缘在基底上的正投影位于第一隔断坝74在基底上的正投影的范围之内，或者，第一无机层96远离孔区一侧的边缘在基底上的正投影位于第一隔断坝74在基底上的正投影的范围之内，或者，连接电极72靠近孔区一侧的边缘在基底上的正投影和第一无机层96远离孔区一侧的边缘在基底上的正投影均位于第一隔断坝74在基底上的正投影的范围之内。在连接电极72在基底上的正投影和第一无机层96在基底上的正投影至少具有部分交叠时，该部分交叠位于第一隔断坝74在基底上的正投影的范围之内。由于电源线310的孔区边缘313被第一隔断层60覆盖，第一无机层96覆盖第一隔断层60，第一无机层96的边缘被连接电极72覆盖，而连接电极72的边缘被第一隔断坝74覆盖，使得电源线的孔区边缘、第一无机层边缘和连接电极边缘被依次包覆，所形成的多重包覆可以有效防止电源线孔区边缘、第一无机层边缘和连接电极边缘的剥离失效。
在示例性实施方式中，第一隔断坝可以设置在电源线区中，实现对膜层边缘的多重包覆。在一些可能的示例性实施方式中，第一隔断坝可以设置在显示区域、电路区、电源线区和边缘区中，在实现对电源线区膜层边缘多重包覆的同时，提高显示区域、电路区和边缘区中第一隔断结构的隔断效果。
在示例性实施方式中，第一隔断坝可以设置在隔断槽远离孔区的一侧，此时，在靠近孔区的内侧和远离孔区的外侧，包括第一隔断坝的第一隔断结构具有不同的高度。远离孔区外侧的第一隔断结构的顶部表面(第一隔断坝远离基底的一侧的表面)与基底之间的距离大于靠近孔区内侧的第一隔断结构的顶部表面(第一无机层远离基底的一侧的表面)与基底之间的距离。
在示例性实施方式中，第一隔断坝可以同时设置在隔断槽靠近孔区的一侧和远离孔区的一侧，形成环绕孔区50的二个环形坝体。
在示例性实施方式中，第二隔断坝75可以形成在第二隔断结构靠近显示区域的一侧，为沿着第一边缘311延伸的线形坝体。第二隔断坝75远离显示 区域的一侧设置在第二隔断结构靠近显示区域一侧的第二无机层97上，第二隔断坝75靠近显示区域的一侧设置在连接电极72上，且完全覆盖连接电极72远离显示区域一侧的边缘。在示例性实施方式中，第二隔断坝75覆盖连接电极72的第五宽度L5可以大于或等于1μm，即第二隔断坝75靠近显示区域一侧的边缘与连接电极72远离显示区域一侧的边缘之间的距离大于或等于1μm，使得连接电极的边缘被第二隔断坝75完整包覆，防止连接电极边缘的剥离失效。通过第五宽度L5的设置，可以使得第二隔断坝75覆盖住连接电极72远离显示区域一侧的边缘，或者覆盖住第二无机层97靠近显示区域一侧的边缘，或者同时覆盖住连接电极72远离显示区域一侧的边缘和第二无机层97靠近显示区域一侧的边缘。在示例性实施方式中，连接电极72远离显示区域一侧的边缘在基底上的正投影位于第二隔断坝75在基底上的正投影的范围之内，或者，第二无机层97靠近显示区域一侧的边缘在基底上的正投影位于第二隔断坝75在基底上的正投影的范围之内，或者，连接电极72远离显示区域一侧的边缘在基底上的正投影和第二无机层97靠近显示区域一侧的边缘在基底上的正投影均位于第二隔断坝75在基底上的正投影的范围之内。在连接电极72在基底上的正投影和第二无机层97在基底上的正投影至少具有部分交叠时，该部分交叠位于第二隔断坝75在基底上的正投影的范围之内。由于电源线310的第一边缘311被第二隔断层70覆盖，第二无机层97覆盖第二隔断层70，第二无机层97的边缘被连接电极72覆盖，而连接电极72的边缘被第二隔断坝75覆盖，使得电源线的第一边缘、第二无机层边缘和连接电极边缘被依次包覆，所形成的多重包覆可以有效防止电源线的第一边缘、第二无机层边缘和连接电极边缘的剥离失效。
在示例性实施方式中，第二隔断坝可以设置在第二隔断结构靠近显示区域的一侧，实现对膜层边缘的多重包覆。此时，包括第二隔断坝的第二隔断结构具有不同的高度。在一些可能的示例性实施方式中，第二隔断坝可以同时设置在第二隔断结构靠近显示区域的一侧和远离显示区域的一侧，形成沿着第一边缘延伸的二个线形坝体，在实现对膜层边缘多重包覆的同时，提高第二隔断结构的隔断效果。
在示例性实施方式中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯 二甲酸乙二醇酯等。在平行于显示基板的平面内，像素开口的形状可以是三角形、矩形、多边形、圆形或椭圆形等。在垂直于显示基板的平面内，像素开口的截面形状可以是矩形或者梯形等，第一隔断坝74和第二隔断坝75的截面形状可以是梯形状，隔断坝远离基底一侧的宽度小于隔断坝靠近基底一侧的宽度。
(17)形成有机发光层图案。在示例性实施方式中，形成有机发光层图案可以包括：在形成前述图案的基底上，通过蒸镀方式或喷墨打印方式形成有机发光层76图案，如图13a、图13b和图13c所示，图13a为图3中A-A向的剖视图，图13b为图6中B-B向的剖视图，图13c为图6中C-C向的剖视图。
在示例性实施方式中，有机发光层76可以仅形成在显示区域，有机发光层76通过像素开口与阳极71连接。
在示例性实施方式中，由于隔断槽61为侧蚀结构，且第一无机层96和第二无机层97具有凸出隔断槽61上开口的“屋檐”结构，因而显示区域中的有机发光层76在隔断槽61的“屋檐”结构处断开，在隔断槽61的底部形成有机发光块，有机发光块与有机发光层76相互隔离设置。本公开通过设置隔断槽使有机发光层断开，可以截断水氧的传输通道，有效阻断来自孔区的水氧入侵。
在示例性实施方式中，由于孔区50内壁的复合绝缘层具有凸出基底的“屋檐”结构，因而显示区域中的有机发光层76在孔区50的“屋檐”结构处断开，在孔区50底部的玻璃载板1上形成有机发光块，有机发光块与有机发光层76相互隔离设置。本公开通过在显示区域的孔区底部形成有机发光块，使得后续形成的无机封装层形成在有机发光块上，由于有机发光材料与玻璃衬底容易分离，因而有效避免了显示基板和玻璃载板剥离过程中膜层不能剥离的情况。
在示例性实施方式中，通过掩膜板的设计可以使有机发光层76仅形成在显示区域，或者可以使有机发光层76形成在显示区域，以及形成在电路区301、电源线区302和边缘区303中的任意一个区或多个区中，使得这些区域的隔断槽底部和孔区底部形成有机发光块。
在示例性实施方式中，有机发光层可以包括发光层(EML)，以及如下任意一种或多种：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，有机发光层可以通过采用精细金属掩模版(Fine Metal Mask，简称FMM)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在示例性实施方式中，可以采用如下制备方法制备有机发光层。先采用开放式掩膜版依次蒸镀空穴注入层和空穴传输层，在显示基板上形成空穴注入层和空穴传输层的共通层。随后，采用精细金属掩模版在红色子像素蒸镀电子阻挡层和红色发光层，在绿色子像素蒸镀电子阻挡层和绿色发光层，在蓝色子像素蒸镀电子阻挡层和蓝色发光层，相邻子像素的电子阻挡层和发光层可以有少量的交叠(例如，交叠部分占各自发光层图案的面积小于10％)，或者可以是隔离的。随后，采用开放式掩膜版依次蒸镀空穴阻挡层、电子传输层和电子注入层，在显示基板上形成空穴阻挡层、电子传输层和电子注入层的共通层。
在示例性实施方式中，电子阻挡层可以作为发光器件的微腔调节层，通过设计电子阻挡层的厚度，可以使得阴极和阳极之间有机发光层的厚度满足微腔长度的设计。在一些示例性实施方式中，可以采用有机发光层中的空穴传输层、空穴阻挡层或电子传输层作为发光器件的微腔调节层，本公开在此不做限定。
在示例性实施方式中，发光层可以包括主体(Host)材料和掺杂在主体材料中的客体(Dopant)材料，发光层客体材料的掺杂比例为1％至20％。在该掺杂比例范围内，一方面发光层主体材料可将激子能量有效转移给发光层客体材料来激发发光层客体材料发光，另一方面发光层主体材料对发光层客体材料进行了“稀释”，有效改善了发光层客体材料分子间相互碰撞、以及能量间相互碰撞引起的荧光淬灭，提高了发光效率和器件寿命。在示例性实施方式中，掺杂比例是指客体材料的质量与发光层的质量之比，即质量百分比。在示例性实施方式中，可以通过多源蒸镀工艺共同蒸镀主体材料和客体材料，使主体材料和客体材料均匀分散在发光层中，可以在蒸镀过程中通过 控制客体材料的蒸镀速率来调控掺杂比例，或者通过控制主体材料和客体材料的蒸镀速率比来调控掺杂比例。在示例性实施方式中，发光层的厚度可以约为10nm至50nm。
在示例性实施方式中，空穴注入层可以采用无机的氧化物，如钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物或锰氧化物，或者可以采用强吸电子体系的p型掺杂剂和空穴传输材料的掺杂物。在示例性实施方式中，空穴注入层的厚度可以约为5nm至20nm。
在示例性实施方式中，在示例性实施方式中，空穴传输层可以采用空穴迁移率较高的材料，如芳胺类化合物，其取代基团可以是咔唑、甲基芴、螺芴、二苯并噻吩或呋喃等。在示例性实施方式中，空穴传输层的厚度可以约为40nm至150nm。
在示例性实施方式中，空穴阻挡层和电子传输层可以采用芳族杂环化合物，例如苯并咪唑衍生物、咪唑并吡啶衍生物、苯并咪唑并菲啶衍生物等咪唑衍生物；嘧啶衍生物、三嗪衍生物等嗪衍生物；喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等包含含氮六元环结构的化合物(也包括在杂环上具有氧化膦系的取代基的化合物)等。在示例性实施方式中，空穴阻挡层的厚度可以约为5nm至15nm，电子传输层的厚度可以约为20nm至50nm。
在示例性实施方式中，电子注入层可以采用碱金属或者金属，例如氟化锂(LiF)、镱(Yb)、镁(Mg)或钙(Ca)等材料，或者这些碱金属或者金属的化合物等。在示例性实施方式中，电子注入层的厚度可以约为0.5nm至2nm。
(18)形成阴极图案。在示例性实施方式中，形成阴极图案可以包括：在形成前述图案的基底上，通过蒸镀方式形成阴极77图案，如图14a、图14b和图14c所示所示，图14a为图3中A-A向的剖视图，图14b为图6中B-B向的剖视图，图14c为图6中C-C向的剖视图。在示例性实施方式中，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
在示例性实施方式中，可拉伸的阴极77可以形成在显示区域、电路区301和电源线区302，可以是连通在一起的整体结构。显示区域的阴极77与有机发光层76连接，实现了有机发光层76同时与阳极71和阴极77连接。电源线区302的阴极77与第三开口K3暴露出的连接电极72连接，由于电源线310与连接电极72连接，连接电极72与阴极77连接，因而实现了阴极77与电源线310的连接。
在示例性实施方式中，由于隔断槽61为侧蚀结构，且第一无机层96和第二无机层97具有凸出隔断槽61上开口的“屋檐”结构，因而显示区域、电路区301和电源线区302中的阴极77在隔断槽61的“屋檐”结构处断开，在隔断槽61的底部形成阴极块，阴极块与阴极77相互隔离设置。
在示例性实施方式中，由于孔区50内壁的复合绝缘层具有凸出基底的“屋檐”结构，因而显示区域、电路区301和电源线区302中的阴极77在孔区50的“屋檐”结构处断开，在孔区50底部的玻璃载板1上形成阴极块，阴极块与阴极77相互隔离设置。本公开通过设置隔断槽使阴极断开，可以截断水氧的传输通道，有效阻断来自孔区的水氧入侵。
在示例性实施方式中，在显示区域，阴极块设置在隔断槽61底部和孔区50底部的有机发光块上。在电路区301和电源线区302，阴极块设置在隔断槽61的底部和孔区50底部的玻璃衬底1上。本公开通过在电路区和电源线区的孔区底部形成阴极块，使得后续形成的无机封装层形成在阴极块上，由于蒸镀形成的阴极块与玻璃衬底容易分离，因而有效避免了显示基板和玻璃载板剥离过程中膜层不能剥离的情况。
在示例性实施方式中，在电源线区302，整体结构的阴极77完全包裹第一隔断坝74和第二隔断坝75。由于电源线310的孔区边缘313被第一隔断层60覆盖，第一无机层96覆盖第一隔断层60，第一无机层96的边缘被连接电极72覆盖，连接电极72的边缘被第一隔断坝74覆盖，而第一隔断坝74被阴极77完全覆盖，使得电源线的孔区边缘、第一无机层边缘、连接电极边缘和第一隔断坝被依次包覆，所形成的多重包覆可以进一步防止电源线孔区边缘、第一无机层边缘和连接电极边缘的剥离失效，且保证了结构表面的平滑。由于电源线310的第一边缘311被第二隔断层70覆盖，第二无机层 97覆盖第二隔断层70，第二无机层97的边缘被连接电极72覆盖，连接电极72的边缘被第二隔断坝75覆盖，而第二隔断坝75被阴极77完全覆盖，使得电源线的第一边缘、第二无机层边缘、连接电极边缘和第二隔断坝被依次包覆，所形成的多重包覆可以进一步防止电源线的第一边缘、第二无机层边缘和连接电极边缘的剥离失效，且保证了结构表面的平滑。
在示例性实施方式中，通过掩膜板的设计可以在边缘区303形成阴极，使得边缘区的隔断槽底部和孔区底部形成阴极块。
(19)形成光学耦合层图案。在示例性实施方式中，形成光学耦合层图案可以包括：在形成前述图案的基底上，通过蒸镀方式形成光学耦合层78图案，如图15a、图15b和图15c所示，图15a为图3中A-A向的剖视图，图15b为图6中B-B向的剖视图，图15c为图6中C-C向的剖视图。
在示例性实施方式中，光学耦合层78可以形成在显示区域、电路区301、电源线区302和边缘区303，可以是连通在一起的整体结构。在显示区域、电路区301和电源线区302，光学耦合层78设置在阴极77上，在边缘区303，光学耦合层78设置在复合绝缘层和第一隔断结构上。
在示例性实施方式中，由于隔断槽61为侧蚀结构，且第一无机层96和第二无机层97具有凸出隔断槽61上开口的“屋檐”结构，因而光学耦合层78在隔断槽61的“屋檐”结构处断开，在隔断槽61的底部形成光学耦合块，光学耦合块与光学耦合层78相互隔离设置。
在示例性实施方式中，由于孔区50内壁的复合绝缘层具有凸出基底的“屋檐”结构，因而光学耦合层78在孔区50的“屋檐”结构处断开，在孔区50底部的玻璃载板1上形成光学耦合块，光学耦合块与光学耦合层78相互隔离设置。本公开通过设置隔断槽使光学耦合块断开，可以截断水氧的传输通道，有效阻断来自孔区的水氧入侵。
在示例性实施方式中，在显示区域、电路区301和电源线区302，光学耦合块设置在隔断槽61和孔区50底部的阴极块上。在边缘区303，光学耦合块设置在隔断槽61的底部和孔区50底部的玻璃衬底1上。本公开通过在边缘区的孔区底部形成光学耦合块，使得后续形成的无机封装层形成在光学 耦合块上，由于蒸镀形成的光学耦合块与玻璃衬底容易分离，因而有效避免了显示基板和玻璃载板剥离过程中膜层不能剥离的情况。
在示例性实施方式中，边缘区的光学耦合层覆盖第一无机层远离孔区一侧的边缘，在一定程度上可以防止边缘区的第一无机层边缘的剥离失效。
在示例性实施方式中，光学耦合层的折射率可以大于阴极的折射率，有利于光取出并增加出光效率。光学耦合层的材料可以采用有机材料，或者采用无机材料，或者采用有机材料和无机材料，可以是单层、多层或复合层，本公开在此不做限定。
在示例性实施方式中，当光波(电磁波)入射到金属与电介质分界面时，金属表面的自由电子发生集体振荡，电磁波与金属表面自由电子耦合而形成的一种沿着金属表面传播的近场电磁波，如果电子的振荡频率与入射光波的频率一致就会产生共振，在共振状态下电磁场的能量被有效地转变为金属表面自由电子的集体振动能，这时就形成的一种特殊的电磁模式：电磁场被局限在金属表面很小的范围内并发生增强，这种现象就被称为表面等离子激元(Surface Plasmon Polariton，简称SPP)效应，该效应会导致出射光效率降低。本公开示例性实施例通过设置光学耦合层，可以有效减少表面等离子激元现象，以减少光损耗，有效提高了发光器件内部的耦合出光效率，更利于发挥器件的出光特性。此外，由于阴极对出射光具有半透半反作用，通过在阴极上设置光学耦合层，可以有效调节出射光的反射率和透过率，并有效调节光学微谐振腔的腔长，提高出射光强度。
至此，制备完成发光结构层。在显示区域，发光结构层包括阳极71、有机发光层76、阴极77和光学耦合层78，有机发光层76设置在阳极71和阴极77之间。
(20)形成封装层图案。在示例性实施方式中，形成封装层图案可以包括：在形成前述图案的基底上，利用开放式掩膜板采用沉积方式沉积第一无机封装薄膜，在显示区域、电路区301、电源线区302和边缘区303形成第一封装层81。随后，利用喷墨打印工艺打印有机封装材料，对有机封装材料进行图案化，去掉孔区及孔区附近的有机封装材料，固化成膜后，在显示区域、电路区301、电源线区302和边缘区303形成第二封装层82。随后，利 用开放式掩膜板采用沉积方式沉积第二无机封装薄膜，在显示区域、电路区301、电源线区302和边缘区303形成第三封装层83，如图16a、图16b和图16c所示，图16a为图3中A-A向的剖视图，图16b为图6中B-B向的剖视图，图16c为图6中C-C向的剖视图。
在示例性实施方式中，在显示区域、电路区310、电源线区302和边缘区303，第一封装层81设置在光学耦合层78上，并覆盖隔断槽61和孔区50的内壁，覆盖隔断槽61和孔区50底部的光学耦合块。第一封装层81对孔区和隔断槽的完整包裹保证了封装完整性，不仅有效隔绝了来自孔区的水氧，而且隔断槽对封装层形成钉扎点，可以进一步防止膜层边缘的剥离失效。第二封装层82设置在第一封装层81上，并完全填充隔断槽61，孔区及孔区附近区域的第二封装层82被去掉，暴露出第一封装层81的表面。在孔区以外区域，第三封装层83设置在第二封装层82上，形成无机材料/有机材料/无机材料的叠层结构，在孔区及孔区附近区域，第三封装层83设置在第一封装层81上，形成无机材料/无机材料的叠层结构。孔区以外区域的无机材料/有机材料/无机材料叠层结构可以保证有效的封装，孔区及孔区附近区域的无机材料/无机材料叠层结构可以进一步保证封装完整性，有效隔绝来自孔区的水氧。
在示例性实施例中，第一封装薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，可以保证外界水氧无法进入发光结构层。有机封装材料可以采用树脂材料，起到包覆显示基板各个膜层的作用，以提高结构稳定性和平坦性。
在示例性实施方式中，第一封装层和第二封装层构成封装层。在示例性实施方式中，制备完成封装层后，可以在封装层上形成触摸结构层(TSP)，触摸结构层可以包括触控电极层，或者包括触控电极层和触控绝缘层，本公开在此不作限定。
后续工艺中，可以通过图案化工艺对孔区进行刻蚀，刻蚀掉孔区底部的膜层，形成通孔。由于刻蚀工艺基本上是沿着覆盖通孔内壁的第一封装层的表面进行刻蚀，因而最终刻蚀形成的通孔内壁可以包含基底段、有机材料段和无机材料段，且基底段、有机材料段和无机材料段沿着从基底到第一封装 层的方向排布。
在示例性实施方式中，显示区域的孔区内壁中，基底段可以包括由第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层形成的内壁，有机材料段可以包括由有机材料块、阴极块和光学耦合块形成的内壁，无机材料段可以是由第一封装层形成的内壁。
在示例性实施方式中，电路区和电源线区的孔区内壁中，基底段可以包括由第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层形成的内壁，有机材料段可以包括由阴极块和光学耦合块形成的内壁，无机材料段可以是由第一封装层形成的内壁。
在示例性实施方式中，边缘区的孔区内壁中，基底段可以包括由第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层形成的内壁，有机材料段可以是由光学耦合块形成的内壁，无机材料段可以是由第一封装层形成的内壁。
后续工艺中，可以通过激光剥离工艺将显示基板与玻璃衬底剥离。本公开示例性实施例在孔区内形成有机材料，后续形成的第一封装层形成在有机材料上，在刻蚀形成通孔中，即使通孔底部的第一封装层未被完全刻蚀掉，残留有部分第一封装层，但残留的第一封装层设置在有机材料上，由于有机材料与玻璃衬底之间的粘着力较弱，因而激光剥离工艺中有机材料很容易与玻璃衬底分离，有效避免了显示基板和玻璃载板剥离过程中膜层不能剥离的情况。
在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程还可以包括贴附背膜、切割等工艺，本公开在此不作限定。
一种设置拉伸孔的显示基板中，不仅存在剥离过程中膜层不能有效剥离的问题，而且存在封装失效的问题。研究发现，封装失效在一定程度上是由于隔断结构中的膜层边缘出现剥离(peeling)造成的，特别是电源线边缘的剥离。通常，显示基板拉伸变形中会使隔断结构承受较大的拉力，这些拉力作用在膜层边缘会导致膜层边缘出现剥离，在膜层边缘形成空洞。当封装层出现裂缝时，外界的水氧可以通过裂缝进入空洞，并沿着空洞形成的通道流 通，直至扩散到发光结构层，导致封装失效。进一步研究发现，剥离过程中膜层不能有效剥离在一定程度上是由于拉伸孔内存在无机封装层残留造成的。目前的孔区刻蚀工艺中，很难完全刻蚀掉孔区内的结构层，特别是边缘区中直接沉积在玻璃衬底上的第一封装层，使得孔区底部会残留有部分贴合在玻璃衬底上的第一封装层。当孔区底部残留有部分第一封装层时，由于第一封装层与玻璃衬底之间的粘着力较强，使得剥离工艺中部分第一封装层未能与玻璃衬底分离，而残留在玻璃衬底上的第一封装层会使封装层出现拉拽裂缝(Crack)，进而导致封装失效。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，本公开示例性实施例通过在电源线边缘所在区域形成边缘多重包覆结构，有效避免了膜层边缘的剥离，特别是电源线边缘的剥离。本公开示例性实施例中，电源线的孔区边缘和第一边缘被隔断层覆盖，隔断层被无机层覆盖，无机层的边缘被连接电极覆盖，连接电极的边缘被隔断坝覆盖，隔断坝被阴极覆盖，使得电源线边缘、无机层边缘、连接电极边缘和隔断坝被依次包覆，所形成的边缘多重包覆结构可以有效避免电源线边缘、无机层边缘和连接电极边缘的剥离失效，可拉伸的边缘结构稳定，信赖性好，避免了在膜层边缘形成水氧传输通道，有效保证了显示基板的封装效果。本公开示例性实施例通过在孔区内形成有机材料，使得后续形成的第一封装层设置在有机材料上，有机材料可以与玻璃衬底无损分离，不仅避免了显示基板的膜层不能与玻璃衬底分离的情况，而且避免了第一封装层出现拉拽裂缝，有效保证了显示基板的封装效果。本公开示例性实施例显示基板的制备过程具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图17a和图17b为本公开示例性实施例另一种显示基板的剖面结构示意图，图17a示意了电路区301和电源线区302交界处的剖面结构，为图6中B-B向的剖视图，图17b示意了电源线区302和边缘区303交界处的剖面结构，为图6中C-C向的剖视图。在示例性实施方式中，显示区域的膜层结构、电源线区的复合绝缘层和电源线与前述实施例基本上相同。
在示例性实施方式中，第一隔断结构包括环绕孔区50的第一隔断层60、设置在第一隔断层60上的第一无机层96和设置在第一无机层96上的第三无 机层98，第一隔断层60上设置有环绕孔区50的隔断槽61，第一无机层96上设置有环绕孔区50的隔断孔，隔断孔和隔断槽连通。位于隔断孔周边的第一无机层96相对于隔断槽61的侧壁具有突出部，突出部和隔断槽的侧壁形成内陷结构，第三无机层98覆盖第一无机层96，并覆盖隔断槽61的内壁。
在示例性实施方式中，第一隔断结构中的第一隔断层60覆盖电源线310靠近孔区50一侧的孔区边缘313，第一隔断结构中远离孔区50一侧的第一无机层96和第三无机层98与电源线310不直接接触，即第一无机层96和第三无机层98在基底上的正投影与电源线310在基底上的正投影没有交叠。
在示例性实施方式中，连接电极72靠近孔区50的一侧与第一隔断结构中远离孔区50一侧的第一无机层96和第三无机层98不直接接触，第一无机层96和第三无机层98在基底上的正投影与连接电极72在基底上的正投影没有交叠。
在示例性实施方式中，第一隔断坝74设置在第一隔断结构远离孔区50的一侧，第一隔断坝74靠近孔区50的一侧覆盖第一无机层96和第三无机层98远离孔区50一侧的边缘，第一无机层96和第三无机层98在基底上的正投影与第一隔断坝74在基底上的正投影存在重叠区域。第一隔断坝74远离孔区50的一侧覆盖连接电极72靠近孔区50一侧的边缘，连接电极72在基底上的正投影与第一隔断坝74在基底上的正投影存在重叠区域。
在示例性实施方式中，第二隔断结构包括沿着第一边缘311延伸的第二隔断层70、设置在第二隔断层70上的第二无机层97和设置在第二无机层97上的第三无机层98，第二隔断层70上设置有沿着第一边缘311延伸的隔断槽61，第二无机层97上设置有沿着第一边缘311延伸的隔断孔，隔断孔和隔断槽连通。位于隔断孔周边的第二无机层97相对于隔断槽61的侧壁具有突出部，突出部和隔断槽的侧壁形成内陷结构，第三无机层98覆盖第二无机层97，并覆盖隔断槽61的内壁。
在示例性实施方式中，第二隔断结构中的第二隔断层70覆盖电源线310的第一边缘311，第二隔断结构中靠近显示区域一侧的第二无机层97与电源线310不直接接触，第二无机层97和第三无机层98在基底上的正投影与电源线310在基底上的正投影没有交叠。
在示例性实施方式中，连接电极72靠近第一边缘311的一侧与第二隔断结构中靠近显示区域一侧第二无机层97和第三无机层98不直接接触，第二无机层97和第三无机层98在基底上的正投影与连接电极72在基底上的正投影没有交叠。
在示例性实施方式中，第二隔断坝75设置在所述第二隔断结构靠近显示区域的一侧，第二隔断坝75远离显示区域的一侧覆盖第二无机层97和第三无机层98靠近显示区域一侧的边缘，第二无机层97和第三无机层98在基底上的正投影与第二隔断坝75在基底上的正投影存在重叠区域。第二隔断坝75靠近显示区域的一侧覆盖连接电极72靠近第一边缘311一侧的边缘，连接电极72在基底上的正投影与第二隔断坝75在基底上的正投影存在重叠区域。
在示例性实施方式中，阴极77包裹第一隔断坝74和第二隔断坝75，即阴极77覆盖第一隔断坝74和第二隔断坝75暴露出的全部表面。
在示例性实施方式中，第一隔断层60和第二隔断层70可以与驱动电路层中的平坦层同层设置，第一隔断坝74和第二隔断坝75可以与发光结构层中的像素定义层同层设置，第一无机层和第二无机层同层设置，且与显示区域中的一个绝缘层同层设置，第三无机层可以与显示区域中的另一个绝缘层同层设置。
在示例性实施方式中，本公开示例性实施例另一种显示基板的制备过程可以包括如下操作。
(21)至(23)制备基底、驱动结构层和隔断层等图案的过程，与前述实施例的制备过程(11)至(13)相同。
(24-1)形成隔断槽图案。在示例性实施方式中，形成隔断槽图案可以包括：在形成前述图案的基底上沉积无机材料薄膜，通过图案化工艺对无机材料薄膜进行图案化，形成覆盖第一隔断层60部分表面的第一无机层96、覆盖第二隔断层70部分表面的第二无机层97以及设置在第一隔断层60和第二隔断层70上的隔断槽61，如图18a和图18b，图18a为图6中B-B向的剖视图，图18b为图6中C-C向的剖视图。
在示例性实施方式中，对于电源线区302中第一隔断结构的第一无机层96，第一无机层96靠近孔区50的一侧覆盖第一隔断层60靠近孔区50一侧的表面，第一无机层96远离孔区50的一侧位于第一隔断层60远离基底一侧的表面上，第一隔断层60远离孔区50一侧的部分表面没有被第一无机层96覆盖，因而第一无机层96远离孔区50的一侧与电源线310不直接连接，第一无机层96在基底上的正投影与电源线310在基底上的正投影没有重叠区域。
在示例性实施方式中，对于电源线区302中第二隔断结构的第二无机层97，第二无机层97远离显示区域的一侧覆盖第二隔断层70远离显示区域一侧的表面，第二无机层97靠近显示区域的一侧位于第二隔断层70远离基底一侧的表面上，第二隔断层70靠近显示区域一侧的部分表面没有被第二无机层97覆盖，因而第二无机层97靠近显示区域的一侧与电源线310不直接连接，第二无机层97在基底上的正投影与电源线310在基底上的正投影没有重叠区域。
在示例性实施方式中，对于边缘区303中第一隔断结构的第一无机层96，第一无机层96覆盖第一隔断层60的外表面。
在示例性实施方式中，第一隔断结构和第二隔断结构中形成具有侧蚀结构的隔断槽的结构和过程与前述示例性实施例相近。
(24-2)形成第三无机层图案。在示例性实施方式中，形成第三无机层图案可以包括：在形成前述图案的基底上沉积无机材料薄膜，通过图案化工艺对无机材料薄膜进行图案化，形成第三无机层98图案，如图19a和图19b，图19a为图6中B-B向的剖视图，图19b为图6中C-C向的剖视图。
在示例性实施方式中，第三无机层98设置在第一无机层96和第二无机层97远离基底的一侧，并覆盖隔断槽61的内壁，覆盖内壁包括覆盖隔断槽61的侧壁表面和底部表面。第三无机层98对隔断槽内壁的完整包裹保证了隔断结构的完整性，可以保证隔断结构的隔断效果。
在示例性实施方式中，对于电源线区302中第一隔断结构的第三无机层98，第三无机层98靠近孔区50的一侧覆盖第一无机层96靠近孔区50一侧的表面，第三无机层98远离孔区50的一侧位于第一无机层96远离基底一侧 的表面上，且第三无机层98远离孔区50一侧的边缘与第一无机层96远离孔区50一侧的边缘基本上平齐，因而第三无机层98远离孔区50的一侧与电源线310不直接连接，第一无机层96和第三无机层98在基底上的正投影与电源线310在基底上的正投影没有重叠区域。
在示例性实施方式中，对于电源线区302中第二隔断结构的第三无机层98，第三无机层98远离显示区域的一侧覆盖第二无机层97远离显示区域一侧的表面，第三无机层98靠近显示区域的一侧位于第二无机层97远离基底一侧的表面上，且第三无机层98靠近显示区域一侧的边缘与第二无机层97靠近显示区域一侧的边缘基本上平齐，因而第三无机层98靠近显示区域的一侧与电源线310不直接连接，第二无机层97和第三无机层98在基底上的正投影与电源线310在基底上的正投影没有重叠区域。
在示例性实施方式中，第一隔断层60和设置在第一隔断层60上的隔断槽61、设置在第一隔断层60上的第一无机层96和设置在第一无机层96上的隔断孔、以及设置在第一无机层96上和覆盖隔断槽内壁的第三无机层98组成第一隔断结构，第一隔断结构形成在环绕孔区50的隔断区51，为环绕孔区50的环形隔断结构。
在示例性实施方式中，第二隔断层70和设置在第二隔断层70上的隔断槽61、设置在第二隔断层70上的第二无机层97和设置在第二无机层97上的隔断孔、以及设置在第二无机层97上和覆盖隔断槽内壁的第三无机层98组成第二隔断结构，第二隔断结构形成在第一边缘311远离显示区域的一侧，为沿着第一边缘311延伸的线形隔断结构。
(25)形成连接电极图案。在示例性实施方式中，形成连接电极图案可以包括：在形成前述图案的基底上沉积导电薄膜，通过图案化工艺对导电薄膜进行图案化，形成连接电极图案，如图20a和图20b所示，图20a为图6中B-B向的剖视图，图20b为图6中C-C向的剖视图。
在示例性实施方式中，连接电极72设置在电源线区302远离基底的一侧，实现连接电极72与电源线310的连接。
在示例性实施方式中，连接电极72靠近孔区50一侧的边缘与第一隔断 结构间隔一段距离，连接电极72与第一隔断层60、第一无机层96和第三无机层98均没有接触连接，连接电极72在基底上的正投影与第一隔断结构中的第一隔断层60、第一无机层96和第三无机层98在基底上的正投影没有重叠。
在示例性实施方式中，连接电极72远离显示区域一侧的边缘与第二隔断结构间隔一段距离，连接电极72与第二隔断层70、第二无机层97和第三无机层98均没有接触连接，连接电极72在基底上的正投影与第二隔断结构中的第二隔断层70、第二无机层97和第三无机层98在基底上的正投影没有重叠。
(26)形成隔断坝图案。在示例性实施方式中，形成隔断坝图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成第一隔断坝74和第二隔断坝75图案，如图21a和图21b所示，图21a为图6中B-B向的剖视图，图21b为图6中C-C向的剖视图。
在示例性实施方式中，第一隔断坝74可以形成在第一隔断结构远离孔区50的外侧，为环绕第一隔断结构的环形坝体。第一隔断坝74靠近孔区50的一侧设置在第一隔断结构远离孔区50一侧的第三无机层98上，且完全覆盖第一无机层96和第三无机层98远离孔区50一侧的边缘。第一隔断坝74远离孔区50的一侧设置在连接电极72上，且完全覆盖连接电极72靠近孔区50一侧的边缘。这样，第一隔断坝74同时覆盖住连接电极72靠近孔区一侧的边缘、第一无机层96和第三无机层98远离孔区一侧的边缘。在示例性实施方式中，连接电极72靠近孔区一侧的边缘在基底上的正投影位于第一隔断坝74在基底上的正投影的范围之内，第一无机层96和第三无机层98远离孔区一侧的边缘在基底上的正投影位于第一隔断坝74在基底上的正投影的范围之内。由于电源线310的孔区边缘313被第一隔断层60覆盖，而第一无机层96和第三无机层98的边缘、连接电极72的边缘被第一隔断坝74覆盖，使得电源线的孔区边缘、第一无机层和第三无机层边缘、连接电极边缘被包覆，可以有效防止电源线孔区边缘、第一无机层和第三无机层边缘、连接电极边缘的剥离失效。
在示例性实施方式中，第二隔断坝75可以形成在第二隔断结构靠近显示区域的一侧，为沿着第一边缘311延伸的线形坝体。第二隔断坝75远离显示区域的一侧设置在第二隔断结构靠近显示区域一侧的第三无机层98上，且完全覆盖第二无机层97和第三无机层98靠近显示区域一侧的边缘。第二隔断坝75靠近显示区域的一侧设置在连接电极72上，且完全覆盖连接电极72远离显示区域一侧的边缘。这样，第二隔断坝75同时覆盖住连接电极72远离显示区域一侧的边缘、第二无机层97和第三无机层98靠近显示区域一侧的边缘。在示例性实施方式中，连接电极72远离显示区域一侧的边缘在基底上的正投影位于第二隔断坝75在基底上的正投影的范围之内，第二无机层97和第三无机层98靠近显示区域一侧的边缘在基底上的正投影位于第二隔断坝75在基底上的正投影的范围之内。由于电源线310的第一边缘311被第二隔断层70覆盖，而第二无机层97和第三无机层98的边缘、连接电极72的边缘被第二隔断坝75覆盖，使得电源线的第一边缘、第二无机层边缘和第三无机层边缘、连接电极边缘被依次包覆，可以有效防止电源线的第一边缘、第二无机层和第三无机层边缘、连接电极边缘的剥离失效。
(27)至(30)形成有机发光层、阴极、光学耦合层、封装层及其后续工艺过程，与前述实施例的制备过程(17)至(20)相同。
本公开示例性实施例通过在电源线边缘所在区域形成隔断坝的覆盖结构，有效避免了膜层边缘的剥离，特别是电源线边缘的剥离。
本公开示例性实施例中，电源线的孔区边缘和第一边缘被隔断层覆盖，无机层的边缘和连接电极的边缘被隔断坝覆盖，不仅可以有效避免电源线边缘、无机层边缘和连接电极边缘的剥离失效，可拉伸的边缘结构稳定，信赖性好，避免了在膜层边缘形成水氧传输通道，有效保证了显示基板的封装效果，而且通过设置无机层与电源线不接触、无机层与连接电极不接触，可以降低工艺难度，减少因为膜层段差导致的材料残留，有效保证了工艺质量，提高了良品率。此外，通过在孔区内形成有机材料，使得后续形成的第一封装层设置在有机材料上，有机材料可以与玻璃衬底无损分离，不仅避免了显示基板的膜层不能与玻璃衬底分离的情况，而且避免了第一封装层出现拉拽裂缝，有效保证了显示基板的封装效果。本公开示例性实施例显示基板的制 备过程具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开示例性实施例显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺。例如，孔区外侧可以设置多个依次套设的第一隔断结构。又如，第一边缘远离显示区域的一侧可以设置多个依次设置的第二隔断结构，本公开在此不做限定。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (25)

  1. 一种显示基板，包括显示区域和位于所述显示区域至少一侧的边框区域，所述显示区域和边框区域包括至少一个拉伸孔；所述拉伸孔包括孔区和环绕所述拉伸孔的隔断区，所述隔断区设置有环绕所述孔区的第一隔断结构；所述第一隔断结构包括环绕所述孔区的第一隔断层和设置在所述第一隔断层上的第一覆盖层，所述第一隔断层上设置有环绕所述孔区的隔断槽，所述第一覆盖层上设置有环绕所述孔区的隔断孔，所述隔断孔和隔断槽连通；位于所述隔断孔周边的第一覆盖层相对于所述隔断槽的侧壁具有突出部，所述突出部和所述隔断槽的侧壁形成内陷结构。
  2. 根据权利要求1所述的显示基板，其中，所述边框区域包括沿着远离所述显示区域方向依次设置的电路区、电源线区和边缘区，所述电源线区包括至少一个拉伸孔；在垂直于所述基底的平面内，所述电源线区包括设置在基底上的至少一层绝缘层和设置在所述至少一层绝缘层上的电源线；所述第一隔断结构中的第一隔断层覆盖所述电源线靠近所述孔区一侧的孔区边缘。
  3. 根据权利要求2所述的显示基板，其中，所述第一覆盖层与所述电源线不直接接触。
  4. 根据权利要求2所述的显示基板，其中，所述第一隔断结构中远离所述孔区一侧的第一覆盖层搭设在所述电源线上。
  5. 根据权利要求2所述的显示基板，其中，所述电源线在所述显示基板平面上的正投影和所述第一覆盖层在所述显示基板平面上的正投影至多部分交叠。
  6. 根据权利要求2所述的显示基板，其中，在平行于所述基底的平面内，所述电源线的第一边缘和/或第二边缘为折线，所述第一边缘为所述电源线远离所述显示区域一侧的边缘，所述第二边缘为所述电源线靠近所述显示区域一侧的边缘。
  7. 根据权利要求6所述的显示基板，其中，所述第一边缘和/或第二边缘在所述显示基板平面上的正投影与所述拉伸孔在所述显示基板平面上的正投影不重叠。
  8. 根据权利要求6所述的显示基板，其中，所述第一边缘远离所述显示区域的一侧设置有第二隔断结构，所述第二隔断结构包括沿着所述第一边缘延伸的第二隔断层和设置在所述第二隔断层上的第二覆盖层，所述第二隔断层上设置有沿着所述第一边缘延伸的隔断槽，所述第二覆盖层上设置有沿着所述第一边缘延伸的隔断孔，所述隔断孔和隔断槽连通；位于所述隔断孔周边的第二覆盖层相对于所述隔断槽的侧壁具有突出部，所述突出部和所述隔断槽的侧壁形成内陷结构。
  9. 根据权利要求8所述的显示基板，其中，所述第二隔断结构中的第二隔断层覆盖所述电源线的第一边缘。
  10. 根据权利要求8所述的显示基板，其中，所述第二覆盖层与所述电源线不直接接触。
  11. 根据权利要求8所述的显示基板，其中，所述第二隔断结构中靠近所述显示区域一侧的第二覆盖层搭设在所述电源线上。
  12. 根据权利要求2至11任一项所述的显示基板，其中，所述电源线区还包括连接电极和环绕所述孔区的第一隔断坝，所述连接电极设置在所述电源线上，所述第一隔断坝设置在所述第一隔断结构远离所述孔区的一侧，所述第一隔断坝远离所述孔区的一侧覆盖所述连接电极靠近所述孔区一侧的边缘。
  13. 根据权利要求8至11任一项所述的显示基板，其中，所述电源线区还包括连接电极和沿着所述第一边缘延伸的第二隔断坝，所述第二隔断坝设置在所述第二隔断结构靠近所述显示区域的一侧，所述第二隔断坝靠近显示区域的一侧覆盖所述连接电极靠近所述第一边缘一侧的边缘。
  14. 根据权利要求2至11任一项所述的显示基板，还包括设置在第一覆盖层和/或第二覆盖层上方的第三覆盖层，所述第三覆盖层至少覆盖第一覆盖层和/或第二覆盖层，以及所述隔断槽。
  15. 根据权利要求14所述的显示基板，其中，所述第一覆盖层远离所述孔区的边缘和第三覆盖层远离所述孔区的边缘基本齐平；和/或所述第二覆盖层远离所述孔区的边缘和第三覆盖层远离所述孔区的边缘基本齐平。
  16. 根据权利要求2至11任一项所述的显示基板，其中，所述电源线区还包括连接电极，所述连接电极设置在所述电源线上，所述连接电极靠近所述孔区的一侧覆盖所述搭设所述电源线的所述第一覆盖层的边缘，所述连接电极靠近第一边缘的一侧覆盖所述搭设所述电源线的所述第一覆盖层的边缘。
  17. 根据权利要求16所述的显示基板，其中，所述电源线区还包括环绕所述孔区的第一隔断坝，所述第一隔断坝设置在所述第一隔断结构远离所述孔区的一侧，所述第一隔断坝靠近所述孔区的一侧设置在所述第一覆盖层上，所述第一隔断坝远离所述孔区的一侧覆盖所述连接电极靠近所述孔区一侧的边缘。
  18. 根据权利要求17所述的显示基板，其中，所述连接电极靠近所述孔区一侧的边缘在所述显示基板平面上的正投影位于所述第一隔断坝在所述显示基板平面上的正投影的范围之内，和/或，所述第一覆盖层远离所述孔区一侧的边缘在所述显示基板平面上的正投影位于所述第一隔断坝在所述显示基板平面上的正投影的范围之内。
  19. 根据权利要求8所述的显示基板，其中，所述电源线区还包括沿着所述第一边缘延伸的第二隔断坝，所述第二隔断坝设置在所述第二隔断结构靠近所述显示区域的一侧，所述第二隔断坝远离所述显示区域的一侧设置在所述第二覆盖层上，所述第二隔断坝靠近显示区域的一侧覆盖所述连接电极靠近所述第一边缘一侧的边缘。
  20. 根据权利要求19所述的显示基板，其中，所述连接电极远离显示区域一侧的边缘在所述显示基板平面上的正投影位于所述第二隔断坝在所述显示基板平面上的正投影的范围之内，和/或，所述第二覆盖层靠近显示区域一侧的边缘在所述显示基板平面上的正投影位于所述第二隔断坝在所述显示基板平面上的正投影的范围之内。
  21. 根据权利要求19所述的显示基板，其中，所述连接电极在所述显示基板平面上的正投影和所述第一覆盖层在所述显示基板平面上的正投影至少具有第一部分交叠；所述连接电极在所述显示基板平面上的正投影和所述第二覆盖层在所述显示基板平面上的正投影至少具有第二部分交叠。
  22. 根据权利要求21所述的显示基板，其中，所述第一部分交叠位于第一隔断坝在所述显示基板平面上的正投影的范围之内，所述第二部分交叠位于第二隔断坝在所述显示基板平面上的正投影的范围之内。
  23. 根据权利要求22所述的显示基板，其中，所述电源线区还包括阴极，所述阴极设置在所述连接电极上，且包裹第一隔断坝和第二隔断坝。
  24. 根据权利要求1至23任一项所述的显示基板，其中，所述显示区域包括设置在基底上的驱动电路层和设置在所述驱动电路层上的发光结构层；第一隔断层和第二隔断层与所述驱动电路层中的平坦层同层设置，第一隔断坝和第二隔断坝与所述发光结构层中的像素定义层同层设置。
  25. 一种显示装置，包括权利要求1至24任一项所述的显示基板。
PCT/CN2022/080153 2021-06-17 2022-03-10 显示基板和显示装置 WO2022262329A1 (zh)

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