CN101213671A - 利用金属氧化物纳米粒子制备电子器件的方法 - Google Patents
利用金属氧化物纳米粒子制备电子器件的方法 Download PDFInfo
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- CN101213671A CN101213671A CNA2006800234135A CN200680023413A CN101213671A CN 101213671 A CN101213671 A CN 101213671A CN A2006800234135 A CNA2006800234135 A CN A2006800234135A CN 200680023413 A CN200680023413 A CN 200680023413A CN 101213671 A CN101213671 A CN 101213671A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
一种制备薄膜晶体管的方法,其包括:(a)将包括半导体金属氧化物纳米粒子的分散体溶液沉积在衬底上,(b)烧结所述纳米粒子以形成半导体层,和(c)任选使得到的半导体层经沉积后处理。
Description
技术领域
本发明涉及利用金属氧化物纳米粒子制备电子器件的方法。
背景技术
有机半导体可在相对低的温度下加工,并从而与温度敏感性衬底如例如塑性衬底具有相容性。因而,作为具有使得可用于在以塑性衬底上制备的轻质、柔性、低成本电子产品为中心的不同应用中潜力的技术,有机电子器件(例如,有机薄膜晶体管(TFTs))受到关注。
然而,有机TFTs的性能通常不如无机TFTs如硅基TFTs的性能。此外,当置于某种环境(例如溶液法中的溶剂)下时,会降低有机半导体的质量。甚至一些有机半导体材料在标准大气条件下也是不稳定的。
可利用有机溶剂递送无机半导体材料的纳米粒子,一旦它们被烧结,则它们通常不受溶剂的影响。从而,在烧结的无机层顶部可用溶液法加工另外的TFT层。
发明概述
考虑到前述内容,我们认识到,需要一种制备稳定的无机电子器件的相对低温方法。
简言之,本发明的一个方面提供了一种制备电子器件的方法,其包括以下步骤:(a)将包括金属氧化物纳米粒子的分散体溶液沉积在衬底上,和(b)使所述纳米粒子经光或氧化处理,或其组合以形成器件层。
在另一个方面,本发明提供了一种制备TFT的方法,其包括以下步骤:(a)将包括半导体金属氧化物纳米粒子的分散体溶液沉积在衬底上,(b)烧结所述纳米粒子以形成半导体层,和(c)任选使得到的半导体层经沉积后处理。这里,“烧结”是指在低于它们熔点的温度下附聚纳米粒子。
仍在另一方面,本发明提供了利用本发明的方法制备的电子器件和TFTs。
本发明的方法使得可以在相对低的温度下生产基于金属氧化物的电子器件和TFTs。从而,本发明的方法使得可在温度敏感性衬底如塑性衬底上构造电子器件和TFTs。
由纳米粒子制备的半导体层相对不太稳定或对空气敏感(例如,参见美国专利6,294,401(Jacobson等)和Ridley等.Science,286,746(1999),其中必须在惰性气氛手套箱中制备由硒化镉纳米粒子制成的半导体层)。
然而,通常借助于有机配体或聚合物,可以将用于本发明方法中的金属氧化物纳米粒子分散到水或有机溶剂中。这使得所述金属氧化物纳米粒子可以通过溶液沉积法被递送到衬底。与其它材料(例如,硅、锗、和硒化镉)的半导体纳米粒子不同,金属氧化物纳米粒子具有对氧化稳定的额外优点。这种稳定性使得可在各种氧化性条件下处理所述金属氧化物纳米粒子,所述氧化性条件如空气、臭氧、原子态氧、或氧等离子体中。如果使用有机配体的话,这种氧化性条件可在相对低的温度下有效地从所述金属氧化物表面除去有机配体。所述纳米粒子的烧结也可以在相对低的温度下进行。
从而,本发明的方法满足了本领域对于制备稳定无机电子器件的相对低温方法的需要。
详细说明
制备电子器件的方法
本发明的方法可用于制备如下的电子器件,如电容器、晶体管(例如,结式晶体管或薄膜晶体管)、二极管(例如发光二极管)、光伏系统、传感器、太阳能电池和显示器。
本发明一种用于制备电子器件的方法包括:将含有金属氧化物纳米粒子的分散体溶液沉积在衬底上,和然后使所述纳米粒子经光或氧化或其组合处理,以形成器件层。所述器件层可以是器件的任何层,其中半导体的或导体的特性将是有用的。所述器件层可以例如是半导体层、电极层、导电迹线、电子传递层、空穴传递层、发光层等。优选,所述器件层是半导体层或电极层。
所述器件层由金属氧化物纳米粒子形成(即,具有0.1-100nm范围内的二维尺寸的金属氧化物粒子)。适当的金属氧化物包括二元、三元和四元的金属氧化物化合物。有用的二元金属氧化物包括,例如,ZnO,SnO2,In2O3,CdO,TiO2,Ga2O3,Cu2O,Ag2O,BeO,NiO,等。有用的三元金属氧化物包括,例如,AgInO2,AgSbO3,Cd2GeO4,CdIn2O4,Cd2Sb2O7,CdSnO3,Cd2SnO4,CuAlO2,CuInO2,CuGaO2,In4Sn3O12,MgIn2O4,SrCu2O2,ZnGa2O4,Zn2In2O5,Zn3In2O6,ZnSnO3,Zn2SnO4等。有用的四元金属氧化物包括,例如,InGaMgO4,InGaZnO4等。
本领域还已知,上述金属氧化物化合物的排列或构造顺序对于各种多型体或晶相可以是不同的,并且这种结构顺序决定了所述器件层电子特性。所述化合物采用的晶相例如取决于形成所述层的工艺和条件。也可以,例如通过沉积后处理控制内部缺陷。从而,取决于金属氧化物材料是如何加工或掺杂的,金属氧化物材料可以是半导电的或导电的。
所述器件层还可以由通常为绝缘材料的纳米粒子形成,所述绝缘材料被掺杂以使得它们成为半导电或导电材料。例如,可用大量(例如,10-30%)In2O3掺杂氧化锆(ZrO2)以使其成为半导电或导电材料,所述氧化锆当其在纯的和相对无缺陷的状态下是绝缘体。通过用原子如Nb掺杂,也可使得碱金属钛酸盐(例如,SrTiO3,BaTiO3,和CaTiO3)成为半导电的。
当需要半导体层时,优选所述的纳米粒子包括如下的金属氧化物,当作为单晶或薄膜测量时,通过范德堡方法估算的所述金属氧化物的霍耳迁移率大于约1cm2V-1s-1(更优选,大于约10cm2V-1s-1;最优选,大于约50cm2V-1s-1)。当需要导电层时,优选所述纳米粒子包括电阻率小于约10-2Ω-cm(更优选小于约10-3Ω-cm)的金属氧化物。
优选,由包括氧化锌或氧化锡或其组合的纳米粒子形成所述器件层;更优选,由包括氧化锌的纳米粒子形成所述器件层。对于某些应用,优选所述器件层是透明的。
一些金属氧化物如氧化锌和氧化锡纳米粒子是商购可得的。可利用各种化学方法(例如,参见Vayssieres,Adv.Mater.15,464(2003);Pacholski等,Angew.Chem.114,1234(2002);Games等,Langmuir 16,3764(2000);和Shim等,J.Am.Chem.Soc.123,11651(2001))或物理方法(例如,参见Yang等,Adv.Funct.Mater.12,323(2002);和Park等,Adv.Mater.14,1841(2002))合成金属氧化物纳米粒子。
优选,所述金属氧化物纳米粒子是利用金属有机前体法合成的。可以例如通过以下方法合成金属氧化物纳米粒子,首先通过金属有机前体的分解形成金属纳米粒子,然后氧化这样形成的纳米粒子(例如,参见Nayral等,Chem.Eur.J.6,4082(2000)关于氧化锡纳米粒子的制备;Soulantica等,Adv.Funct.Mater.13,553(2003)关于氧化铟纳米粒子的制备;和Rataboul等J.Organomet.Chem.643-644,311(2002)关于由Zn(c-C6H11)2制备氧化锌纳米粒子)。当所述金属有机前体是空气敏感性的并在空气中分解时,优选通过溶液中前体的控制氧化而合成所述金属氧化物纳米粒子(例如,参见Monge等,Angew.Chem.Int.42,5321(2003),其中通过使Zn(c-C6H11)2、配体和四氢呋喃的混合物在室温下缓慢蒸发而形成氧化锌纳米粒子;和参见Tang等,Nano Lett.543-548,5(2005),其中通过在室温下在有机溶液中使双-(环辛四烯)钛和二甲亚砜和配体反应而形成氧化钛纳米粒子)。
所述金属氧化物纳米粒子至少具有两个纳米尺度(即在0.1-100nm的范围内)上的维度。优选,所述纳米粒子在至少一个维度上小于50nm;更优选,所述纳米粒子在至少一个维度上小于10nm。它们可以具有不同的形状(例如,球形、杆状或纳米线)和可以是不同尺寸的。在一些应用中,优选可使用形状和/或尺寸的结合。例如,在一些应用中,纳米粒子的尺寸具有双峰或多峰分布是有利的,这样当它们被沉积时所述纳米粒子可以更紧密地“压紧”。
所述金属氧化物纳米粒子可以被分散在溶剂中并溶液沉积到衬底上。可使用所述纳米粒子可分散在其中并与所选的溶液沉积工艺相容的任何溶剂。任选,所述分散体可包括少量的添加剂,例如表面活性剂。通常,所述分散体包括小于约1wt%~大于约90wt%的纳米粒子。如本领域普通技术人员已知的,理想的浓度将取决于选择的溶液沉积方法而定。
可利用任何溶液沉积技术将所述分散体沉积在衬底上。例如,可通过旋涂法、浸渍涂布、凸凹涂布、凹版涂布或印刷技术如喷墨印刷、柔版印刷等沉积所述分散体。优选,通过旋涂或印刷技术沉积所述分散体。
所述衬底可以是支撑整个电子器件的衬底(“器件衬底”)或器件的另一层或部件。
在将金属氧化物纳米粒子的分散体沉积在所述衬底上之后,可蒸发溶剂,优选通过加热蒸发。通常有用的层厚为约5nm~约100nm。优选,得到的层厚为约15nm~约60nm。然而,如本领域普通技术人员已知的,最佳的层厚取决于形成的器件层类型和所述电子器件的最终用途而定。如果得到的层不够厚,可进行附加的溶液沉积。
然后所述干燥的纳米粒子层可经光(例如紫外光(UV)、可见光或红外光)或氧化处理,或其组合的处理。所述光和/或氧化处理结合或附聚所述纳米粒子以形成器件层。
通常,应使用被所述金属氧化物强吸收的波长的光。优选光的波长能量比金属氧化物的带隙能量更高。从而,对于多数金属氧化物,优选UV光。然而,对于一些金属氧化物如Cu2O,可见光是足够的。
例如可以通过受激准分子激光器、UV荧光(“黑光”)、杀菌光或254nm低压水银弧光灯而提供UV光。优选,所述干燥的纳米粒子层经光和臭氧处理。例如可通过185nm低压水银弧光灯提供UV/臭氧。
例如,可利用臭氧处理、置于原子态氧或氧等离子体之下而进行氧化处理。原子态氧和带负电荷的氧离子可作为氧等离子体产生的结果而产生,或者它们可以通过本领域已知的方法产生(例如,参见Tagawa等,AIAA Journal 32,95(1994))。可通过多种本领域已知方法产生氧等离子体(例如,参见,Finn,Engineering,Chemistry,and Use ofPlasma Reactors,American Institute of Chemical Engineers,New York,1971)。
例如利用喷墨印刷或掩模技术可将所述金属氧化物层图案化。为利用掩模技术进行图案化,可如上述沉积金属氧化物层。然后,通过光掩模将所述层的预定区域置于UV光下可图案化该层,所述光掩模仅根据所需图案允许光通过。将仅烧结置于所述光下的区域。然后可除去所述未烧结的区域(例如,用溶剂)。
在同一电子器件中可利用本发明方法制备多个器件层。例如,利用本发明方法制备的掺杂金属氧化物层可用作光伏器件中的透明电极。利用本发明方法制备的半导电层可用作同一光伏器件中作为半导体层,所述半导电层包括至少在一部分可见光谱中不透明的金属氧化物(如,Cu2O)。
可利用任何可以使用的方法制备所述电子器件的其他部件和层。
利用本发明方法制备的器件层看起来比通过其他方法制备的相同材料的层更具多孔性。从而,本发明的方法特别可用于制备传感器的传感层,例如目标气体传感器。
制备薄膜晶体管的方法
薄膜晶体管(TFTs)是一类特别有用的电子器件。TFTs通常包括晶体管衬底,在所述晶体管衬底上的栅电极,在所述栅电极上的栅介质,与所述栅介质毗邻的源极和漏极,和与所述栅介质毗邻并与所述源极和漏极毗邻的半导体层。这些部件可组装成各种构造。例如,所述源极和漏极可与所述栅介质相邻并用所述半导体层覆盖所述源极和漏极,或者所述半导体层可插入所述源极和漏极与栅介质之间。
本发明提供了一种制备TFTs的方法。本发明包括将包括半导电金属氧化物纳米粒子的分散体溶液沉积到衬底上,并烧结所述纳米粒子以形成半导体层。
根据本发明制备的TFTs可提供到衬底上(“晶体管衬底”)。所述晶体管衬底通常在生产、测试、和/或使用过程中支撑所述TFT。例如,可选择一种晶体管衬底用于测试和筛选各种实施方式,而选择另一种晶体管衬底用于工业实施方式。任选地,所述晶体管衬底可赋予所述TFT电气性能。有用的晶体管衬底材料包括有机和无机材料。例如,所述晶体管衬底可包括无机玻璃、陶瓷箔、聚合物材料(例如,丙烯酸类、环氧类、聚酰胺类、聚碳酸酯类、聚酰亚胺类、聚酮类、聚(氧-1,4-亚苯基氧-1,4-亚苯基羰基-1,4-亚苯基)(有时称作聚(醚醚酮)或PEEK),聚降冰片烯,聚苯醚,聚萘二甲酸乙二醇酯(PEN),聚对苯二甲酸乙二醇酯(PET),聚苯硫醚(PPS)),填充聚合物材料(例如,纤维增强的塑料(FRP)),纤维材料,如纸和纺织品,和涂覆或未涂覆的金属箔。优选所述晶体管衬底包括聚合物材料。
柔性晶体管衬底可用于本发明。柔性晶体管衬底使得可进行辊处理,其可以是连续的,从而提供了规模经济和在平的和/或刚性衬底上生产的经济性。优选选择所述柔性晶体管衬底,使其能够卷绕在直径小于约50cm的(优选直径小于约25cm;更优选直径小于约10cm;最优选直径小于约5cm;)圆筒周围,而不会变形或破裂。用于将本发明所述柔性晶体管衬底卷绕至特定圆筒上的所用的力通常较低,如通过徒手操作(即,不借助于杠杆、机械、水力学等)。优选的柔性晶体管衬底可自动卷起。
TFT的栅电极可以是任何有用的导电材料。例如,所述栅电极可以包括掺杂的硅,或金属,如铝、铜、铬、金、银、镍、钯、铂、钽、和钛,和透明的导电氧化物如铟锡氧化物或掺杂的氧化锌(例如铝掺杂的氧化锌或镓掺杂的氧化锌)。
也可以使用导电聚合物,例如,聚苯胺或聚(3,4-二氧乙基噻吩)/聚(苯乙烯磺酸钠)(PEDOT:PSS)。此外,可使用这些材料的合金、混合物和多层。在一些TFTs中,同一材料可提供栅电极作用并同样提供晶体管衬底支撑性能。例如,掺杂的硅可作为栅电极和支撑TFT的作用。
所述栅介质使得栅电极和TFT器件的其他部分电绝缘。栅介质的相对介电常数优选大于约2(更优选,大于约5)。所述栅介质的介电常数可以相对较高,例如为80~100或更高。可用于所述栅介质的材料可包括,例如,有机或无机电绝缘材料。
可用于栅介质的有机材料的具体例子包括:聚合物材料,如聚偏氟乙烯(PVDF),氰基纤维素,聚酰亚胺,环氧化物等。其他有用的有机材料记载于共同未决的申请USSN10/434,377中,其于2003年5月8日提交。
可用于栅介质的无机材料的具体例子包括:氧化锶、钽酸盐、钛酸盐、锆酸盐、氧化铝、氧化硅、氧化钽、氧化钛、氮化硅、钛酸钡、钛酸锶钡、和钛酸锆酸钡。此外,可利用这些材料的合金、混合物和多层用作所述栅介质。
TFT的源极和漏极通过栅介质与栅电极隔开,同时所述半导体层可在所述源极和漏极之上或之下。源极和漏极可以是任何有用的导电材料。有用的材料包括大多数上述对于栅电极所述的那些材料,例如,铝、钡、钙、铬、铜、金、银、镍、钯、铂、和钛,透明的导电氧化物如铟锡氧化物或掺杂的氧化锌(例如铝掺杂的氧化锌或镓掺杂的氧化锌),聚苯胺,PEDOT:PSS,其他导电聚合物,其合金、其混合物和其多层。
可通过任何有用的方法提供所述薄膜电极(即,栅电极、源极和漏极),如,通过镀、喷墨印刷或气相沉积(例如,热蒸发或溅镀)。可通过已知方法实现所述薄膜电极的图案化,所述方法如孔眼掩模、附加光刻法、消减光刻法、印刷、微接触式印刷和图案化涂布。可通过任何有用的方法提供所述栅介质,例如气相沉积或等离子体沉积。
根据本发明方法,由半导电的金属氧化物纳米粒子形成制得的TFT的半导体层(即,半导电金属氧化物粒子至少具有两个在0.1-100nm范围内的维度)。优选,所述纳米粒子至少在一个维度上小于50nm;更优选,小于10nm。
适当的半导电金属氧化物包括,例如,上述列出的二元、三元和四元金属氧化物化合物。
也可由通常为绝缘材料的纳米粒子形成所述半导体层,所述绝缘材料被掺杂以使得它们成为半导电材料。例如,氧化锆(ZrO2),当其在纯的和相对无缺陷的状态下是绝缘体,可用In2O3掺杂使其成为半导电材料。也可通过用原子如Nb掺杂使得碱金属钛酸盐(例如,SrTiO3,BaTiO3,和CaTiO3)成为半导电的。
优选所述的纳米粒子包括如下的金属氧化物,当作为单晶或薄膜测量时,通过范德堡方法估算的所述金属氧化物的霍耳迁移率大于约1cm2V-1s-1(更优选,大于约10cm2V-1s-1;最优选,大于约50cm2V-1s-1)。
优选,所述半导体层由包括氧化锌或氧化锡或其组合的纳米粒子形成;更优选,所述半导体层由包括氧化锌的纳米粒子形成。
优选,例如如上述讨论的金属有机前体法合成所述金属氧化物纳米粒子。
所述半导体层金属氧化物纳米粒子可以具有不同的形状(例如,球形、杆状或纳米线)并可以是不同尺寸的。在一些应用中,优选使用形状和/或尺寸的结合。例如,在一些应用中,纳米粒子的尺寸具有双峰或多峰分布是有利的,这样当它们被沉积时所述纳米粒子可以更紧密地被“压紧”。
所述金属氧化物纳米粒子可以被分散在溶剂中并溶液沉积到衬底上。可利用任何溶液沉积技术将所述分散体沉积在衬底上。例如,可通过旋涂法、浸渍涂布、凸凹涂布、凹版涂布或印刷技术如喷墨印刷、柔版印刷等沉积所述分散体。优选,通过旋涂或印刷技术沉积所述分散体。
在其上沉积所述半导体层的“衬底”可以是晶体管衬底或器件的另一层或部件。例如,在一些TFT构造中,将半导体层沉积在栅介质上(即,栅介质是“衬底”),并将源极和漏极沉积在半导体层上。在其他构造中,将源极和漏极沉积在所述栅介质上,并将半导体层沉积在栅介质与源极和漏极上(即,栅介质和源极和漏极是“衬底”)。所述衬底还可以是任选的TFT层,如密封层或表面处理层。
任选地,在将金属氧化物纳米粒子的分散体沉积到所述衬底上之后,可蒸发溶剂,优选利用热蒸发。通常,得到的层厚可以在约5nm~约100nm之间(优选,在约15nm~约60nm之间)。然而,如本领域普通技术人员已知的,最佳的层厚取决于形成的器件层类型和所述电子器件的最终用途而定。如果得到的层不够厚,可进行附加的溶液沉积。
然后可烧结所述纳米粒子层。可利用在低于它们熔点的温度下附聚所述纳米粒子的任何方法完成所述烧结。例如,可利用热、光(例如紫外光、可见光或红外光)或氧化处理(例如,臭氧处理、置于原子态氧或氧等离子体下)、或其组合(例如,紫外/臭氧处理或脉冲热处理)完成烧结。
例如,可利用加热炉完成所述加热烧结。当利用加热时,通常在低于所述金属氧化物熔点约2/3的温度进行烧结。优选,在低于约300℃的温度进行烧结;更优选,低于约150℃。
当利用光进行烧结时,应采用被所述技术氧化物强吸收的波长的光。优选光的波长能量比金属氧化物的带隙能量更高。对于多数金属氧化物,优选UV光。
原子态氧和带负电荷的氧离子可作为氧等离子体产生的结果而产生,或者它们可以通过本领域已知的方法产生(例如,参见Tagawa等,AIAA Journal 32,95(1994))。
可通过多种本领域已知方法产生氧等离子体(例如,参见,Finn,Engineering,Chemistry,and Use of Plasma Reactors,American Instituteof Chemical Engineers,New York,1971)。
优选,利用热、紫外光和/或臭氧处理的组合进行烧结;更优选,利用所有三种的组合。紫外光/臭氧可例如利用185nm低/中压汞灯提供。也可利用高密度红外等离子弧用于脉冲热处理(例如,参见Ott等,JOM 45-47,56(2004))。
任选的,得到的半导体可经沉积后处理以改进其半导电性能。一些金属氧化物层,例如氧化锡层可能不会表现出令人满意的用作TFT半导体层的半导电性能,除非使它们经沉积后处理。沉积后处理可以包括,例如,在空气中退火,在形成气体(例如,约5%H2和约95%氮气或氩气等)中退火,用原子态氢处理,或在环境条件下老化(优选,在形成气体中退火)。
这里,“退火”是指加热至高于环境温度。通常,退火包括加热至高于环境温度的温度,但低于所述金属氧化物熔点的约2/3。优选,在低于约300℃下进行退火;更优选低于约150℃。
置于原子态氢(H)可例如降低金属氧化物层至过量的氧原子浓度。例如可通过H2和加热的钨催化剂在催化化学气相沉积设备中的催化反应而产生原子态氢(例如,参见Tabuchi等,Jpn.J.Appl.Phys.5060-5063,41(2002))。
当在环境条件下老化时,通常将所述半导体层老化至少1天;优选,至少7天。
可在形成所述半导体层之后立即进行沉积后处理(即在所述半导体层上沉积气体TFT层或部件之前),或者,如果要保留至少一部分所述半导体层露出的情况下,在将其他TFT层或部件沉积到半导体层上之后进行沉积后处理。也可在将其他的TFT层或部件沉积到所述半导体层之后或完成TFT时进行第二沉积后处理。如果在沉积源极和漏极之前进行第一沉积后处理,则优选,使得到的TFT(即完成的)经第二沉积后处理。
也可利用沉积后处理以改进其他器件层(例如,利用本发明用于制备器件层的方法制备的器件层,或利用其他方法制备的器件层)的性能。还可使器件层经氢等离子体处理,以改进传导率。
实施例
通过以下实施例进一步说明本发明的目的和优点,但是这些实施例所引用的具体材料和量以及其他条件和细节不应构成对本发明的不当限制。
实验测量
膜厚
利用单波长椭圆偏振仪得到聚合物层厚的估值。在50°和70°的入射角和632.8nm的波长处,利用Gaertner Dual Mode AutomaticEllipsometer,model Ll 16A(Gaertner Co.Skokie,Illinois),由清洁后的衬底(下文描述)得到Ψ和δ(ψs和Δs)的衬底值。将ZnO纳米粒子层应用到所述衬底上(下文描述),并测量值(ψf和Δf)。
利用椭圆偏振仪建模软件,WVASE32(来自J.A.Woollam,Inc.Lincoln,Nebraska)来构建适用于所研究的具体衬底的光学模型。除非另外指明,所述程序中包括了材料的光学常数。
对于硅衬底上的热氧化,所述光学模型由位于硅衬底顶部的在50的混合层上的1000的SiO2构成(Bruggeman有效介质模拟由50%SiO2和50%Si构成)。拟合的浮点数变量是SiO2的厚度和混合层厚度。通常拟合值是950-990 SiO2,10-60混合层。
对于在硅衬底上的氧化铝层,所述光学模型是Si上1500的Al2O3。拟合浮点数变量是Al2O3的以埃(d)表示的厚度和折射率(n)。利用d=1500和n=1.77的晶种值。通常最终拟合值在1400~1700之间,n在1.56~1.60之间。
一旦通过ψs和Δs建模确定了衬底参数,即将它们固定并将层加到光学模型上以代表位于空气和电介电层之间的ZnO层。该层的厚度和折射率均可变。利用WVASE32程序找到允许对ψf和Δf最佳拟合的厚度和折射率值。
薄膜半导体性能
利用本领域已知的技术,例如S.M.Sze,Physics of SemiconductorDevices,page 442,John Wiley&Sons,New York,1981中所述,在空气中在室温下测试半导体性能。利用Semiconductor Parameter Analyzer(型号4145A,来自Hewlett-Packard,Palo Alto,California)以得到以下结果。
将漏电流(Id)的平方根作为栅源偏置(Vg)的函数作图,对于+40V的恒定源极漏极偏置(Vd)为-10V~+40V,并利用栅介质的比电容、沟道宽度和沟道长度,由该曲线的直线部分计算饱和场效应迁移率。采用该直线拟合的x轴外推法作为阈电压(Vt)。此外,将Id作为Vg的函数作图,得到其中沿所述曲线含有Vt的部分引出直线拟合的曲线。该线斜率的倒数是亚阈值斜率(S)。占空比取作Id-Vg曲线的最小和最大漏电流(Id)值的差。
材料
制备实施例A-二异丙基锌衍生的ZnO纳米粒子质点
在惰性气氛手套箱中,将二异丙基锌(2.1mmol,2.1ml在甲苯中的1.0M溶液,可得自Aldrich,Milwaukee,WI)加入到无水的未稳定化的四氢呋喃(THF,47.5ml,Aldrich)中并搅拌。加入辛胺(2.1mmol,0.35ml,得自Aldrich),并将溶液在惰性气氛下搅拌31/2小时。然后从惰性气氛中取出溶液,打开容器盖,使THF蒸发至干。然后,通过搅拌和超声波处理相结合,将粒子分散到40ml的THF中。随后,通过配备有1微米玻璃膜的针头式过滤器(Acrodisc 4524,可得自Pall LifeSciences,East Hills,NY)过滤所述分散体,然后通过配备有玻璃膜的针头式过滤器(AP1502500,可得自Millipore,Billerica,MA)。接着,通过旋转蒸发器除去THF。进一步在真空系统(20毫托)上干燥所述粒子。X-射线衍射(XRD)和透射电子显微镜(TEM)证实了纳米粒子的存在。
制备实施例B-二苯基锌衍生的ZnO纳米粒子点
在手套箱中,将二苯基锌(2.1mmol,0.461g,可得自Alfa Aesar,Ward Hill,MA)加入到无水的未稳定化的四氢呋喃(THF,49.5ml,Aldrich)中并搅拌。加入辛胺(2.1mmol,0.35ml,得自Aldrich),并将溶液在惰性气氛下搅拌31/2小时。然后从惰性气氛中取出溶液,打开容器盖,使THF蒸发至干。然后,通过搅拌和超声波处理相结合,将粒子分散到40ml的THF中。随后,通过配备有1微米玻璃膜的针头式过滤器(Acrodisc 4524,Pall Life Sciences)过滤所述分散体。接着,通过旋转蒸发器除去THF。进一步在真空系统(20毫托)上干燥所述粒子。XRD和TEM证实了纳米粒子的存在。
制备实施例C-二乙基锌衍生的ZnO纳米粒子点
在手套箱中,将二乙基锌(4.2mmol,4.2ml在己烷中的1.0M溶液,Aldrich)加入到100ml无水的未稳定化的THF中。加入辛胺(4.2mmol,0.69ml,Aldrich),并将溶液在惰性气氛下搅拌31/2小时。然后从惰性气氛中取出溶液,打开容器盖,使THF蒸发至干。然后,通过搅拌和超声波处理相结合,将得到的粒子分散到120ml的THF中。随后,通过配备有1微米玻璃膜的针头式过滤器(Acrodisc 4524,Pall LifeSciences)过滤所述分散体,接着通过配备有0.2微米PTFE膜的针头式过滤器(Acrodisc 4225,Pall)过滤。通过旋转蒸发除去THF,并进一步在真空系统上干燥所述样品(20毫托,1小时)。XRD和TEM证实了纳米粒子的存在。
制备实施例D-二乙基锌衍生的ZnO纳米粒子点
在手套箱中,将二乙基锌(21mmol,21ml在己烷中的1.0M溶液,Aldrich)加入到22.5ml无水的未稳定化的THF中。加入辛胺(0.42mmol,3.47ml,Aldrich),并将溶液在惰性气氛下搅拌3小时。然后从惰性气氛中取出溶液。将溶液的容器置于水浴中,以保持溶液的温度处于室温下或接近室温。打开容器的盖子,使THF蒸发至干。通过加入50ml的THF生成浆体。用更多THF稀释所产生的浆体的一部分,使浓度降低10倍的。然后通过1微米玻璃膜(Acrodisc 4524,Pall Life Sciences)过滤,并通过旋转蒸发进一步降低浓度以形成糊状物。
将一部分所述糊状物置于50ml圆底烧瓶中并挥发,通过Kugelrohr装置(70℃,20毫托)除去辛胺。用6ml甲乙酮(MEK)再浆化剩余的粒子,并再次通过Kugelrohr装置(80℃,20毫托)挥发除去。通过Kugelrohr重复第二次加入和除去MEK的操作。加入约2.6g的带有残留的辛胺涂层的ZnO粒子。加入38.5ml MEK,通过搅拌、加热至40℃和超声波处理相结合,将粒子分散。随后,通过配备有1微米玻璃膜的针头式过滤器(Acrodisc 4524,Pall Life Sciences)过滤所述分散体,接着通过配备有0.45微米PTFE膜的针头式过滤器(Acrodisc 4219,Pall)过滤。干透样品的XRD和TEM证实了氧化锌纳米棒的存在,棒为34±12nm长×6.3±1.6nm直径。
薄膜晶体管的制备
衬底的制备
单晶<100>取向重掺杂硅晶片,得自Silicon Valley Microelectronics,San Jose,California。通过化学气相沉积,将1500的氧化铝层(晶片A),或1000的高温热解二氧化硅层(晶片B)沉积在各晶片前侧。将5000的铝金属层气相沉积在各晶片的后侧上。在该示例中,在制备薄膜晶体管时,覆盖有铝的掺杂晶片用作栅电极,而氧化铝或二氧化硅用作栅介质。
将所述晶片衬底分成小片,并通过依次在庚烷、丙酮、2-丙醇中漂洗而进行清洁,并用过滤的氮气流吹干。然后通过置在UV/臭氧室内10分钟对其进行进一步清洁。
半导体涂布方法
用金属氧化物纳米粒子的分散体对所述清洁的镀介质硅晶片进行旋涂。然后通过在烤盘上短暂加热所述晶片而干燥所述层。然后利用椭圆偏振仪检查层厚。如果其小于30nm,则进行第二旋涂和加热循环。
在烘干以驱除溶剂后,烧结所述衬底上的纳米粒子层,通常通过在加热炉中在空气中加热或者通过置于UV光和该光产生的臭氧下,或者通过受激准分子激光器提供的UV光产生。这之后,通过椭圆偏振仪检查烧结后的层厚和折射率。
源极和漏极沉积方法
通过荫罩(如在美国专利No.6,897,164(Baude et al)中教导的柔性聚合物荫罩)截取将源极和漏极沉积在ZnO-涂布的晶片上,并将其装载入物理气相沉积室内。首先,沉积5nm的钙,随后沉积100nm的铝,如通过石英晶体微天平测得的。器件尺寸为20-110微米沟道长度×1000微米沟道宽度。然后如上测试器件。
沉积后处理
有时将如上产生的器件经沉积后处理,如在空气中退火,在形成气体中退火,或在周围环境下老化。然后如上述指出的再次对其进行测试。
实施例
对于下面列出的实施例1-30,制备1-10的器件。从而,当制备并测试多于一个器件时,记录于表1-6中的结果是平均的结果。
实施例1
收集足够的辛胺涂覆的二异丙基锌衍生的ZnO纳米粒子点(来自制备实施例A),并分散在MEK中以形成15mg ml-1的分散体。在1000rpm下将该分散体旋涂在清洁的晶片B上。然后在100℃在烤盘上烘干其10分钟。然后将该晶片分成四片。在Vulcan 3-550(Ney,Yucaipa,CA)加热炉中,在四种温度(300,500,700或900℃)之一下单独加热各片。将所述晶片置于该炉中,并以20℃min-1从室温升温,以达到特定的加热温度。保持炉在特定温度下1小时,然后使其冷却至室温。沉积顶接点,测试器件,结果记录于表1中。
实施例2
收集足够的辛胺涂覆的二苯基锌衍生的ZnO纳米粒子点(来自制备实施例B),并分散在MEK中以形成25mg ml-1的分散体。在2000rpm下将该分散体旋涂在清洁的晶片B上。将所述晶片置于炉中,并以10℃min-1从室温升温,以达到300℃的加热温度。保持炉在300℃下1小时,然后使其冷却至室温。沉积顶部接点,测试器件,结果记录于表1中。
实施例3和4
通过将晶片放入插入管式炉(Barnstead International,ThermolyneModel 79500,Dubuque,Iowa)内的石英管中的玻璃管内,完成完整TFT器件(实施例1和2)的形成气体处理。形成气体(N2中的5%H2)流入该管内。该管引出端与压力控制器(J-KEM Scientific,Digital VacuumRegulator Model 200,St.Louis,MO)相连,所述压力控制器与真空泵相连。设置该压力控制器以保持压力在500托。将管式炉加热至300℃。达到该温度后,保持2小时。然后在流动的形成气体(FG)下,将该炉冷却至室温。随后移出器件。
表1:在其上旋涂烧结的氧化锌纳米粒子的器件特性
晶片B
实施例 | 空气焙烧温度℃ | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
1 | 300 | 无 | 2.8 | 3×104 | 4×10-5 | 10 |
3 | 300 | FG | 1.4 | 9×105 | 1.5×10-3 | 19 |
2 | 300 | 无 | 13 | 3 | 4×10-6 | -25 |
4 | 300 | FG | 5 | 8000 | 5×10-5 | 10 |
1 | 500 | 无 | 11 | 100 | 0.08 | -43 |
3 | 500 | FG | 150 | 3 | 0.026 | -130 |
1 | 700 | 无 | 4.9 | 5000 | 0.4 | -19 |
3 | 700 | FG | 17 | 73 | 1.10 | -33 |
实施例5
收集足够的辛胺涂覆的二异丙基锌衍生的ZnO纳米粒子点(来自制备实施例A),并分散在MEK中以形成15mg ml-1的分散体。在1000rpm下将该分散体旋涂在清洁的晶片A上。然后在100℃在烤盘上烘干其10分钟。然后将该晶片分成四片,并如实施例1中的晶片进行焙烧,除利用10℃min-1的加热速率外。结果在表2给出。
实施例6
收集足够的辛胺涂覆的二苯基锌衍生的ZnO纳米粒子点(来自制备实施例B),并分散在MEK中以形成25mg ml-1的分散体。在2000rpm下将该分散体旋涂在清洁的晶片A上。将所述晶片置于炉中,并以10℃min-1从室温升温,以达到300℃的加热温度。保持炉在300℃下1小时,然后使其冷却至室温。沉积顶部接点,测试器件,结果记录于表2中。
实施例7和8
利用与实施例3中使用的基本相同的方法,使实施例5和6的器件经形成气体处理。
表2:在其上旋涂烧结的氧化锌纳米粒子的器件特性
晶片A
实施例 | 空气焙烧温度℃ | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
5 | 300 | 无 | 6.4 | 600 | 8×10-7 | -3 |
7 | 300 | FG | N/A | N/A | N/A | N/A |
6 | 300 | 无 | 32 | 2.6 | 9×10-7 | -31 |
8 | 300 | FG | 6 | 4000 | 4×10-4 | -2 |
5 | 500 | 无 | 19 | 47 | 4×10-4 | 0 |
7 | 500 | FG | 24 | 49 | 7×10-5 | 3 |
5 | 700 | 无 | 39 | 6 | 2×10-4 | -30 |
7 | 700 | FG | 50 | 19 | 5×10-3 | -70 |
5 | 900 | 无 | 14 | 1000 | 2.5×10-3 | 13 |
7 | 900 | FG | 22 | 200 | 0.025 | 1 |
实施例9(实施例10和11的准备)
收集足够的辛胺涂覆的二乙基锌衍生的ZnO纳米粒子点(来自准备实施例C),并分散在MEK中以形成25mg ml-1的分散体。在2000rpm下将该分散体旋涂在清洁的晶片B上。然后在150℃在烤盘上烘干其3分钟。然后将该晶片分成四片,形成实施例10和实施例11。
实施例10
以10℃min-1加热样品和炉,在300℃烘焙该晶片1小时。加热之后,使晶片和炉冷却至室温。沉积源极和漏极,测试片。结果记录于表3中。
实施例11
将该晶片置于利用臭氧发生格栅灯(part 88-9102-02,BHKIncorporated,Claremont,CA)的嵌入式UV-臭氧清洁室的小三角架上。所述臭氧发生格栅灯发出185nm和254nm和更低强度、更长波长的光。利用UV Power Puck Radiometer(UV Process Supply,Chicago,IL)测量所述254nm发光的强度。调整所述三角架使得辐射计传感器比灯反射器壳的边缘低10mm。测得所述UV-C(250-260nm)波段剂量为6.4mW每平方厘米。调整所述三角架使得所述晶片与固定灯的反射器壳的边缘距离为10mm。使氧气以4.2标准公升/分钟的速度流入室内。使所述晶片置于UV光和其中产生的臭氧下30分钟。从UV-O3室内取出晶片,然后沉积源极和漏极,并如上述测试所述片。结果记录于表3。
实施例12和13
如实施例3中那样,在形成气体中处理来自实施例10和11的晶片,除了将管式炉设定为150℃外。通过冷却,取出并测试所述晶片。结果记录于表3。
表3:在其上旋涂烧结的氧化锌纳米粒子的器件特性
晶片B
实施例 | 烧结方法 | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
10 | 300℃ | 无 | 4.5 | 126 | 0.00066 | -7.6 |
11 | UV-臭氧 | 无 | 1.7 | 900 | 0.007 | -7 |
12 | 300℃ | FG | 3.0 | 3700 | 0.0006 | -3 |
13 | UV-臭氧 | FG | 3.4 | 1.3×104 | 0.0039 | 5 |
实施例14-18
如上述清洁两片晶片B。然后用25mg ml-1的二乙基锌衍生的纳米粒子点的分散体(来自准备实施例C)以2000rpm对其进行旋涂。然后在150℃在烤盘上加热所述晶片3分钟。随后进一步将所述晶片分割成4小片,用于用UV受激准分子激光器系统进行处理。所述受激准分子激光器由Resonetics制造,包括OPTex Kr.F受激准分子激光器(由Lambda Physik生产)。所述激光器提供248nm的短强脉冲。调整体系的光学器件使得它可在1.1cm×1.5cm的区域内产生1.5mJ cm-2的脉冲。以50脉冲/秒的速率,用50、100、1000、10,000、或65,535的脉冲处理各晶片。在用受激准分子激光器处理之后,沉积源极和漏极。初始测试表明样品没有表现出n沟道TFT性能。然后如在实施例12中那样,在150℃在形成气体中处理所述晶片2小时。结果在表4中给出。
表4:晶片B上的基于UV受激准分子激光器处理的ZnO纳米粒子的TFT的器件特性
实施例 | 处理(激光脉冲) | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
14 | 50 | FG | 10.0 | 200 | 2.0×10-6 | 6 |
15 | 100 | FG | 19 | 12 | 9×10-6 | -6 |
16 | 1000 | FG | 8 | 1000 | 6×10-6 | 8.9 |
17 | 10,000 | FG | 7 | 700 | 1.8×10-4 | 2.2 |
18 | 65,535 | FG | 6 | 61 | 0.00016 | -5.5 |
实施例19和20
用Kugelrohred二乙基锌衍生的ZnO纳米棒(来自准备实施例D)的分散体,在500rpm旋涂晶片A和晶片B片6秒,然后在2000rpm旋涂60秒。然后在150℃在烤盘上烘焙该晶片3分钟。然后如实施例11那样,在相同条件下,在UV-臭氧室内处理所述ZnO层。沉积源极和漏极,并如上述测试所述器件。结果见表5。
对于晶片B上的样品,通常利用Vd=40V和-10V<Vg<40V进行扫描产生反向I-V曲线,其不会回到它们开始的相同断电流(offcurrent)(通常它们在Id中为100x或更高)。这表明在正向测得的器件参数将不是器件性能的准确表征。然而,仅以5V的Vd,所述器件不能适当地表现。这产生了0.00048cm2V-1s-1的迁移率。
实施例21
将实施例19中所用的晶片小片(含有源极和漏极)切碎,并在环境大气中在用晶片盘盖(Entegris H22-201-0615)密封的晶片盘(EntegrisH22-20-0615,Chaska,Minnesota)中老化7天。然后再次测试。结果在表5中给出。老化器件似乎具有改进的性能。
实施例22
在150℃下,将实施例21的老化晶片在空气中在烤盘上退火30分钟。结果在表5给出。
实施例23
在其150℃的退火之后,使实施例22的晶片老化一周。再次测试其。结果在表5中。
实施例24
将实施例21中所用的晶片破碎成若干片,使得它们在其上均具有源极和漏极接点。在150℃,将一片在空气中的烤盘上退火30分钟。再次测试其。结果在表5给出。
实施例25
在300℃下,将实施例24中所用的晶片在空气中在烤盘上退火30分钟。结果在表5给出。
实施例26和27
将实施例19和实施例20中所用的晶片破碎成小片,使得它们在150℃经形成气体处理2小时,基本如实施例12所述。结果在表5给出。
实施例28和29
在形成气体中处理后,在环境条件下,使实施例26和实施例27中所用的样品密封在实验台上带有盖子的晶片盘(参见实施例21)中老化118天。然后再次测试它们。结果见表5。
表5:基于UV-臭氧处理的ZnO纳米棒的TFT的器件特性
晶片A
实施例 | 晶片 | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
19 | A | 无 | 3.98 | 487 | 0.000484 | -2.64 |
20 | B | 无 | 2.5 | 500 | 0.0119 | -3.0 |
21 | A | 环境条件下老化7天 | 2.6 | 2×105 | 0.0034 | 17 |
22 | A | 环境条件下老化7天,150℃下30分钟 | 1.9 | 5×105 | 0.017 | 12 |
23 | A | 环境条件下老化7天,150℃下30分钟,和环境条件下老化7天 | 1.5 | 8×105 | 0.013 | 15 |
24 | B | 150℃下30分钟 | 4.2 | 2900 | 0.010 | 5 |
25 | B | 150℃下30分钟,300℃下30分钟 | 21 | 25 | 12×10-6 | 3 |
26 | A | FG | 8.4 | 1100 | 0.031 | 4 |
27 | B | FG | 7 | 3000 | 0.030 | 6 |
28 | A | FG和环境条件下老化118天 | 4.3 | 1.0×104 | 0.0147 | 9.8 |
29 | B | FG和环境条件下老化118天 | 4.1 | 1.6×104 | 0.0148 | 10.9 |
实施例30
利用Spectra/Por 2 Dialysis Membrane(Spectrum Labs,Los Angeles,CA)将商购可得的氧化锡溶胶(Nyacol SN1 5ES,Nyacol NanoTechnologies,Inc.Ashland,MA)相对于蒸馏水透析1周。在透析之后,用等重量的水稀释所述溶胶。然后通过1微米玻璃滤器膜(Acrodisc4524,Pall Life Sciences)过滤所述溶胶。
如上述清洁晶片B的样品。在2000rpm下,将所述透析的氧化锡分散体旋涂在所述晶片上。然后基本与如上所述的相同方式UV-O3处理所述样品30分钟。测试沉积的Ca/Al电极和器件。没有观察到晶体管性能。然后使所述晶片在150℃经形成气体处理2小时。
表6:晶片B上基于UV-臭氧烧结的SnO2纳米粒子的TFT的器件特性
晶片B
实施例 | 沉积后处理 | 亚阈斜率,V/十进位 | 占空比 | 迁移率,cm2V-1s-1 | 阈电压,V |
30 | FG | 4 | 1×105 | 1.4×10-4 | 8 |
对于本领域普通技术人员而言,不偏离本发明的范围和精神,本发明的各种改变和变换形式将是显而易见的。应理解,本发明不应不当地受限于本文给出的说明性实施方式和实施例,这些实施例和实施方式仅为举例方式给出,本发明的范围仅受到本文随后所附的权利要求的限制。
Claims (35)
1.制备薄膜晶体管的方法,其包括:
(a)将包括半导体金属氧化物纳米粒子的分散体溶液沉积在衬底上,
(b)烧结所述纳米粒子以形成半导体层,和
(c)任选使得到的半导体层经沉积后处理。
2.权利要求1所述的方法,其中所述纳米粒子包括氧化锌或氧化锡,或其组合物。
3.权利要求2所述的方法,其中所述纳米粒子包括氧化锌。
4.权利要求1所述的方法,其中所述纳米粒子包括掺杂的绝缘材料。
5.权利要求1所述的方法,其中所述纳米粒子包括霍耳迁移率大于约1cm2V-1s-1的金属氧化物。
6.权利要求5所述的方法,其中所述纳米粒子包括霍耳迁移率大于约10cm2V-1s-1的金属氧化物。
7.权利要求1所述的方法,其中所述纳米粒子包括透明的金属氧化物。
8.权利要求1所述的方法,其中所述纳米粒子利用金属有机前体法合成。
9.权利要求1所述的方法,其中所述分散体包括具有双峰或多峰分布尺寸的纳米粒子。
10.权利要求1所述的方法,其中通过旋涂或印刷技术沉积所述分散体。
11.权利要求1所述的方法,其中所述衬底是介电层。
12.权利要求1所述的方法,其中所述薄膜晶体管包括聚合物晶体管衬底。
13.权利要求12所述的方法,其中所述薄膜晶体管包括柔性聚合物晶体管衬底。
14.权利要求1所述的方法,其中利用热、光或氧化处理、或其组合进行烧结。
15.权利要求14所述的方法,其中利用UV光或臭氧处理、或其组合进行烧结。
16.权利要求14所述的方法,其中利用热、UV光和臭氧处理的组合进行烧结。
17.权利要求14所述的方法,其中利用热进行烧结。
18.权利要求14所述的方法,其中利用脉冲热处理进行烧结。
19.权利要求1所述的方法,其中在低于约300℃的温度下进行烧结。
20.权利要求19所述的方法,其中在低于约150℃的温度下进行烧结。
21.权利要求1所述的方法,其中使得到的半导体层经沉积后处理。
22.权利要求21所述的方法,其中使得到的薄膜晶体管经第二沉积后处理。
23.权利要求21所述的方法,其中得到的薄膜晶体管在空气中退火、在形成气体中退火、用原子态氢处理、或在环境条件下老化。
24.权利要求23所述的方法,其中得到的薄膜晶体管在形成气体中退火。
25.一种制备电子器件的方法,其包括:
(a)将包括金属氧化物纳米粒子的分散体溶液沉积在衬底上,和
(b)使所述纳米粒子经光或氧化处理,或其组合以形成器件层。
26.权利要求25所述的方法,其中所述纳米粒子包括氧化锌或氧化锡,或其组合。
27.权利要求25所述的方法,其中所述纳米粒子包括掺杂的绝缘材料。
28.权利要求25所述的方法,其中所述纳米粒子包括霍耳迁移率大于约1cm2V-1s-1或电阻率小于约10-2Ω-cm的金属氧化物。
29.权利要求25所述的方法,其中所述纳米粒子包括透明的金属氧化物。
30.权利要求25所述的方法,其中将所述纳米粒子置于UV光下以形成器件层。
31.权利要求25所述的方法,其中所述器件层是半导体层或电极层。
32.权利要求25所述的方法,其中将所述纳米粒子置于UV光和臭氧下以形成器件层。
33.权利要求25所述的方法,其中所述电子器件是传感器。
34.薄膜晶体管,其包括通过权利要求1的方法制备的半导体层。
35.电子器件,其包括通过权利要求25的方法制备的半导体层或电极层。
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US11/167,800 US7507618B2 (en) | 2005-06-27 | 2005-06-27 | Method for making electronic devices using metal oxide nanoparticles |
PCT/US2006/024377 WO2007044098A1 (en) | 2005-06-27 | 2006-06-22 | Method for making electronic devices using metal oxide nanoparticles |
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CN106098787A (zh) * | 2010-02-16 | 2016-11-09 | 株式会社理光 | 场效应晶体管、显示元件、图像显示设备和系统 |
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CN103000297A (zh) * | 2011-09-15 | 2013-03-27 | 中国科学院生态环境研究中心 | 一种在低温下制备纳米金属氧化物半导体薄膜电极的方法 |
CN105244283A (zh) * | 2015-10-26 | 2016-01-13 | 华南理工大学 | 紫外微图形化氧化物薄膜的制备方法及薄膜晶体管 |
CN105244283B (zh) * | 2015-10-26 | 2018-05-04 | 华南理工大学 | 紫外微图形化氧化物薄膜的制备方法及薄膜晶体管 |
CN105551955A (zh) * | 2016-02-23 | 2016-05-04 | 华南理工大学 | 氧化物薄膜的制备方法及其薄膜晶体管 |
CN108642460A (zh) * | 2018-04-17 | 2018-10-12 | 齐鲁工业大学 | 网状复合结构薄膜及增韧合成方法 |
CN108982600A (zh) * | 2018-05-30 | 2018-12-11 | 杨丽娜 | 基于氧化镓/镓酸锌异质结纳米阵列的柔性气敏传感器及其制备方法 |
CN110459601A (zh) * | 2018-06-26 | 2019-11-15 | 浙江大学 | 一种二维非晶氧化物半导体与薄膜晶体管及其制备方法 |
CN111024775A (zh) * | 2018-10-09 | 2020-04-17 | 中国科学院物理研究所 | 用于臭氧气体传感器的气敏传感器件以及制备方法 |
CN111024775B (zh) * | 2018-10-09 | 2021-05-25 | 中国科学院物理研究所 | 用于臭氧气体传感器的气敏传感器件以及制备方法 |
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KR20080027276A (ko) | 2008-03-26 |
JP2008547237A (ja) | 2008-12-25 |
CN101213671B (zh) | 2013-01-02 |
WO2007044098A1 (en) | 2007-04-19 |
US20060292777A1 (en) | 2006-12-28 |
EP1908120A1 (en) | 2008-04-09 |
US7507618B2 (en) | 2009-03-24 |
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