CN101819938B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN101819938B
CN101819938B CN201010121255.5A CN201010121255A CN101819938B CN 101819938 B CN101819938 B CN 101819938B CN 201010121255 A CN201010121255 A CN 201010121255A CN 101819938 B CN101819938 B CN 101819938B
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film layer
oxide semiconductor
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semiconductor thin
zinc oxide
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平尾孝
古田守
古田宽
松田时宜
平松孝浩
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Kochi Industrial Promotion Center Of Japanese Consortium Corp
Casio Computer Co Ltd
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Abstract

一种半导体器件的制造方法，包括形成氧化物半导体薄膜层(3)，所述氧化物半导体薄膜层(3)主要包括具有至少一个不同于(002)取向的取向的氧化锌。该氧化锌可以具有包括(002)取向和(101)取向的混合取向。可选地，该氧化锌可以具有包括(100)取向和(101)取向的混合取向。

Description

半导体器件的制造方法
本申请为分案申请，其原申请是2007年9月13日进入中国国家阶段、国际申请日为2007年2月13日的国际专利申请PCT/JP2007/053119,该原申请的中国国家申请号是200780000102.1，发明名称为“半导体器件及其制造方法”。
相关申请的交叉引用
本申请基于并要求2006年2月15日提交的第2006-38424号在先日本专利申请的优先权，通过引用将其整体内容并入此处。
技术领域
本发明涉及半导体器件的制造方法，并且尤其涉及包含氧化物半导体薄膜层的半导体器件的制造方法，其中氧化物半导体薄膜层主要包括氧化锌。
背景技术
诸如氧化锌或氧化锌镁（magnesium zinc oxide）的氧化物作为半导体（有源层）具有极优的特性，这已经为公众所知许多年了。最近几年中，为了将这种半导体薄膜层应用于电子器件，例如薄膜晶体管（以下缩写为TFT）、光发射器件和透明导电膜，已经对使用这些化合物的半导体薄膜层进行了活跃的研究和开发。
与具有非晶硅（a-Si：H）半导体薄膜层的非晶硅TFT相比，包括由氧化锌或氧化锌镁制成的半导体薄膜层的氧化物TFT具有更大的电子迁移率和更好的TFT特性，其已经主要用于液晶显示器。氧化物TFT的另一个优点在于，因为晶体薄膜即使在低至室温的温度中均能形成，所以可预期高电子迁移率。这些优点一直在激励着氧化物TFT的发展。
已报道了使用氧化物半导体薄膜层的TFT，如底栅型TFT和顶栅型TFT。
例如，底栅型TFT包括衬底、在衬底上形成的栅电极、在栅电极上形成的栅极绝缘薄膜、主要包括氧化锌并设置在栅电极的上表面上的氧化物半导体薄膜层、与氧化物半导体薄膜层连接的一对源/漏电极。用类似于制造底栅型非晶硅TFT的方法制造底栅型氧化物TFT，该制造方法已经工业化。这种底栅型结构广泛用在氧化锌TFT中。
另一方面，顶栅型TFT包括，例如衬底、在衬底上形成的一对源/漏电极、在源/漏电极上形成的氧化物半导体薄膜层、在氧化物半导体薄膜层上形成的栅极绝缘膜以及在栅极绝缘膜上形成的栅电极。
在底栅型TFT中，氧化物半导体薄膜层在栅极绝缘膜上形成。在有着这种结构的底栅型TFT中，在氧化物半导体薄膜层形成的早期阶段所沉积的氧化物半导体薄膜层的不完全晶化区，通常用作有源层。这样导致不充分的电子迁移率。另一方面，在顶栅型TFT中，栅极绝缘膜设置在氧化物半导体薄膜层上。这意味着在氧化物半导体薄膜层的上部的完全晶化区用作有源层。在这一方面，顶栅型TFT比底栅型TFT更有用。
传统地，优选使用有着高c轴晶体取向的氧化锌半导体薄膜层。在这种氧化锌半导体薄膜层中，晶粒具有与垂直于基底的方向一致的c轴。使用在某一方向具有择优取向的氧化锌半导体薄膜层被认为提高包括有该氧化锌半导体薄膜层的薄膜晶体管（TFT）的电子迁移率。公知具有高c轴晶体取向的基于氧化锌的膜，可通过在500度C或更低的温度下溅射的方法形成。然而，还没有进行过关于针对非C轴取向的其他取向的取向控制的报道或关于非晶氧化锌的报道。
另一方面，有关加强TFT半导体薄膜层的c轴取向已经进行了多种研究。而且，在第2787198号日本专利中公开了加强热释电红外检测元件的热释电部件的c轴取向的方法。
有着高c轴取向的氧化锌包括沿膜厚方向延伸的柱形结构，且氧化锌中存在许多的晶界。在晶界中，存在晶格缺陷、晶体变形以及悬挂键。因而氧化物半导体薄膜层是热不稳定的。当出于某种目的（例如，形成栅极绝缘膜）使氧化物半导体薄膜层经受热处理时，在氧化物半导体薄膜层的晶界中发生氧化物和锌的脱附。这形成产生电性浅杂质能级并降低氧化物半导体薄膜层的电阻的缺陷能级。如果这种氧化物半导体薄膜层用作薄膜晶体管中的有源层，该薄膜晶体管以常开启型（耗尽型）工作。换句话说，不施加栅电压而出现漏电流。在耗尽型工作中，缺陷能级增加，而阈电压降低并且泄漏电流增大。另外，晶界作用为沟道中电子的能垒，并降低了电子迁移率。
在顶栅型薄膜晶体管中这样的问题更突出，与底栅型薄膜晶体管相比，顶栅型薄膜晶体管中的栅极绝缘膜沉积在氧化物半导体薄膜层上。
在主要包括具有高c轴取向并具有柱形结构的氧化锌的氧化物半导体薄膜层中，蚀刻沿柱形结构进行。这种蚀刻在微加工中产生困难。柱形结构增加氧化物半导体薄膜层表面的粗糙度，而增加的粗糙度阻止在其上所设置的薄栅极绝缘膜的形成。由于栅极绝缘膜的电场集中和增大的泄漏电流，进一步引起栅极绝缘膜的击穿。
如上所述，当用在薄膜晶体管以及例如二极管和光电转换元件等其他半导体器件中时，这种具有高c轴取向的氧化物半导体薄膜层在热阻、微加工特性（有利于微加工的材料特性）以及表面平整度方面具有缺陷。
发明内容
鉴于上述问题，本发明的一个目标是提供作为组件半导体（constituent semiconductor）的一种半导体器件的制造方法，该半导体器件包括有着改进的热阻、微加工特性以及表面平整度的氧化物半导体薄膜层。
根据本发明的半导体器件的制造方法包括：在衬底上形成氧化物半导体薄膜层、使用主要包含氧化锌的氧化物靶。在形成氧化物半导体薄膜层的过程中，对衬底施加射频电源以控制包含（002）取向的氧化物半导体薄膜层中的氧化锌的取向。
根据本发明的一个方面，一种半导体器件的制造方法包括：通过使用主要包含氧化锌的氧化物靶在衬底上形成氧化物半导体薄膜层；以及在所述形成所述氧化物半导体薄膜层的步骤期间，向所述氧化物靶施加射频输入电功率，并向所述衬底施加射频偏置电功率，以将作为所述氧化物半导体薄膜层的主要成分的氧化锌的取向控制为具有至少一个不同于（002）取向的取向，并且其中所述射频偏置电功率小于所述输入电功率。
根据本发明的另一方面，一种半导体器件的制造方法包括：准备靶，所述靶用于形成所述半导体器件的氧化物半导体薄膜层；以及通过磁控溅射，同时向所述靶施加射频输入电功率，并且向衬底施加射频偏置电功率，而在衬底上形成所述氧化物半导体薄膜层，以将作为所述氧化物半导体薄膜层的主要成分的氧化锌的取向控制为具有至少一个不同于（002）取向的取向，其中所述射频偏置电功率小于所施加的所述输入电功率，其中所述偏置电功率在所述输入电功率的0.5%到11%或22%到45%的范围内。
附图说明
由以下结合附图所作的详细说明，本发明的进一步特征和优点将变得明显。
图1示出以根据本发明的一个实施例的方法制造的薄膜晶体管（TFT）。该薄膜晶体管是根据本发明的半导体器件的一个实例；
图2A到2G是薄膜晶体管（TFT）的截面图，其按顺序示出了根据本发明的薄膜晶体管的制造方法的一个实施例。图2A是在衬底上形成一对源/漏电极之后的薄膜晶体管的截面图；图2B是涂覆氧化物半导体薄膜层层之后的薄膜晶体管的截面图；图2C是形成第一栅极绝缘膜之后的薄膜晶体管的截面图；图2D是涂覆光致抗蚀剂并对其进行构图之后的薄膜晶体管的截面图；图2E是对氧化物半导体薄膜和第一栅极绝缘膜进行构图之后的薄膜晶体管的截面图；图2F是形成第二栅极绝缘膜和接触孔之后的薄膜晶体管的截面图；以及图2G是形成栅电极、接触部、外部源/漏电极以及显示电极之后的薄膜晶体管的截面图；
图3示出了在沉积氧化物半导体薄膜层期间对衬底施加0W、1W、2W、5W、10W、20W、40W和80W的偏置功率时的X射线衍射的结果；
图4A是一照片示图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加0W的偏置功率（即，无偏置功率）时，氧化物半导体薄膜层的横截面TEM图像；以及图4B是一照片示图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加5W的偏置功率时，氧化物半导体薄膜层的横截面TEM图像；
图5A是一照片示图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加0W的偏置功率时，氧化物半导体薄膜层的干式蚀刻侧表面的扫描电子显微镜（SEM）图像；以及图5B是一照片示图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加40W的偏置功率时，氧化物半导体薄膜层的干式蚀刻侧表面的扫描电子显微镜（SEM）图像；
图6A是一曲线图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加0W的偏置功率时，通过热脱附谱测得的所去除的质量数（m/e）为64和66的Zn的量的测量结果；以及图6B是一曲线图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加0W的偏置功率时，通过热脱附谱测得的所去除的质量数（m/e）为67和68的Zn的量的测量结果；以及
图7A是一曲线图，其示出了在沉积氧化物半导体薄膜层期间，对衬底施加5W的偏置功率时，通过热脱附谱测得的所去除的质量数（m/e）为64和66的Zn的量的测量结果；以及图7B是一曲线图，示出了在沉积氧化物半导体薄膜层期间，对衬底施加5W的偏置功率时，通过热脱附谱测得的所去除的质量数（m/e）为67和68的Zn的量的测量结果。
具体实施方式
以下将描述以本发明的方法制造的薄膜晶体管，作为以本发明的方法制造的半导体器件的实例。以本发明的方法制造的半导体器件不限于薄膜晶体管，而可以是例如二极管等其它半导体元件或例如传感器等的光电转换元件。尽管如在下面实施例中所示的薄膜晶体管具有顶栅结构，然而本发明的薄膜晶体管可以是底栅型TFT或具有其它顶栅结构的TFT。
在以下说明中，通过例如（002）、（100）和（101）等密勒指数表示氧化锌的取向。这些密勒指数对应于下列六角晶系的指数。
表1
Figure GDA00003340334800061
本发明的薄膜晶体管100包括衬底1、一对源/漏电极2、氧化物半导体薄膜层3、第一栅极绝缘膜4、接触部5a、一对外部源/漏电极2a、第二栅极绝缘膜6、栅电极7、显示电极8，它们按图1所示顺序形成。
如图1a所示，薄膜晶体管100在衬底1上形成，该衬底由玻璃（主要包含Si02和Al203的非碱性玻璃）制成。形成衬底1的材料不限于玻璃，而诸如覆盖有绝缘体的塑料和覆盖有绝缘体的金属箔等绝缘材料可用以形成衬底1。
一对源/漏电极2在衬底1的上表面上形成。这对源/漏电极2包括彼此间隔开的源电极和漏电极。
源/漏电极2由导电氧化物制成，例如氧化铟锡（ITO）和n+ZnO;或金属;或至少局部覆盖有导电氧化物的金属。
氧化物半导体薄膜层3在衬底1和这对源/漏电极2上形成。该氧化物半导体薄膜层3设置为在这对源/漏电极2之间形成沟道。氧化物半导体薄膜层3由主要包含氧化锌的氧化物半导体制成。例如,如此处所使用的，主要包括氧化锌的氧化物半导体包括但不限于：本征（未掺杂）氧化锌；掺杂有诸如Li、Na、N、C等P型掺杂物的氧化锌；掺杂有诸如B、Al、Ga、In等n型掺杂物的氧化锌；以及掺杂有Mg、Be的氧化锌。
与传统的氧化物半导体薄膜层相比，包括具有至少一个不同于（002）取向的取向的氧化锌的氧化物半导体薄膜层3可用以获得较平整的表面、较好的微加工特性以及较高的热阻。
在另一实施例中，可使用含有有着混合取向的氧化锌的氧化物半导体薄膜层3，其中混合取向包括（002）取向和（101）取向。在该实施例中，表示（002）取向的X射线衍射强度I（002）与表示（101）取向的X射线衍射强度I（101）之比I(002)/I(101)优选2或更小。由于与传统的氧化物半导体薄膜层相比，这种氧化物半导体薄膜层具有较平整的表面，所以可能形成较薄的栅极绝缘膜，这增强薄膜晶体管的栅电容和电流驱动能力。而且，由于氧化锌是微晶态或非晶态，该氧化物半导体薄膜层具有较好的微加工特性和较高的热阻。
在另一实施例中，可使用含有有着混合取向的氧化锌的氧化物半导体薄膜层3，其中混合取向包括（100）取向和（101）取向。在该实施例中，表示（101）取向的X射线衍射强度I（101）与表示（100）取向的X射线衍射强度I（100）之比I(101)/I(100)优选在0.5到5的范围中。在制造工程中的热处理期间，有着（100）和（101）混合取向的氧化锌具有较高的热阻，并防止氧化物半导体薄膜层电阻的减小导致氧化锌成分的脱附。从而，抑制了泄漏电流。而且，改善了氧化锌的微加工特性。
例如,氧化物半导体薄膜层3的厚度不特别限于但可以为约25-200nm且优选为约30-100nm。
形成第一栅极绝缘膜4以仅覆盖氧化物半导体薄膜层3的上表面。第一栅极绝缘膜4构成栅极绝缘膜的一部分并用作保护膜，以保护氧化物半导体薄膜层3,使其免受光刻过程中所用的抗蚀剂剥离液。例如,第一栅极绝缘膜4的厚度不特别限于但可以为约20-100nm，且优选为约50nm或更小。
在一对源/漏电极上形成第二栅极绝缘膜6以覆盖氧化物半导体薄膜层3的侧表面和第一栅极绝缘膜4的整个表面。既然氧化物半导体薄膜层3的上表面覆盖有第一栅极绝缘膜4，那么就完成了对氧化物半导体薄膜层3整个表面上的覆盖。
例如,第二栅极绝缘膜6的厚度可以为200-400nm且优选为约300nm。
第一栅极绝缘膜4和第二栅极绝缘膜6可以是氧化硅（SiOx）膜、氮氧化硅（SiON）膜、氮化硅（SiNx）膜或利用氧气或含有氧的化合物（例如N2O）而掺杂氧的氮化硅（SiNx）膜。优选地，栅极绝缘膜4由利用氧气或含有氧的化合物（例如N2O）而掺杂氧的氮化硅（SiNx）膜形成。与氧化硅化合物（SiOx）或氮氧化硅（SiON）相比，这种掺杂的氮化硅膜具有较高的介电常数。
例如,第一栅极绝缘膜4和第二栅极绝缘膜6可通过等离子体增强化学气相沉积（PCVD）形成。通过等离子体增强化学气相沉积（PCVD）形成膜优选在200-400度C范围的衬底温度下进行。
外部源/漏电极2a经由接触部5a分别连接于相应的源/漏电极2。
在第二栅极绝缘膜6上形成栅电极7。配置栅电极7用于根据施加到薄膜晶体管的栅电压控制氧化物半导体薄膜层3中的电子密度。栅电极7由诸如Cr膜或Ti膜等金属膜制成。
配置显示电极8用于向液晶显示器中所使用的液晶施加电压。显示电极8由诸如氧化铟锡（ITO）薄膜等导电氧化物薄膜形成，因为关于可见光其具有高透射率。显示电极8形成在第二栅极绝缘膜6上并且沿与栅电极7不同的方向延伸。
参照图2A-2G，下面将描述根据本发明的一个实施例的薄膜晶体管的制造方法。
参照图2A，通过磁控溅射在玻璃衬底1上形成诸如Cr膜或Ti膜等薄金属膜，其具有例如50nm的厚度。然后通过光刻将该薄膜图案化成一对源/漏电极2。
参照图2B，通过磁控溅射在这对源/漏电极2的整个上表面和玻璃衬底1上形成氧化物半导体薄膜层3，其具有30-100nm的厚度。该氧化物半导体薄膜层3可以是基于氧化锌的半导体薄膜或优选基于本征氧化锌（ZnO）的半导体薄膜。
公知通过普通磁控溅射所形成的基于氧化锌的半导体薄膜具有（002）择优取向。换句话说，基于氧化锌的氧化物薄膜没有表示不同于（002）取向的其它取向的X射线衍射峰。在本发明中，另一方面，在通过磁控溅射形成薄膜期间，通过经衬底平台平台（substratestage）（在薄膜形成期间放置衬底的平台）向衬底施加射频电功率控制氧化物半导体薄膜层的取向。特别地，向衬底施加适当功率（见下文）的射频（本发明实施例中为13.56MHz）偏置电功率，而向氧化物靶施加180W的射频（在本发明实施例中为13.56MHz）输入电功率。
约1-10W、优选约1-5W的偏置电功率能够使氧化物半导体薄膜层的I(002)/I(101)比为2或更小。与传统的氧化物半导体薄膜层相比，由于这种氧化物半导体薄膜层具有较平整的表面，有可能形成较薄的栅极绝缘膜，这增强薄膜晶体管的电流驱动能力。而且，由于氧化锌处于微晶态或非晶态，所以该氧化物半导体薄膜层具有改善的微加工特性和较高的热阻。只要有上述效果，也可使用小于1W的偏置电功率。
在沉积氧化物半导体薄膜层期间，可向衬底施加10W或更大的偏置电功率。如果偏置电功率超过10W（即输入电功率的5%），氧化物半导体薄膜层的取向从（002）和（101）混合取向变为（100）和（101）混合取向（当偏置电功率小于输入电功率的5%时实现的）。换句话说，通过将偏置电功率设为大于输入电功率的5%而获得I(101)/I(100)比的范围为从0.5到5的氧化物半导体薄膜层。有着（100）和（101）混合取向的氧化锌具有较高的热阻，并且在制造过程中的热处理期间，其防止由氧化锌成分的脱附所导致氧化物半导体薄膜层电阻的减小。从而，从而，抑制了泄漏电流。而且，改善了氧化锌的微加工特性。下面参照图3将以所示实例描述通过施加上述偏置电功率控制氧化锌的取向的方法。
在某些实施例中，可通过改变除所施加的偏置电功率量以外的其它的膜形成条件控制氧化锌的取向。而且输入电功率和偏置电功率的比率之间的分界可根据所用的条件变化，其中在分界处（101）和（102）的混合取向变为（100）和（101）的混合取向。上述值5%是在下面所述例子中所用的条件下的值。该值可以根据所使用的装置和偏置电功率的频率变化.
参照图2C，使用一种技术并在不减小氧化物半导体薄膜层3的电阻的条件下，在氧化物半导体薄膜层3上形成第一栅极绝缘膜4。
栅极绝缘膜4可以是在一条件下通过等离子体增强化学气相沉积（PCVD）制造的20到50nm厚的SiNx膜，该条件为，例如衬底温度是250℃，并且以4比1的流量比使用含NH3和SiH4的混合气体。
参照图2D，在第一栅极绝缘膜4上布置光致抗蚀剂并对其进行构图。利用作为掩模的图案化光致抗蚀剂，用例如SF6等气体干式蚀刻第一栅极绝缘膜4。而后用0.2%的NHO3湿式蚀刻氧化物半导体薄膜层3。
图2E示出了湿式蚀刻氧化物半导体薄膜层3随后去除光致抗蚀剂4a之后的薄膜晶体管的横截面。在图2E所示的薄膜晶体管中，形成TFT有源层区，该有源层区包括形状与氧化物半导体薄膜层3相同的第一栅极绝缘膜4。第一栅极绝缘膜4不仅形成与氧化物半导体薄膜层3的界面，而且在对有源区进行构图时保护氧化物半导体薄膜层3。如果不存在第一栅极绝缘膜4，对TFT有源区构图后，当使用抗蚀剂剥离液去除光致蚀刻剂4a时，蚀刻剂剥离液与氧化物半导体薄膜层3的表面接触。蚀刻剂剥离液通常腐蚀和粗糙化氧化物半导体薄膜层3的表面和晶粒界面。然而，如果在氧化物半导体薄膜层3的表面上存在第一栅极绝缘膜4，第一栅极绝缘膜4用作保护膜，其抵抗像光刻工艺中所用的例如抗蚀剂剥离液等各种液体化学药品。因此第一栅极绝缘膜4防止氧化物半导体薄膜层3的表面粗糙化。
参照图2F，对TFT有源层区进行构图后，在衬底1、一对源/漏电极2、氧化物半导体薄膜层3以及第一栅极绝缘膜4的整个上表面和/或侧表面上形成第二栅极绝缘膜6。然后在第二栅极绝缘膜6中打开接触孔以暴露这对源/漏电极2的部分。在该实施例中，理想地为在与第一栅极绝缘膜4（受控界面绝缘膜）相似的条件下形成第二栅极绝缘膜6。
最后，参照图2G，在第二栅极绝缘膜6上形成由金属膜（例如，Cr膜或Ti膜）制成的栅电极7。之后，用与栅电极7相同的材料形成外部源/漏电极2a。外部源/漏电极经由接触部5a分别连接到源/漏电极2。在形成TFT阵列的最后步骤中，形成由例如氧化铟锡（ITO）等制成的显示电极8。
例子
在下文中，将说明用于评测以本发明的方法制造的半导体器件的氧化物半导体薄膜层的实验例子，以阐明本发明的效果。通过磁控溅射，同时向靶施加恒量180W的13.56MHz频率的输入电功率，并经衬底平台向衬底施加13.56MHz频率的各种偏置电功率,来形成用在以下例子中的氧化物半导体薄膜层。
图3示出了在形成氧化物半导体薄膜层的氧化锌膜期间，作为向衬底施加的不同偏置电功率的函数的X射线衍射强度。特别地，用不同的偏置电功率0W、1W、2W、5W、10W、20W、40W以及80W形成氧化物半导体薄膜层。换句话说，以不施加偏置电功率和施加范围是从输入电功率的约0.5%到约45%的不同偏置电功率的方式,形成氧化物半导体薄膜层。
在沉积氧化物半导体薄膜层期间，当不向衬底施加偏置电功率时，未检测到其它取向而只检测到（002）取向。
在沉积氧化物半导体薄膜层期间，当向衬底施加1W的偏置电功率时，（002）取向衰减并观察到（101）取向。推测利用1W或更小的偏置电功率可得到相似的效果，尽管利用在例子中所用的射频功率源未检测如此小的偏置电功率。
当使用1W到10W的偏置电功率时，得到I(002)/I(101)比为2或更小的氧化物半导体薄膜层。与传统的氧化物半导体薄膜层相比，由于这种氧化物半导体薄膜层具有较平整的表面，所以微加工特性被改善。而且，提高了氧化物半导体薄膜层的热阻。
在沉积氧化物半导体薄膜层期间，当向衬底施加10W（即，输入电功率的5%）或更大的偏置电功率时，氧化物半导体薄膜层的取向从（002）和（101）混合取向变为（100）和（101）混合取向。I(101)/I(100)比的范围为从0.5到5。这种氧化物半导体薄膜层具有较高的热阻和改善的微加工特性。
图4A示出了在沉积氧化物半导体薄膜层期间向衬底施加0W的偏置电功率时，所形成的氧化物半导体薄膜层的横截面透射电子显微镜（TEM）图像，而图4B示出了在沉积氧化物半导体薄膜层期间向衬底施加5W的偏置电功率时，氧化物半导体薄膜层的横截面TEM图像。
在沉积氧化物半导体薄膜层期间，当向衬底施加0W偏置电功率（即，不施加偏置电功率）时，观察到柱状晶体结构和严重的表面粗糙。该柱状结构推测为因c轴（002）取向而产生。
另一方面，参照在沉积氧化物半导体薄膜层期间向衬底施加5W的偏置电功率时的该氧化物半导体薄膜层的横截面TEM图像，观察到氧化物半导体薄膜层被微晶化而具有较平整的表面，尽管该氧化物半导体薄膜层仍有c轴择优取向。使用这种具有较平整表面的氧化物半导体薄膜层，可能形成较薄的半导体器件，例如TFT。所得的TFT具有增强的电流驱动能力。
图5A和图5B分别示出了在沉积氧化物半导体薄膜层期间，当向衬底施加0W和40W的偏置电功率时，所形成的干式蚀刻的氧化物半导体（氧化锌）薄膜层的扫描电子显微镜（SEM）图像。在干式蚀刻中使用CH4气体。
在沉积氧化物半导体薄膜层期间,当向衬底施加0W的偏置电功率（即，不施加偏置电功率）时，因为具有c轴（002）取向的氧化物半导体薄膜层沿氧化锌的柱状晶体结构被蚀刻，干式蚀刻的氧化物半导体薄膜层的所构图侧表面较粗糙。
另一方面，在沉积氧化物半导体薄膜层期间,当向衬底施加40W的偏置电功率时，柱状晶体结构瓦解且所构图侧表面形成小粗糙度的平整表面。因此氧化物半导体薄膜层的微加工特性通过施加适当的偏置电功率得到改善。
图6A和图6B示出了Zn从含在氧化物半导体薄膜层中的氧化锌脱附的热脱附谱。通过使用热脱附方法和在沉积氧化物半导体薄膜层期间向衬底施加0W的偏置电功率时所形成的氧化物半导体薄膜层测量Zn脱附的量。图7A和图7B示出了，使用在沉积氧化物半导体薄膜层期间当向衬底施加5W的偏置电功率时所形成的氧化物半导体薄膜层，以与图6A和图6B中的例子相同的测量所测得的去除的Zn的量。图6A和图7A示出了所去除的质量数（m/e）为64和66的Zn的量，而图6B和图7B示出了所去除的质量数（m/e）为67和68的Zn的量。
在沉积氧化物半导体薄膜层期间,当向衬底施加0W的偏置电功率（即，不施加偏置电功率）时，当热处理温度超过约200度C时，Zn开始从氧化锌脱附，且当热处理温度超过约300度C时，所去除的Zn量迅速增加。这种特性因具有柱状结构和许多晶粒界面的氧化物半导体薄膜层的热不稳定性产生。
另一方面，在沉积氧化物半导体薄膜层期间,当向衬底施加5W的偏置电功率时，柱状晶体结构瓦解。甚至在较高的热处理温度下，实现氧化锌的所去除成分的量的减少。当这种氧化物半导体薄膜层用在例如TFT等半导体器件中时，甚至在栅极绝缘膜形成期间对TFT热处理时，也防止氧化锌成分的脱附。因此防止氧化物半导体薄膜层的电阻减小并且抑制泄漏电流。
如上所述，根据本发明的半导体器件的氧化物半导体薄膜层具有较高的热阻、较平整的表面以及提高的微加工特性。

Claims (8)

1.一种半导体器件的制造方法，其包括：
通过使用主要包含氧化锌的氧化物靶在衬底（1）上形成氧化物半导体薄膜层；以及
在所述形成所述氧化物半导体薄膜层（3）的步骤期间，向所述氧化物靶施加射频输入电功率，并向所述衬底施加射频偏置电功率，以将作为所述氧化物半导体薄膜层的主要成分的氧化锌的取向控制为具有至少一个不同于（002）取向的取向，并且
其中所述射频偏置电功率小于所述输入电功率。
2.如权利要求1所述的半导体器件的制造方法，其中使用磁控溅射执行所述形成所述氧化物半导体薄膜层的步骤，且其中通过衬底平台执行所述向所述衬底（1）施加所述射频电功率的步骤。
3.一种半导体器件的制造方法，其包括：
准备靶，所述靶用于形成所述半导体器件的氧化物半导体薄膜层（3）；以及
通过磁控溅射，同时向所述靶施加射频输入电功率，并且向衬底施加射频偏置电功率，而在衬底上形成所述氧化物半导体薄膜层，以将作为所述氧化物半导体薄膜层的主要成分的氧化锌的取向控制为具有至少一个不同于（002）取向的取向，其中所述射频偏置电功率小于所施加的所述输入电功率，
其中所述偏置电功率在所述输入电功率的0.5%到11%或22%到45%的范围内。
4.如权利要求3所述的半导体器件制造方法，其中所述靶含有氧化锌，因此所述氧化物半导体薄膜层（3）含有氧化锌，并且所述含有氧化锌的氧化物半导体薄膜层具有至少一个不同于（002）取向的取向。
5.如权利要求4所述的半导体器件制造方法，其中包含在所述氧化物半导体薄膜层（3）中的氧化锌具有包括（002）取向和（101）取向的混合取向。
6.如权利要求5所述的半导体器件制造方法，其中表示包含在所述氧化物半导体薄膜层（3）中的氧化锌的所述（002）取向的X射线衍射强度I（002）与表示包含在所述氧化物半导体薄膜层（3）中的氧化锌的所述（101）取向的X射线衍射强度I（101）之比I(002)/I(101)不大于2。
7.如权利要求4所述的半导体器件制造方法，其中包含在所述氧化物半导体薄膜层（3）中的氧化锌具有包括（100）取向和（101）取向的混合取向。
8.如权利要求7所述的半导体器件制造方法，其中表示包含在所述氧化物半导体薄膜层（3）中的氧化锌的所述（101）取向的X射线衍射强度I（101）与表示包含在所述氧化物半导体薄膜层（3）中的氧化锌的所述（100）取向的X射线衍射强度I（100）之比I(101)/I(100)在0.5到5的范围内。
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