JP7528063B2 - 半導体装置および電子機器 - Google Patents
半導体装置および電子機器 Download PDFInfo
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- JP7528063B2 JP7528063B2 JP2021515313A JP2021515313A JP7528063B2 JP 7528063 B2 JP7528063 B2 JP 7528063B2 JP 2021515313 A JP2021515313 A JP 2021515313A JP 2021515313 A JP2021515313 A JP 2021515313A JP 7528063 B2 JP7528063 B2 JP 7528063B2
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- semiconductor
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Description
図2Aおよび図2Bは、バイアス出力手段の回路構成例を示す図である。図2Cは、バイアス出力手段の等価回路を示す図である。
図3Aおよび図3Bは、バイアス出力手段の動作例を示す図である。
図4Aおよび図4Bは、バイアス出力手段の動作例を示す図である。
図5は、バイアス出力手段の回路構成例を示す図である。
図6は、バイアス出力手段の動作例を示す図である。
図7A乃至図7Dは、トランジスタの回路記号を示す図である。
図8は、半導体装置の動作例を示すフローチャートである。
図9は、半導体装置の構成例を示す図である。
図10は、半導体装置の構成例を示す図である。
図11は、半導体装置の構成例を示す図である。
図12A乃至図12Cは、トランジスタの構成例を示す図である。
図13A乃至図13Cは、トランジスタの構成例を示す図である。
図14A乃至図14Cは、トランジスタの構成例を示す図である。
図15AはIGZOの結晶構造の分類を説明する図である。図15BはCAAC-IGZO膜のXRDスペクトルを説明する図である。図15CはCAAC-IGZO膜の極微電子線回折パターンを説明する図である。
図16A乃至図16Eは、電子機器の一例を示す図である。
本発明の一態様に係る半導体装置について、図面を用いて説明する。図1は本発明の一態様に係る半導体装置100の構成を説明するブロック図である。
半導体装置100は、送受信手段110、変換手段120、制御手段130、アンテナ共用器140、およびアンテナ150を有する。
次に、バイアス出力手段112の構成例を説明する。図2Aにバイアス出力手段112の回路構成例を示す。図2Aに示すバイアス出力手段112は、記憶部200と、トランジスタM3と、トランジスタM99と、を有する。また、記憶部200はトランジスタM1と、トランジスタM2と、容量C1と、を有する。
ここで、バイアス出力手段112の動作例について説明しておく。
まず、図3Aおよび図3Bを用いて、ノードFNにバイアス設定電圧を書き込む動作について説明する。
続いて、図4Aおよび図4Bを用いて、ノードFNに書き込まれたバイアス設定電圧に応じた電圧(バイアス信号)を端子OUTに供給する動作について説明する。
続いて、半導体装置100の動作例を説明する。図8は半導体装置100の動作例を説明するフローチャートである。
図9に、半導体装置100の変形例である半導体装置100Aの構成例を示す。半導体装置100Aは、送信手段111とアンテナ共用器140の間に電力検知手段116を有する点が半導体装置100と異なる。
本実施の形態では、上記実施の形態で説明した半導体装置に適用可能なトランジスタの構成について説明する。一例として、異なる電気特性を有するトランジスタを積層して設ける構成について説明する。当該構成とすることで、半導体装置の設計自由度を高めることができる。また、異なる電気特性を有するトランジスタを積層して設けることで、半導体装置の集積度を高めることができる。
図13A、図13B、図13Cに示すトランジスタ500Aは、図12A、図12Bに示す構成のトランジスタ500の変形例である。図13Aはトランジスタ500Aの上面図であり、図13Bはトランジスタ500Aのチャネル長方向の断面図である。図13Cは、トランジスタ500Aのチャネル幅方向の断面図である。なお、図13A、図13B、図13Cに示す構成は、トランジスタ550等、本発明の一態様の半導体装置が有する他のトランジスタにも適用することができる。
図14A、図14Bおよび図14Cを用いて、トランジスタ500Bの構成例を説明する。図14Aはトランジスタ500Bの上面図である。図14Bは、図14Aに一点鎖線で示すL1-L2部位の断面図である。図14Cは、図14Aに一点鎖線で示すW1-W2部位の断面図である。なお、図14Aの上面図では、図の明瞭化のために一部の要素の記載を省略している。
本実施の形態では、金属酸化物の一種である酸化物半導体について説明する。
まず、酸化物半導体における、結晶構造の分類について、図15Aを用いて説明を行う。図15Aは、酸化物半導体、代表的にはIGZO(Inと、Gaと、Znと、を含む金属酸化物)の結晶構造の分類を説明する図である。
なお、酸化物半導体は、結晶構造に着目した場合、図15Aとは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のCAAC-OS、及びnc-OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)、非晶質酸化物半導体、などが含まれる。
CAAC-OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC-OS膜の厚さ方向、CAAC-OS膜の被形成面の法線方向、またはCAAC-OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC-OSは、a-b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC-OSは、c軸配向し、a-b面方向には明らかな配向をしていない酸化物半導体である。
nc-OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc-OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc-OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc-OSは、分析方法によっては、a-like OSや非晶質酸化物半導体と区別が付かない場合がある。例えば、nc-OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut-of-plane XRD測定では、結晶性を示すピークが検出されない。また、nc-OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう。)を行うと、ハローパターンのような回折パターンが観測される。一方、nc-OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう。)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a-like OSは、nc-OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a-like OSは、鬆又は低密度領域を有する。即ち、a-like OSは、nc-OS及びCAAC-OSと比べて、結晶性が低い。また、a-like OSは、nc-OS及びCAAC-OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC-OSの詳細について、説明を行う。なお、CAC-OSは材料構成に関する。
CAC-OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本実施の形態では、本発明の一態様に係る半導体装置を適用できる電子機器について説明する。
Claims (5)
- 受信手段と、制御手段と、バイアス出力手段と、送信手段と、を有し、
前記バイアス出力手段は、複数の記憶手段と、複数の第1トランジスタと、第2トランジスタと、を有する半導体装置であって、
前記受信手段は、受信信号に含まれる第1信号を前記制御手段に供給する機能を有し、
前記制御手段は、前記第1信号に応じて、前記複数の記憶手段の中から第1記憶手段を選択する機能を有し、
前記バイアス出力手段は、前記第1記憶手段が保持する第1情報に応じて第2信号を出力する機能を有し、
前記送信手段は、前記第2信号に応じて出力電力を決定する機能を有し、
前記複数の記憶手段のそれぞれは、第3トランジスタと、第4トランジスタと、容量と、を有し、
前記第3トランジスタのソースまたはドレインの一方は、第1端子と常に導通し、
前記第3トランジスタのソースまたはドレインの他方は、前記第4トランジスタのゲートと常に導通し、
前記容量の一方の電極は、前記第4トランジスタのゲートと常に導通し、
前記第4トランジスタのソースまたはドレインの一方には、第1電源電位が与えられ、
前記第4トランジスタのソースまたはドレインの他方は、前記複数の第1トランジスタのうち、一の第1トランジスタのソースまたはドレインの一方と常に導通し、
前記一の第1トランジスタのソースまたはドレインの他方は、第2端子と常に導通し、
前記第2トランジスタのソースまたはドレインの一方は、前記第2端子と常に導通し、
前記第2トランジスタのソースまたはドレインの他方には、前記第1電源電位よりも高い第2電源電位が与えられ、
前記第1トランジスタがオン状態にあり、前記第2トランジスタがオン状態にあり、かつ、前記第4トランジスタがオン状態にある期間を有し、
前記第1トランジスタの半導体層は酸化物半導体を含む半導体装置。 - 請求項1において、
前記半導体層は、In及びZnの一方または双方を含む半導体装置。 - 請求項1または請求項2において、
前記第1記憶手段は、電力供給が停止しても前記第1情報を保持する機能を有する半導体装置。 - 請求項1乃至請求項3のいずれか1項において、
前記制御手段は、前記複数の記憶手段のそれぞれに情報を書き込む機能を有する半導体装置。 - 請求項1乃至請求項4のいずれか一項に記載の半導体装置と、
アンテナと、マイクと、スピーカと、を有する電子機器。
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