CN109427547A - 用于沉积经掺杂锗锡半导体的方法和相关半导体装置结构 - Google Patents

用于沉积经掺杂锗锡半导体的方法和相关半导体装置结构 Download PDF

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CN109427547A
CN109427547A CN201810725750.3A CN201810725750A CN109427547A CN 109427547 A CN109427547 A CN 109427547A CN 201810725750 A CN201810725750 A CN 201810725750A CN 109427547 A CN109427547 A CN 109427547A
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tin
germanium
semiconductor
precursor
substrate
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D·科恩
H·B·普罗菲特
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ASM Japan KK
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ASM Japan KK
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

公开一种用于沉积锗锡(Ge1‑xSnx)半导体的方法。所述方法可包含:在反应腔室内提供衬底;将所述衬底加热到沉积温度;以及将所述衬底暴露于锗前体和锡前体。所述方法可进一步包含:将锗锡(Ge1‑xSnx)半导体沉积在所述衬底的表面上;以及将所述锗锡(Ge1‑xSnx)半导体暴露于硼掺杂剂前体。还提供包含通过本公开的方法形成的锗锡(Ge1‑xSnx)半导体的半导体装置结构。

Description

用于沉积经掺杂锗锡半导体的方法和相关半导体装置结构
技术领域
本公开大体上涉及用于沉积锗锡(Ge1-xSnx)半导体的方法和含有锗锡(Ge1-xSnx)半导体的相关装置结构。本公开还大体上涉及用于掺杂锗锡(Ge1-xSnx)半导体的方法。
背景技术
人们越来越关注如锗锡(Ge1-xSnx)的含锡半导体材料在许多应用中的应用,例如用于先进微电子装置的高迁移率通道和应变工程、用于光子装置的直接带隙IV族材料或用于光伏装置的GeSn合金。
单晶锗锡(Ge1-xSnx)半导体材料可使用各种技术沉积或生长。举例来说,包含分子束外延和化学气相沉积的真空工艺可用于形成单晶锗锡(Ge1-xSnx)半导体。
在一些半导体装置应用中,锗锡(Ge1-xSnx)半导体可掺杂有选定的杂质以获得所要电导率。举例来说,锗锡(Ge1-xSnx)半导体可通过将硼并入到锗锡(Ge1-xSnx)半导体中而掺杂成p型。然而,在一些应用中,可能需要沉积或生长锗锡(Ge1-xSnx)半导体,其不仅具有高p型掺杂浓度,而且具有显著的锡(Sn)组成。举例来说,对于锡(Sn)组成大于x=0.03的锗锡(Ge1-xSnx)半导体,可能难以获得大于1×1020掺杂剂/立方厘米的掺杂浓度。因此,当沉积或生长锗锡(Ge1-xSnx)半导体材料时,锡(Sn)组成与掺杂浓度之间存在取舍。因此,需要用于形成具有显著锡(Sn)组成和高掺杂浓度的锗锡(Ge1-xSnx)半导体的方法。
发明内容
根据本公开的至少一个实施例,公开一种用于沉积经掺杂锗锡(Ge1-xSnx)半导体的方法。所述方法可包括:在反应腔室内提供衬底;将所述衬底加热到沉积温度;以及将所述衬底暴露于锗前体和锡前体。所述方法可进一步包括:将锗锡(Ge1-xSnx)半导体沉积在所述衬底的表面上;以及将所述锗锡(Ge1-xSnx)半导体暴露于硼掺杂剂前体。本公开的实施例还可包含半导体装置结构,所述半导体装置结构可包括通过本公开的方法形成的经掺杂锗锡(Ge1-xSnx)半导体。
出于概述本发明和优于现有技术而实现的优势的目的,上文中描述了本发明的某些目标和优势。当然,应理解,未必所有此类目标或优势都可根据本发明的任一特定实施例实现。因此,举例来说,所属领域的技术人员将认识到,本发明可以按实现或优化如本文中所教示或建议的一种优势或一组优势,但不一定实现如本文中可能教示或建议的其它目的或优势的方式来实施或进行。
所有这些实施例意欲在本文中所公开的本发明的范围内。对于所属领域的技术人员来说,这些和其它实施例将从参考附图的某些实施例的以下详细描述变得显而易见,本发明不限于所公开的任何特定实施例。
附图说明
尽管本说明书以明确地指出并且明显地要求被视为本发明实施例的部分的权利要求结束,但是当结合附图阅读时,可以从本公开实施例的某些实例的描述中更容易地确定本公开实施例的优势,在附图中:
图1说明工艺流程图,所述工艺流程图说明根据本公开的实施例的示范性沉积方法;
图2说明包含通过本公开的实施例形成的锗锡(Ge1-xSnx)半导体的半导体装置结构。
将了解,图中的元件仅为简单及清晰起见而进行说明,且未必是按比例绘制。举例来说,图中的一些元件的尺寸可能相对于其它元件夸大,以有助于改进对本公开所说明实施例的理解。
具体实施方式
尽管下文公开某些实施例和实例,但所属领域的技术人员将理解,本发明延伸超出了所具体公开的实施例和/或本发明的用途和显而易见的修改以及其等效物。因此,希望本发明所公开的范围不应受下文所描述特定公开实施例的限制。
如本文中所使用,术语“衬底”可指可以使用的,或其上可形成装置、电路或膜的任何底层材料。
如本文中所使用,术语“外延层”可指在底层大致上单晶衬底上的大致上单晶层。
如本文中所使用,术语“化学气相沉积”可指其中衬底暴露于一种或多种挥发性前体的任何方法,所述前体在衬底表面上反应和/或分解以产生所要沉积。
如本文中所使用,术语“锗锡”可指包括锗和锡的半导体材料,且可表示为Ge1- xSnx,其中1≥x≥0。
本公开的实施例可包含用于形成锗锡(Ge1-xSnx)半导体材料且明确地说用于通过化学气相沉积方法沉积锗锡(Ge1-xSnx)半导体的方法。本公开的实施例还可包含用于用p型掺杂剂掺杂锗锡半导体材料同时将显著锡(Sn)组成并入到锗锡(Ge1-xSnx)半导体材料中的方法,其中所述p型掺杂剂可由硼掺杂剂前体提供。
应力工程已证明对于在每个连续技术节点上实现改进的Si-CMOS装置性能至关重要。预期并入IV族半导体及其合金,且明确地说,并入锗锡(Ge1-xSnx)半导体材料可显著扩大设计空间,以延续带隙工程和与硅(Si)兼容的平台的应力工程。锗锡(Ge1-xSnx)半导体合金提供IV族半导体的最大晶格常数,由此提供超越用于基于应力工程锗(Ge)和硅锗(SiGe)的装置的硅(Si)和硅锗(SiGe)的额外灵活性。举例来说,锗锡(Ge1-xSnx)半导体材料不仅可用于pMOSFET装置的通道材料,而且此外,pMOSFET装置的源极区/漏极区还可包括利用本公开的实施例沉积和掺杂的锗锡(Ge1-xSnx)半导体材料。
然而,为了向正在制造的半导体装置结构(即FinFET装置)赋予显著应力,锗锡(Ge1-xSnx)半导体材料可能需要显著的锡(Sn)组成;例如,源极区/漏极区中的锗锡(Ge1- xSnx)半导体材料的组成可大于x=0.08。相反,晶体管结构的源极区/漏极区可能需要高度掺杂,使得与源极区/漏极区的电接触电阻保持最小,由此改进装置的效率。因此,需要包括高度掺杂(以提供低接触电阻)且包括显著锡(Sn)组成(以向装置结构提供应力)的锗锡(Ge1-xSnx)半导体材料的方法和装置结构。
本公开的方法可参考图1来理解,图1说明用于形成锗锡(Ge1-xSnx)半导体材料的方法的非限制性实例实施例。举例来说,图1可说明用于形成锗锡(Ge1-xSnx)半导体材料的方法100,其可包括过程框110,其中可将衬底提供到反应腔室中且可在反应腔室内将衬底加热到处理温度。作为非限制性实例,反应腔室可包括化学气相沉积系统的反应腔室。本公开的实施例可在从ASM International N.V.以名称IntrepidTM XP或购得的化学气相沉积系统中执行。然而,还预期还可利用来自其它制造商的其它反应腔室和替代化学气相沉积系统来执行本公开的实施例。
在本公开的一些实施例中,衬底可包括平面衬底或图案化衬底。图案化衬底可包括可包含形成到衬底表面中或其上的半导体装置结构的衬底。举例来说,图案化衬底可包括部分制造的半导体装置结构,例如晶体管和存储元件。衬底可含有单晶表面和/或一个或多个次表面,所述次表面可包括非单晶表面,例如多晶表面和非晶形表面。单晶表面可包括例如以下中的一种或多种:硅(Si)、硅锗(SiGe)、锗锡(GeSn)或锗(Ge)。多晶或非晶形表面可包含介电材料,例如氧化物、氮氧化物或氮化物。
在本公开的一些实施例中,衬底可包括“虚拟衬底”,其中虚拟衬底可包括设置在彼此上的两种或更多种材料。举例来说,锗虚拟衬底可包括上部大部分暴露的锗生长表面,其中虚拟衬底可包括沉积在例如硅衬底的另一材料上的一层锗。
继续参考图1,方法100可通过在反应腔室内将衬底加热到所要处理温度来继续。在本公开的一些实施例中,方法100可包括将衬底加热到小于约400℃的温度或小于约350℃的温度或小于约300℃的温度或甚至小于约250℃的温度。在本公开的一些实施例中,所述方法可包括将衬底加热到约275℃与约400℃之间的温度。在本公开的一些实施例中,可在将衬底装载到反应腔室中之后且在将衬底加热到处理温度之前对衬底执行任选的沉积前烘烤,例如,衬底可经受在约350℃与约500℃之间的温度下的沉积前烘烤。
一旦将衬底加热到所要处理温度,方法100就可通过将衬底暴露于锗前体和锡前体来继续,如由图1的过程框120所说明。在本公开的一些实施例中,锗前体与锡前体两者可以通常被称为“共流”工艺的工艺同时引入到反应腔室中。举例来说,在一些实施例中,锗前体到反应腔室中的流动速率可大于50sccm或大于100sccm或甚至大于200sccm。此外,在一些实施例中,锡前体到反应腔室中的流动速率可大于0.1mg/min或大于1mg/min或甚至大于5mg/min。
在本公开的一些实施例中,将衬底暴露于锗前体可进一步包括选择锗前体以包括锗烷(GeH4)、二锗烷(Ge2H6)、三锗烷(Ge3H8或锗烷基硅烷(GeH6Si)中的至少一个。在本公开的一些实施例中,锗前体可包括Si-Ge-氢化物前体,例如(H3Ge)xSiH4-x,其中x=1到4,或(H3Si)XGeH4-x,其中x=1到4。在本公开的一些实施例中,可能有利的是进一步将硅并入到沉积过程中,例如,前体流还可包含硅前体,例如但不限于,硅烷(SiH4)、二硅烷(Si2H6)、三硅烷(Si3H8)或较高阶硅烷化合物。在本公开的一些实施例中,将衬底暴露于锡前体可进一步包括选择锡前体以包括四氯化锡(SnCl4)或氘化锡(SnD4)中的至少一个。
应了解,在将衬底加热到沉积温度且将锗前体与锡前体同时引入到反应腔室中时,反应腔室可维持在大气压或者减压下。举例来说,在一些实施例中,反应腔室的压力可小于760托或甚至小于100托或甚至小于10托。
在本公开的一些替代实施例中,将衬底暴露于锗前体和锡前体可进一步包括将衬底暴露于初始硼掺杂剂前体。举例来说,可将锗前体、锡前体与初始硼掺杂剂前体同时引入到反应腔室中,即以“共流”工艺引入。在本公开的一些实施例中,初始硼掺杂剂前体可包括二硼烷(B2H6)或三氯化硼(BCl3)中的至少一个。初始硼掺杂剂前体可以大于0.01sccm或大于0.1sccm或甚至大于1sccm的流动速率引入到反应腔室中。
方法100可以过程框130继续,其中所述方法包括将锗锡(Ge1-xSnx)半导体材料沉积在衬底的表面上。在本公开的一些实施例中,锗锡(Ge1-xSnx)半导体材料可包括锡(Sn)组成,其中x大于0.01或大于0.05或甚至大于0.08。在一些实施例中,将锗锡(Ge1-xSnx)半导体材料沉积在衬底的表面上进一步包括将锗锡(Ge1-xSnx)半导体材料沉积到约1纳米到约50纳米之间的厚度。
在不利用初始硼掺杂剂前体,即在过程框120期间不将初始硼掺杂剂引入到反应腔室中的实施例中,锗锡(Ge1-xSnx)半导体材料可最初作为未掺杂材料而沉积。应注意,本文中,术语“未掺杂”还可指“无意地掺杂”,因为所沉积的锗锡(Ge1-xSnx)半导体可包括可能导致锗锡半导体的无意掺杂的杂质及/或缺陷。在利用初始硼掺杂剂前体,即在过程框120期间将初始硼掺杂剂引入到反应腔室中的实施例中,锗锡(Ge1-xSnx)半导体可最初作为p型锗锡半导体而沉积,初始载流子浓度大于1×1018掺杂剂/立方厘米或大于1×1019掺杂剂/立方厘米或甚至大于1×1020掺杂剂/立方厘米。
沉积p型经掺杂锗锡(Ge1-xSnx)半导体材料的方法100可在过程框130之后,即在将锗锡半导体沉积在衬底的表面上之后通过停止所有前体气体到反应腔室中的流动而继续。举例来说,在一些实施例中,所述方法可进一步包括在将锗锡(Ge1-xSnx)半导体沉积在衬底的表面上之后从反应腔室移除锗前体和锡前体。除了停止锗前体和锡前体的流动之外,在沉积锗锡之后保持在反应腔室中的锗前体和锡前体可通过流体连接到反应腔室的真空系统从反应腔室排空。
方法100可用过程框140继续,其包括将所沉积的锗锡(Ge1-xSnx)半导体材料暴露于硼掺杂剂前体。举例来说,在一些实施例中,所述方法可包括选择硼掺杂剂前体以包括二硼烷(B2H6)或三氯化硼(BCl3)中的至少一个。此外,在一些实施例中,硼掺杂剂前体可以大于0.01sccm或大于0.1sccm或甚至大于1sccm的流动速率引入到反应腔室中。在本公开的一些实施例中,将锗锡(Ge1-xSnx)半导体材料暴露于硼掺杂剂前体可进一步包括将锗锡(Ge1- xSnx)半导体材料暴露于硼掺杂剂前体达约1秒与约60秒之间的时间段。应注意,在锗锡(Ge1-xSnx)半导体材料暴露于硼掺杂剂前体期间,不将锗前体或锡前体引入到反应腔室中,即,硼掺杂剂前体单独地且独自地引入到反应腔室中。
方法100可在过程框150继续,其中决策门确定方法100继续还是退出。过程框150的决策门是基于所沉积的锗锡(Ge1-xSnx)半导体材料的厚度而确定,例如,如果锗锡半导体的厚度对于所要装置结构来说不足,则方法100可返回到过程框120,且可重复两次或更多次以下处理:将衬底暴露于锗前体和锡前体、将锗锡半导体沉积在衬底的表面上,以及将锗锡半导体暴露于硼掺杂剂前体。换句话说,方法100可包括沉积循环,其中沉积循环包括:将衬底暴露于锗前体和锡前体、沉积锗锡(Ge1-xSnx)半导体材料,以及将锗锡(Ge1-xSnx)半导体材料暴露于硼掺杂剂前体。在本公开的一些实施例中,方法100可包括执行两个或更多个沉积循环,直到沉积所要厚度的p型经掺杂锗锡(Ge1-xSnx)半导体材料。
在本公开的一些实施例中,执行两个或更多个沉积循环进一步包括将锗锡(Ge1- xSnx)半导体材料沉积到约40纳米与约60纳米之间的厚度。此外,执行两个或更多个沉积循环可包括将p型锗锡(Ge1-xSnx)半导体材料以所要掺杂剂浓度沉积到所要厚度。因此,本公开的方法可包括将锗锡(Ge1-xSnx)半导体材料暴露于硼掺杂剂前体,且可进一步包括将锗锡(Ge1-xSnx)半导体材料掺杂到大于约1×1020掺杂剂/立方厘米或大于约5×1020掺杂剂/立方厘米或甚至大于约1×1021掺杂剂/立方厘米的掺杂剂浓度。应了解,本公开的方法使得能够沉积具有显著锡(Sn)组成的锗锡(Ge1-xSnx)半导体材料,同时维持高掺杂浓度。因此,在本公开的一些实施例中,所述方法可包括沉积锡(Sn)组成大于x=0.01且掺杂剂浓度大于1×1021掺杂剂/立方厘米的锗锡(Ge1-xSnx)半导体材料。在本公开的其它实施例中,所述方法可包括沉积锡(Sn)组成大于x=0.04且掺杂剂浓度大于1×1020掺杂剂/立方厘米的锗锡(Ge1-xSnx)半导体材料。
一旦锗锡(Ge1-xSnx)半导体材料已沉积到所要厚度、组成和掺杂剂浓度,所述过程就可退出160,且可从反应腔室移除衬底以用于额外装置制造过程。然而,在本公开的一些实施例中,在从反应腔室移除衬底之前,衬底可经受生长后退火处理以有可能进一步活化p型掺杂剂和/或使p型掺杂剂再分布于锗锡(Ge1-xSnx)半导体材料的整个厚度中。在一些实施例中,对锗锡(Ge1-xSnx)半导体材料的生长后退火可在完成两个或更多个沉积循环之后执行,且可进一步包括将衬底加热到约350℃与约650℃之间的温度。在替代实施例中,可在锗锡(Ge1-xSnx)半导体材料已暴露于硼掺杂剂前体之后在每一个别沉积循环期间执行退火处理。
在一些实施例中,包括锗和锡的锗锡(Ge1-xSnx)半导体材料可包括小于约20at-%、小于约10at-%、小于约7at-%、小于约5at-%、小于约3at-%、小于约2at-%或小于约1at-%的杂质,所述杂质为除Ge或Sn以外的元素。在一些实施例中,包括锗和锡的锗锡层包括小于约20at-%、小于约10at-%、小于约5at-%、小于约2at-%或小于约1at-%的氢。在一些实施例中,包括锗和锡的锗锡层可包括小于约10at-%、小于约5at-%、小于约2at-%、小于约1at-%或小于约0.5at-%的碳。在一些实施例中,包括锗和锡的锗锡层可包括小于约5at-%、小于约2at-%、小于约1at-%、小于约0.5at-%或小于约0.2at-%的氮。在一些实施例中,锗锡层可包括小于约15at-%、小于约10at-%、小于约5at-%、小于约3at-%、小于约2at-%或小于约1at-%的氧。在一些实施例中,锗锡层可在表面处平均包括小于约30at-%、小于约20at-%、小于约10at-%、小于约5at-%或小于约3at-%的氧,其中所述表面可理解为距最顶部表面小于约20nm的厚度。在一些实施例中,包括锗和锡的薄膜可包括大于约80at-%、大于约90at-%、大于约93at-%、大于约95at-%、大于约97at-%或大于约99at-%的锗和锡。
本公开的实施例还可提供包括通过本文所描述的方法沉积的锗锡(Ge1-xSnx)半导体材料的半导体装置结构。举例来说,图2说明半导体装置结构200的非限制性实例,其中半导体装置结构200包括部分制造的双栅MOSFET,通常称为FinFET。半导体装置结构200可包括衬底202,所述衬底可包括块状硅(Si)衬底或者可包括“虚拟衬底”,所述“虚拟衬底”包括Si-Ge-Sn合金生长在上面的锗虚拟衬底。衬底202可用p型掺杂剂(用于NMOS型FinFET装置)或用n型掺杂剂(用于PMOS型FinFET装置)掺杂。在图2的非限制性实例半导体装置结构中,衬底202可包括n型掺杂剂,且半导体装置结构200可包括PMOSFET或明确地说PMOS FinFET。
半导体装置结构200还可包括隔离区204,其可包括浅沟槽隔离(STI)区。半导体装置结构200还可包括设置在两个隔离区204之间的鳍片结构(Fin structure)206。半导体装置结构200可包括外延再生长的源极区208A和漏极区208B,其可利用本公开的方法加以沉积。举例来说,源极区208A和漏极区208B可包括锡(Sn)组成为x=0.08且硼掺杂浓度大于约1×1019掺杂剂/立方厘米的锗锡(Ge1-xSnx)半导体材料。半导体装置结构200还可包括通过本公开的实施例形成的通道区210。举例来说,通道区210可包括锡(Sn)组成为x=0.04且硼掺杂浓度大于约1×1018掺杂剂/立方厘米的锗锡(Ge1-xSnx)半导体材料。
在本公开的一些实施例中,可制得到包括源极区208A和漏极区208B的p型锗锡(Ge1-xSnx)半导体材料的电触点。在一些实施例中,电触点(未示出)可包括硅化物,例如硅化钛(TiSi2)。本公开的实施例允许在源极区208A和漏极区208B中的高浓度的有源p型载流子,这又可导致降低对源极区和漏极区的电接触电阻。举例来说,本公开的方法可包括形成到p型源极区208A和漏极区208B的电触点,其中所述电触点具有小于1×10-8Ohm.cm2或小于5×10-9Ohm.cm2或甚至小于1×10-9Ohm.cm2的电阻率。
上文所描述的本公开的实例实施例不限制本发明的范围,这是因为这些实施例仅仅是本发明实施例的实例,本发明由所附权利要求书和其合法等效物界定。任何等效实施例都意欲在本发明的范围内。实际上,除本文中所展示和描述的如所描述元件的替代适用组合的内容以外,对于所属领域的技术人员来说,本公开的各种修改将从描述变得显而易见。此类修改和实施例也意欲属于所附权利要求书的范围内。

Claims (20)

1.一种沉积经掺杂锗锡(Ge1-xSnx)半导体的方法,包括:
在反应腔室内提供衬底;
将所述衬底加热到沉积温度;
将所述衬底暴露于锗前体和锡前体;
将锗锡(Ge1-xSnx)半导体沉积在所述衬底的表面上;以及
将所述锗锡(Ge1-xSnx)半导体暴露于硼掺杂剂前体。
2.根据权利要求1所述的方法,进一步包括在将所述锗锡(Ge1-xSnx)半导体沉积在所述衬底的表面上之后从所述反应腔室移除所述锗前体和所述锡前体。
3.根据权利要求1所述的方法,其中将所述衬底暴露于锗前体和锡前体进一步包括将所述衬底暴露于初始硼掺杂剂前体。
4.根据权利要求1所述的方法,其中将所述衬底加热到沉积温度进一步包括将所述衬底加热到约275℃与约400℃之间的沉积温度。
5.根据权利要求1所述的方法,进一步包括选择所述锗前体以包括以下中的至少一个:锗烷(GeH4)、二锗烷(Ge2H6)、三锗烷(Ge3H8)或锗烷基硅烷(GeH6Si)。
6.根据权利要求1所述的方法,进一步包括选择所述锡前体以包括四氯化锡(SnCl4)或氘化锡(SnD4)中的至少一个。
7.根据权利要求1所述的方法,进一步包括选择所述硼掺杂剂前体以包括至少一种二硼烷(B2H6)或三氯化硼(BCl3)。
8.根据权利要求1所述的方法,其中将所述衬底暴露于所述锗前体和所述锡前体进一步包括使所述锗前体与所述锡前体共流到所述反应腔室中。
9.根据权利要求1所述的方法,其中将所述锗锡(Ge1-xSnx)半导体沉积在所述衬底的表面上进一步包括将所述锗锡(Ge1-xSnx)半导体沉积到约1纳米到约15纳米之间的厚度。
10.根据权利要求1所述的方法,其中将所述锗锡(Ge1-xSnx)半导体暴露于所述硼掺杂剂前体进一步包括将所述锗锡(Ge1-xSnx)半导体暴露于所述硼掺杂剂前体达约1秒与约60秒之间的时间段。
11.根据权利要求1所述的方法,其中沉积循环包括:将所述衬底暴露于所述锗前体和所述锡前体、沉积所述锗锡(Ge1-xSnx)半导体以及将所述锗锡(Ge1-xSnx)半导体暴露于所述硼掺杂剂前体。
12.根据权利要求11所述的方法,进一步包括执行两个或更多个沉积循环。
13.根据权利要求12所述的方法,其中执行两个或更多个沉积循环进一步包括将所述锗锡(Ge1-xSnx)半导体沉积到约40纳米与约60纳米之间的厚度。
14.根据权利要求1所述的方法,其中将所述锗锡(Ge1-xSnx)半导体暴露于所述硼掺杂剂前体进一步包括将所述锗锡(Ge1-xSnx)半导体掺杂到大于约1×1021掺杂剂/立方厘米的掺杂剂浓度。
15.根据权利要求12所述的方法,进一步包括在执行两个或更多个沉积循环之后在约350℃与约650℃之间的温度下对所述锗锡(Ge1-xSnx)进行退火。
16.根据权利要求1所述的方法,其中将所述锗锡(Ge1-xSnx)半导体沉积在所述衬底的表面上进一步包括沉积锡(Sn)含量大于约x=0.05的所述锗锡(Ge1-xSnx)。
17.一种半导体装置结构,包括通过根据权利要求1所述的方法沉积的所述锗锡(Ge1- xSnx)半导体。
18.根据权利要求17所述的半导体装置结构,其中所述锗锡(Ge1-xSnx)半导体包括晶体管结构的源极区或漏极区中的至少一个。
19.根据权利要求18所述的半导体装置结构,其中所述晶体管结构包括PMOSFET。
20.根据权利要求18所述的半导体装置结构,进一步包括形成到所述晶体管结构的所述源极区或所述漏极区的电触点,其中所述电触点具有小于1×10-9Ohm.cm2的电阻率。
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