JP2013149983A - ダイナミックアレイ・アーキテクチャ - Google Patents
ダイナミックアレイ・アーキテクチャ Download PDFInfo
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- JP2013149983A JP2013149983A JP2013031124A JP2013031124A JP2013149983A JP 2013149983 A JP2013149983 A JP 2013149983A JP 2013031124 A JP2013031124 A JP 2013031124A JP 2013031124 A JP2013031124 A JP 2013031124A JP 2013149983 A JP2013149983 A JP 2013149983A
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- 238000009792 diffusion process Methods 0.000 claims abstract description 104
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000000926 separation method Methods 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 54
- 238000004519 manufacturing process Methods 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 37
- 230000003993 interaction Effects 0.000 claims description 35
- 230000006870 function Effects 0.000 claims description 22
- 230000003287 optical effect Effects 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 17
- 238000001459 lithography Methods 0.000 claims description 17
- 238000012937 correction Methods 0.000 claims description 14
- 230000002787 reinforcement Effects 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005452 bending Methods 0.000 claims description 4
- 230000010363 phase shift Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 238000010292 electrical insulation Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 description 114
- 238000013461 design Methods 0.000 description 58
- 239000011295 pitch Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 35
- 238000003491 array Methods 0.000 description 14
- 230000001066 destructive effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007792 addition Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 102100022117 Abnormal spindle-like microcephaly-associated protein Human genes 0.000 description 1
- 101000900939 Homo sapiens Abnormal spindle-like microcephaly-associated protein Proteins 0.000 description 1
- ZPCCSZFPOXBNDL-ZSTSFXQOSA-N [(4r,5s,6s,7r,9r,10r,11e,13e,16r)-6-[(2s,3r,4r,5s,6r)-5-[(2s,4r,5s,6s)-4,5-dihydroxy-4,6-dimethyloxan-2-yl]oxy-4-(dimethylamino)-3-hydroxy-6-methyloxan-2-yl]oxy-10-[(2r,5s,6r)-5-(dimethylamino)-6-methyloxan-2-yl]oxy-5-methoxy-9,16-dimethyl-2-oxo-7-(2-oxoe Chemical compound O([C@H]1/C=C/C=C/C[C@@H](C)OC(=O)C[C@H]([C@@H]([C@H]([C@@H](CC=O)C[C@H]1C)O[C@H]1[C@@H]([C@H]([C@H](O[C@@H]2O[C@@H](C)[C@H](O)[C@](C)(O)C2)[C@@H](C)O1)N(C)C)O)OC)OC(C)=O)[C@H]1CC[C@H](N(C)C)[C@@H](C)O1 ZPCCSZFPOXBNDL-ZSTSFXQOSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005923 long-lasting effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11811—Basic cell P to N transistor count
- H01L2027/11812—4-T CMOS basic cell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11811—Basic cell P to N transistor count
- H01L2027/11814—5-T CMOS basic cell
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11851—Technology used, i.e. design rules
- H01L2027/11855—Twin-tub technology
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L2027/11859—Connectibility characteristics, i.e. diffusion and polysilicon geometries
- H01L2027/11861—Substrate and well contacts
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- H01L2027/11809—Microarchitecture
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- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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Abstract
【解決手段】基板と、前記基板内で定義付けされた多数の拡散領域とを含む半導体装置。前記拡散領域は、前記基板の非活性領域によってお互いに分離されている。前記半導体装置は、前記基板の上を1つの共通方向に伸びるように定義付けされた多数の線形ゲート電極トラックを含む。線形ゲート電極トラックのそれぞれは、1つ以上の線形ゲート電極セグメントによって定義付けされている。前記基板の拡散領域と非活性領域の両方の上を伸びる線形ゲート電極トラックのそれぞれは、前記隣接する線形ゲート電極セグメント間の適切な電気的絶縁を確実にしつつ、前記線形ゲート電極トラック内の隣接する線形ゲート電極セグメントの終端間の分離距離を最小化するように定義付けされている。
【選択図】図6
Description
したがって、所定の層における平行な線形レイアウト形状の間隔は、リソグラフィ補正(例えば、OPC/RET)が最小化され、または排除されるような継続する光波の建設的な光の干渉の回りで設計される。したがって、従来のOPC/RETベース・リソグラフィプロセスと比較して、ここで定義されるダイナミックアレイは、隣接する形状の間の光の相互作用を補償するものではなく、隣接する形状の間の光の相互作用を活用するものである。
隣接する線形形状の間の光の相互作用の予測は、所定の形を描画するのに使用される光がその隣の形を補強するであろう最適な形状−形状間スペーシングの識別を可能にする。所定の層の形状−形状間スペーシングは、形状ピッチとして定義される。ここで、ピッチとは、所定の層における隣接する線形形状の中心−中心間の分離距離である。
例えば、一実施形態において、1つの層の線形形状が第1参照方向(x)に伸び、隣接する層の線形形状が、第1参照方向(x)及び第2参照方向(y)に対して対角線方向に伸びる。当然のことながら、隣接する層の直交する線形形状の配置を持つダイナミックアレイの配線接続設計のために、オープンは、線形形状で定義付けすることが可能であり、コンタクト及びヴィアは必要に応じて定義付けされる。
拡散領域は、下にある基本グリッドにより定義付けされるが、拡散領域は、拡散層の上の層についての線形形状の制限に従わなければならないものではない。拡散領域401及び403は、拡散コンタクトが配置されるように定義付けされた拡散四角405を含む。拡散領域401及び403は、外来のジョグ又はコーナを含まない。したがって、リソグラフィ解像度の使用が改良され、より正確なデバイス抽出の可能になる。さらに、n+マスク領域(412及び416)及びp+マスク領域(410及び414)が、(x),(y)グリッド上に、外来のジョグ又はノッチのない矩形として定義付けされている。この様式は、より大きな拡散領域の使用を可能とし、OPC/RETの必要性を排除し、より低い解像度及びより低いコストのリソグラフィ装置の使用を可能とする(例えば、365nmのiライン照明など)。当然のことながら、図4に描かれた、n+マスク領域416及びp+マスク領域410は、ウェル−バイアスを使用しない一実施形態のものである。ウェル−バイアスを使用する別の実施形態では、図4に示されたn+マスク領域416は、実際はp+マスク領域として定義付けされる。また、この別の実施形態では、図4に示されたp+マスク領域410は、実際はn+マスク領域として定義付けされる。
拡散コンタクトの中心のx座標=I*0.36μm,ここでIはグリッド番号;
ゲート電極形状の中心のx座標=0.18μm+I*0.36μm,ここでIはグリッド番号。
この実施形態において、メタル2トラックのピッチは、コンタクトされたゲート電極のピッチの2/3又は3/4になるように最適に設定される。したがって、この実施形態において、ゲート電極トラックとメタル2トラックは、2つのゲート電極トラック・ピッチごと、及び3つのメタル2トラック・ピッチごとに位置合わせする。例えば、90nmプロセス技術において、コンタクトされたゲート電極トラックの最適なピッチは、0.36μmであり、メタル2トラックの最適なピッチは、0.24μmである。別の実施形態において、ゲート電極トラック及びメタル2トラックは、3つのゲート電極ピッチごと、及び4つのメタル2ピッチごとに位置合わせする。例えば、90nmプロセス技術において、コンタクトされたゲート電極トラックの最適なピッチは、0.36μmであり、メタル2トラックの最適なピッチは、0.27μmである。
また、一実施形態において、隣接するメタル2トラックが割り込まれることが必要なとき、隣接するメタル2トラックの割り込みは、割り込みの隣接する位置の発生を可能な限り避けるように、割り込みのそれぞれの位置がお互いに相殺されるように行われる。特に、隣接するメタル2トラックの中の割り込みの位置は、それぞれ、見えるラインが割り込みの位置を通して存在しないように配置される。ここで、見えるラインは、基板の上を伸びるメタル2トラックの方向と垂直に伸びるものと考えられる。
・少なくとも2つのメタル1トラックがnチャンネルデバイス領域を横切って設けられる;
・少なくとも2つのメタル1トラックがpチャンネルデバイス領域を横切って設けられる;
・少なくとも2つのゲート電極トラックがnチャンネルデバイスに設けられる;及び
・少なくとも2つのゲート電極トラックがpチャンネルデバイスに設けられる。
当然のことながら、ダイナミックアレイで、製造者は、従来の制約のないレイアウトに存在するような、広範囲に変化する任意形状のレイアウト形状の組み合わせの製造調整をすることを気にする必要がない。
ダイナミックアレイを使用するデザインルール・セットは、約45デザインルールを持てばよい。したがって、デザインルールに対する設計の解析と検証を行うのに必要とされる努力は、ダイナミックアレイの制限的なトポロジにより、10以上のファクタで減少する。
Claims (43)
- 基板と、
前記基板内で定義付けされ、前記基板の非活性領域によりお互いに分離された複数の拡散領域と、
前記基板の上を、1つの共通方向に伸びるように定義付けされた複数の線形ゲート電極トラックとを有し、
前記線形ゲート電極トラックのそれぞれは、1つ以上の線形ゲート電極セグメントにより定義付けされ、
前記複数の線形ゲート電極トラックのそれぞれは、前記基板の拡散領域と非活性領域の両方の上を伸びており、隣接する線形ゲート電極セグメントの間の適切な電気的絶縁を確実にするとともに、前記隣接する線形ゲート電極セグメントの終端の間の分離距離が最小化されるように定義付けされ、
前記線形ゲート電極セグメントは、論理ゲート機能を可能にするための可変の長さを持つように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記基板は、シリコン基板であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記基板は、シリコンオンインシュレイタ基板であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記複数の拡散領域のそれぞれは、前記基板の表面と一致した平面に関して2次元的に変化する形状を持つように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記複数の拡散領域、及び上を覆っている1つ以上の線形ゲート電極セグメントのそれぞれの屈曲の間のリソグラフィプロセスにおける光相互作用が予測できるように、多くの拡散領域の屈曲トポロジが制限されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記線形ゲート電極セグメントのそれぞれは、前記基板の上の1つの方向に伸びた長さを持ち、その長さに沿って実質的に一定の縦断面形状を持つように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記複数の線形ゲート電極トラック、及び1つ以上の前記線形ゲート電極セグメントは、お互いに平行になるように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
隣接する線形ゲート電極トラックの間の中心−中心間の距離は、
前記複数の線形ゲート電極トラックの中の1つ以上の前記線形ゲート電極セグメントの製造に使用されるマスクの描画に必要なリソグラフィ補正を最小化するために、リソグラフィプロセスでの光波の建設的な干渉を最適化するように定義付けされていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記リソグラフィ補正は、光近接効果補正とレティクル補強技術の1つ又は両方を含むことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
1つ以上の前記線形ゲート電極セグメントは、隣接するセル間の橋渡しを可能にするため、セル境界を通って伸びるように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記複数の線形ゲート電極トラックは、所定の線形ゲート電極トラック内の隣接する線形ゲート電極セグメントの終端間の分離のそれぞれが、隣接する線形ゲート電極トラック内の隣接する線形ゲート電極セグメントの終端間の分離から相殺されるように定義付けされていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
隣接する線形ゲート電極セグメントの終端間の共通分離距離は、線形ゲート電極トラックのそれぞれの中で利用されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
さらに、前記複数の線形ゲート電極トラックの上で定義付けされた複数の配線層を有し、
前記複数の配線層のそれぞれは、所定の配線層内の1つの共通方向に前記基板の上を伸びるように定義付けされた複数の線形導電体トラックを含み、
前記線形導電体トラックのそれぞれは、1つ以上の線形導電体セグメントによって定義付けされ、
前記複数の線形導電体トラックのそれぞれは、隣接する線形導電体セグメントの間の適切な電気的絶縁を確実にしつつ、隣接する線形導電体セグメントの終端間の分離距離が最小化されるように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
所定の配線層内の線形導電体セグメントのそれぞれは、前記基板の上の1つの方向に伸びた長さを持ち、その長さに沿って実質的に一定の縦断面形状を持つように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
前記複数の線形導電体トラック、及び所定の配線層内の1つ以上の前記線形導電体セグメントは、お互いに平行になるように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
隣接する線形導電体トラックの間の中心−中心間の距離は、
前記複数の線形導電体トラックの中の1つ以上の前記線形導電体セグメントの製造に使用されるマスクの描画に必要なリソグラフィ補正を最小化するために、リソグラフィプロセスでの光波の建設的な干渉を最適化するように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
前記複数の線形導電体トラックは、所定の線形導電体トラック内の隣接する線形導電体セグメントの終端間の分離のそれぞれが、隣接する線形導電体トラック内の隣接する線形導電体セグメントの終端間の分離から相殺されるように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
隣接する線形導電体セグメントの終端間の共通分離距離は、所定の配線層内の線形導電体トラックのそれぞれの中で利用されていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
所定の配線層内の前記複数の線形導電体トラックは、隣接する配線層内の前記複数の導電体トラックを交差して前記基板の上を伸びるように定義付けされていることを特徴とする半導体装置。 - 請求項19記載の半導体装置において、
隣接する配線層の線形導電体トラックは、実質的に垂直にお互いに交差していることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
前記複数の線形ゲート電極トラックの上の第1配線層の前記複数の線形導電体トラックは、前記複数の線形ゲート電極トラックを実質的に垂直に交差して前記基板の上を伸びるように定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
さらに、前記複数の配線層内の選択された線形導電体セグメントに、前記複数の拡散領域を接続するように定義付けされた複数の拡散コンタクトを有していることを特徴とする半導体装置。 - 請求項22記載の半導体装置において、
隣接する拡散コンタクトの間の中心−中心間分離距離は、隣接する線形ゲート電極トラックの間の中心−中心間分離距離と本質的に等価であり、
前記複数の拡散コンタクトのそれぞれの中心は、隣接する線形ゲート電極トラックの間の本質的に中間点に対応する位置で定義付けされていることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
さらに、前記複数の配線層内の選択された線形導電体セグメントに、拡散領域の上を伸びる線形ゲート電極セグメントを接続するように定義付けされた複数のゲート電極コンタクトを有していることを特徴とする半導体装置。 - 請求項24記載の半導体装置において、
前記複数のゲート電極コンタクトは、長さと、その長さに沿った実質的に一定の縦断面形状によって定義付けされた線形形状を持つように定義付けされ、
前記複数のゲート電極コンタクトのそれぞれは、下を横たわる線形ゲート電極トラックと実質的に垂直な1つの方向に、その長さが伸びるように配向していることを特徴とする半導体装置。 - 請求項25記載の半導体装置において、
前記複数のゲート電極コンタクトのそれぞれの長さは、下を横たわる線形ゲート電極セグメントを覆うように十分に長いことを特徴とする半導体装置。 - 基板と、
トランジスタデバイスの活性領域を定義付けするために、前記基板内で定義付けされ複数の拡散領域と、
前記基板の上で1つの共通方向に配向された複数の線形ゲート電極セグメントと、
前記複数の線形ゲート電極セグメントの共通方向を実質的に垂直な方向に交差するように、前記複数の線形ゲート電極セグメントの上のレベル内に配置された複数の線形導電体セグメントとを有し、
前記複数の線形ゲート電極セグメントの多くは、拡散領域の上に配置されており、
前記拡散領域の上に配置された前記複数の線形ゲート電極セグメントのそれぞれは、前記拡散領域の上で定義付けされた必要な活性部と、前記拡散領域を越えて前記基板の上を伸びて定義付けされた画一伸長部とを含み、
前記複数の線形ゲート電極セグメントは、論理ゲート機能を可能にする可変の長さを持つように定義付けされ、
前記複数の線形導電体セグメントは、前記基板の上の共通ライン内の隣接する線形導電体セグメントの間の終端−終端間スペーシングを最小化するように定義付けされていることを特徴とする半導体装置。 - 請求項27記載の半導体装置において、
前記複数の拡散領域のそれぞれは、前記基板の表面と一致した平面に関して2次元的に変化する形状を持つように定義付けされていることを特徴とする半導体装置。 - 請求項27記載の半導体装置において、
隣接する線形ゲート電極セグメントの間の中心−中心間の距離は、
1つ以上の前記線形ゲート電極セグメントの製造に使用されるマスクの描画に必要なリソグラフィ補正を最小化するために、リソグラフィプロセスでの光波の建設的な干渉を最適化するように定義付けされていることを特徴とする半導体装置。 - 請求項27記載の半導体装置において、
前記複数の線形ゲート電極セグメントは、前記基板の上の共通ライン内の隣接する線形ゲート電極セグメントの間の終端−終端間スペーシングを最小化するように定義付けされていることを特徴とする半導体装置。 - 請求項30記載の半導体装置において、
前記基板を横断する所定のライン内の隣接する線形ゲート電極セグメントの間の終端−終端間スペーシングは、前記基板を横断する次のライン内の隣接する線形ゲート電極セグメントの間の終端−終端間スペーシングから相殺されることを特徴とする半導体装置。 - 請求項30記載の半導体装置において、
共通の終端−終端間スペーシングは、隣接する線形ゲート電極セグメントの間で使用されることを特徴とする半導体装置。 - 請求項27記載の半導体装置において、
隣接する線形導電体セグメントの間の中心−中心間の距離は、
1つ以上の前記線形導電体セグメントの製造に使用されるマスクの描画に必要なリソグラフィ補正を最小化するために、リソグラフィプロセスでの光波の建設的な干渉を最適化するように定義付けされていることを特徴とする半導体装置。 - 請求項27記載の半導体装置において、
さらに、複数の配線層を有し、
前記複数の配線層は、隣接する層内の前記複数の線形導電体セグメントを交差するように、前記基板の上を伸びるように定義付けされた複数の線形導電体セグメントを含むことを特徴とする半導体装置。 - 長さと、その長さに沿った実質的に均一の断面形状を持つ線形導電セグメントを有し、 前記線形導電セグメントは、前記線形導電セグメントが配置されているところの下にあるゲート電極と実質的に垂直な方向に伸びたその長さを持つように配向され、
前記線形導電セグメントの長さは、前記線形導電セグメントが下にある前記ゲート電極を覆うように、下にある前記ゲート電極の幅より広くなるように定義付けされていることを特徴とするゲート電極コンタクト。 - 請求項35記載のゲート電極コンタクトにおいて、
前記線形導電セグメントの幅は、前記下にあるゲート電極の幅の全体を覆うことを維持しつつ、前記線形導電セグメントのリソグラフィのひずみに適合するように定義付けされていることを特徴とするゲート電極コンタクト。 - 請求項35記載のゲート電極コンタクトにおいて、
前記線形導電セグメントの幅は、前記下にあるゲート電極の幅と実質的に等価であることを特徴とするゲート電極コンタクト。 - 請求項35記載のゲート電極コンタクトにおいて、
前記線形導電セグメントは、ポリシリコンで形成されていることを特徴とするゲート電極コンタクト。 - 基板を横断して共通グリッド上に投影されるように定義付けされた複数のコンタクトと、
前記複数のコンタクトのそれぞれを囲むように前記共通グリッド上で定義付けされた多数のサブ解像度コンタクトとを有し、
前記サブ解像度コンタクトのそれぞれは、コンタクトの解像度を補強しつつ、リソグラフィプロセス中のそれらの描画を避けるように定義付けされていることを特徴とするコンタクトレイアウト。 - 請求項39記載のコンタクトレイアウトにおいて、
前記サブ解像度コンタクトの数は、前記複数のコンタクトの1つによって占められていない、前記共通グリッド上のグリッド点位置のそれぞれを占めるように定義付けされていることを特徴とするコンタクトレイアウト。 - 請求項39記載のコンタクトレイアウトにおいて、
前記サブ解像度コンタクトのそれぞれの形状は、隣接するコンタクトのリソグラフィ補強を最適化するように定義付けされていることを特徴とするコンタクトレイアウト。 - 請求項39記載のコンタクトレイアウトにおいて、
1つ以上の前記サブ解像度コンタクトは、隣接するコンタクトのコーナ部にリソグラフィ補強を提供するためにX形状を持つように定義付けされていることを特徴とするコンタクトレイアウト。 - 請求項39記載のコンタクトレイアウトにおいて、
前記サブ解像度コンタクトの数は、リソグラフィプロセスでサブ解像度コンタクトが描画されるのを避けることを容易にするため、位相シフトマスク技術の使用を可能にするように前記共通グリッド上で定義付けされていることを特徴とするコンタクトレイアウト。
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