TW594991B - Integrated circuit with one metal layer for programming functionality of a logic operation module - Google Patents

Abstract

An integrated circuit with one metal layer for programming functionality of a logic operation module formed on a semiconductor body. The logic operation module has an input circuit and a logic gate circuit. The input circuit has n output units. Each output unit is electrically connected a first predetermined voltage level or a corresponding input port of the input circuit. The logic gate circuit is electrically connected to the input circuit, and has 2 (n-1) input ports. At least an input port of the 2 (n-1) input ports is electrically connected to a first output port of a first output unit or a second output port of the first output unit. The logic gate circuit performs a combinational function according to connections of the n output units of the input circuit and the 2 (n-1) input ports of the logic gate circuit.

Description

594991 V. Description of the invention (1) Technical field to which the invention belongs The present invention provides a metal programmable integrated circuit, especially a integrated circuit that can use a single metal layer to plan its logic operation module. In the past, electronic components (such as capacitors and resistors) were connected to each other via a rigid circuit board. However, the development of semiconductor technology has further promoted integrated circuits (ICs). In the same semiconductor process, not only the conventional electronic components are fabricated on a wafer, but the required traces are also set on the wafer at the same time. In recent years, semiconductor manufacturing has applied sub-micro process or deep subiicro process manufacturing technology to significantly reduce the wiring line width. Therefore, when planning a more complex circuit, the same The number of components that can be accommodated on a wafer can be greatly increased. In the past, due to the limitation of semiconductor technology, a system circuit required multiple chips to implement a predetermined logic operation through appropriate external connections. However, with the advancement of semiconductor processes, the size of circuits that can be accommodated by a single chip has become larger and larger. A plurality of chips of the system circuit can be integrated to reduce the number of required chips and external wiring. As an example, = In the industry, an overview of System On a Chip (SOC) has been released.

Page 6 594991 V. Description of the invention (2) The idea of achieving a single chip is the goal of a system. However, such a complex chip design requires more efficient design methodology (computer-aided design, CAD) software partners to complete. The development of integrated circuits has also gradually promoted the development of electronic products. For example, 'electronic components that originally appeared on circuit boards as separate units were changed to integrated circuit types, compared to the use of metal guides between electronic components in the past. ^ (Such as copper wire) for connection, because the integrated circuit has shorter and narrower wiring, the internal parasitic capacitance generated by the wiring is greatly reduced, that is, the accuracy of the integrated circuit operation is greatly improved and is better than A circuit constructed by a conventional circuit board method. In addition, since multiple circuits can be integrated into the same integrated circuit through semiconductor manufacturing processes, the f: P product is developed towards the trend of lightness, thinness, shortness, and smallness. dissipati〇n) and production costs "Γ: Γ electricity (T '! is also greatly reduced. Portable electronics, such as (ap computer) and personal digital assistant (PDA)) ^ ± H it ^ ^ Great importance And welcome, so the extension of. ^, / A is judged that the users are flourishing. The size of the relevant portable device path driven by the f-step is not consistent. According to the knowledge, the various types of integrated circuits have the lowest power, so it can be greatly improved; because of the power loss circuit of the integrated circuit, For example, the analog integrated circuit === f, and other types of integrated circuits, the RF integrated circuit because of its power loss

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High or energy loss caused by high-frequency signal transmission due to the transition of metal wiring, so its component density cannot be increased in consideration of heat dissipation or signal transmission. In addition, with the improvement of circuits, some analog circuits with low power and high speed operation It has been combined with digital circuits into a mixed-mode integrated circuit. As mentioned above, integrated circuits have been widely used in various electronic products, and how to plan the wiring between internal components of integrated circuits has also become The progress of semiconductor manufacturing processes has expanded the circuit scale of integrated circuits. For example, a very large-scale integrated circuit (VLSI) chip design has not been handled by a single engineer, so an integrated circuit The manufacturing process is further differentiated into processes, mask layout, and component testing. As is known in the industry as pattern independence, it separates the design of the mask layout from the actual semiconductor process of the wafer, and further regulates the light according to the applied semiconductor process technology (such as the allowable wiring interval). The geometric configuration of the components and wiring in the mask layout, that is, the pattern design on the mask is performed through the known design rules, so the integrated circuit design engineer can eliminate the need to understand the actual manufacturing details of the chip. It can engage in the design of various integrated circuit chips; similarly, the chip maker does not need to know the performance details of the integrated circuit to manufacture the integrated circuit. Because of the use of this design specification, the integrated circuit design work is separated from the semiconductor process technology, which reduces the separate workload of circuit designers and chip makers.

Page 8 594991 V. Description of the invention (4) As long as the principles of the design specification are followed, the manufacturing of integrated circuits will get a yield of acceptance. Today's electronic products successively use application specific integrated circuits (ASICs) to improve the functions of the electronic products and reduce their costs. Many computer peripheral products, such as hard disk drives and scanners, The circuit boards are provided with their respective special-purpose integrated circuits. The purpose of the special-purpose integrated circuits is mainly to integrate the required circuits more efficiently on the one hand, and to protect the circuit design from being competitive on the other. Easily stolen. However, the development of a prototype system is for the manufacture of integrated circuits for this specific purpose. In recent years, the industry is looking for a rapid system prototype process method that can produce prototypes of the system in a short time. Type 'in order to verify the function of the special-purpose integrated circuit and debug the special-purpose integrated circuit, and then shorten the time-to-price of a special-purpose integrated circuit to increase its market competition Force (competitiveness). Generally speaking, the current design methods of integrated circuits can be mainly divided into gate array ar ray des i gns (full_custoIfl design), and standard cell design, The all-customer design refers to the work of the integrated circuit layout starting from the design of the transistor. Therefore, the integrated circuit design engineer needs to design the layout details from the component size, component location, and connection between components. , This design method can get the best performance (such as high operation speed and low consumption

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Power, etc.) and the highest component density (that is, the smallest crystals can get the lowest production because of the small chip area, and the all-customer design method consumes the most labor, and the bureau development time (1 e ad ti me ) Is also longer. Sheet area) due to cost. However, the required design method for the layout of the quasi-cell and gate array can be used to moderately reduce the complexity of the design process. Among them, the design method of the standard cyto-gene is in the ^ 1 = spelling J cel1 library). The designed small component module plus = makes up a large circuit, so the main work content is the placement of these component modules (1) 13 (^ 1116111;) and the routing between the component modules. -The component library is composed of small circuits that have been developed in the past. Because the characteristics of the small circuits contained in the component library have been verified in the previous development stage, the combined large circuits can operate correctly and have the right rate. Higher yield. In addition, the development time can be shortened significantly due to the reduction in the cost of 2 ί Τ 幅: In ί t ^, the circuit structure of each element module group is different, so when a wafer (wafer) is formed λ η . Need a unique mask itself, n ,, each element module to create the various elements and + $ π intersect, & I, and the element mask design of each element group does not coincide with each other The geometric dimensions of the wafer manufacturing cost group are not consistent, so xa 7 ± 1 [combined with 70 molds, so it is not easy to effectively reduce the wafer area. On the other hand, for the design method of the gate array, it is a crystal Round factory

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5. Description of the invention (6) foundry) Provides standard transistors with fixed dimensions and a small distance, so the wafer fab only manufactures transistors, that is, the gate only forms semi-finished wafers containing transistor arrays, but does not enter S The required wiring between transistors, so the integrated circuit designer can design the windings between the transistors according to the hardware specifications of the transistor on the wafer. In other words, the integrated circuit designer The main work is to 'program) the metal layer (metal) Uyer on the integrated circuit.

The photomask layout is then sent to the fab for subsequent metal layer processes to form the connections between the transistors, and finally a wafer containing the integrated circuit can be manufactured, as described above It is stated that since each transistor corresponds to the same hardware specification, the same photomask can be repeatedly used to manufacture the transistor on the wafer, so the cost of the photomask required to produce the transistor can be greatly reduced.

In addition, in the conventional design method of the gate array, the semiconductor base is only manufactured in advance to a contact layer through a semiconductor process, so the designer of the integrated circuit must enter the photomask according to the function of the integrated circuit. Pattern design 'so that the semiconductor process forms a corresponding metal layer on the contact layer to set the required wiring to activate the functionality of the integrated circuit. However, with the rapid development of semiconductor process technology, the width of wiring lines in integrated circuits has also become narrower. In contrast, the photomasks required for semi-conductor processes have become more and more precise. In other words, the The price will increase significantly with the progress of the semiconductor process. Therefore, because the conventional gate array technology requires multiple photomasks to generate windings on the metal layer, the cost of the integrated circuit produced by the conventional gate array technology is therefore increased.

Page 11 594991 V. Description of the invention (7) The rise affects the competitiveness of the integrated circuit in the market. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an integrated circuit that can use a single metal layer to plan its logic operation module to solve the above problems. The patent application scope of the present invention provides a logic operation module formed on a semiconductor body of a semiconductor circuit, which includes an input circuit and a logic gate circuit. The input circuit includes n output units, and each output unit is electrically connected to a first predetermined voltage level or a corresponding input terminal of the input circuit. The logic gate circuit is electrically connected to the input circuit and includes 2 (η ~ υ input terminals, and at least one of the 2 (η-υ input terminals) is electrically connected to the first output unit of the input circuit. The first output terminal or the second output terminal. The logic operation module may correspond to a combination of logic according to the positions of the n output units of the input circuit and the 2 (n—υ input terminals of the logic gate circuit). Function (combinational function) 〇 The scope of patent application of the present invention also provides a logic operation module formed on a semiconductor body of a semiconductor circuit, which includes an input circuit and a logic gate circuit. The input circuit includes There are n output units, and each output unit is electrically connected to a first predetermined voltage level or a corresponding input terminal of the input circuit. The logic gate circuit is

Page 12 594991 V. Description of the invention (8) Electrically connected to the input circuit, which contains only 2 (nM) input terminals, each of the 2 (1 υ input terminals) is electrically connected to the first A predetermined voltage level, a second predetermined voltage level, or a first output terminal or a second output terminal of a first output unit of the input circuit. The logic operation module may be based on the n output units of the input circuit and The positions where the 2 (ηM) input terminals of the logic gate circuit are electrically connected form a combined logic function. The semiconductor base of the integrated circuit of the present invention is manufactured in advance by a fab with a plurality of operation blocks. , And each operation block is provided with a logical operation module, and the logical operation module includes a plurality of planning nodes for planning the functions of the logical operation module. Therefore, for a logical operation module, a product The circuit designer only needs a layer of mask pattern design to determine the planning of the plurality of planning nodes to design the function of the logic operation module. Therefore, the fab can then design the The windings required to implement the functions of the logic operation module are set on the subordinate layer. In addition, in the logic operation module of the present invention, a plurality of planning nodes are arranged in the least horizontal track, so they are formed in subsequent semiconductor processes. In the metal layer, it is possible to have a larger space for setting the windings between the various operation blocks. In other words, the logic operation module of the integrated circuit of the present invention can use less in the manufacturing process of the integrated circuit. Mask, which can significantly reduce production costs.

Page 13 594991 V. Description of the invention (9) Please refer to FIG. 1. FIG. 1 is a schematic diagram of a semiconductor body 10 of the integrated circuit of the present invention. The semiconductor base 10 includes a plurality of basic unit blocks 12. In this embodiment, the operation blocks 12 are arranged on the semiconductor base in a matrix manner. Setting a correspondingly higher component density, that is, reducing the area required for the semiconductor base 10 and reducing the size of the integrated circuit. However, the operation blocks 12 can also be arranged on the semiconductor base 10 in other arrangements, for example, arranged in the same row (row) or the same column (column) to form an array. Semiconductor pedestal 10 is pre-manufactured by a fab, and then an integrated circuit designer can perform relevant mask layouts for each operation block 12 in semiconductor pedestal 10 to plan each shipping nose. The winding of block 12 is completed. Finally, the fab will form at least a metal layer on the semiconductor base 10 according to the photomask layout provided by the integrated circuit designer to set each computing block 12 to implement its operation. Corresponding to the required function, each computing block 12 can then execute its function to make the integrated circuit operate normally according to the design of the integrated circuit designer. Please refer to FIG. 2, which is a functional block diagram of the operation block 12 shown in FIG. 1. The operation block 12 includes a plurality of logic operation modules 14. In this embodiment, the logic operation module 14 is used to perform a logical function operation. In addition, the operation block 12 may also include a drive module 16 and a storage module 18. The storage module 18 can be used to perform data storage functions, and the drive module 16 can be used to drive a predetermined signal, such as a data signal (data

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signal) or a temporary module 16 can be used to drive the data signal or 1 18 'at that time or to drive the module calculation result or store another logical operation module 16 of the module 12 can also be used to store the module 1. 8 storage resource module 1 4 or storage mold pulse 5 hole number (c 1 0cks the data signal or the clock signal to the logical operation 16 can also be used to drive the storage data of logic 18 and then module 14 or another One storage drives the logic operation module and then turns into another operation group (18 glnal), that is, the driving pulse signal, and the operation of the rear rotation module 14 or the storage module series operation module 14 enters the same operation. Block module 18 'In addition, the operation results of the shame zone 1 4 or the logical operation of the nose block 12 are shown in Figure 2 and Figure 3. Figure 3 is the logical operation function block shown in Figure 2. The logic operation module 14 includes a plurality of operation two 々a \ 15b, and each operation circuit 15a, 15b is used to perform a two-ja logic function (c〇mbinati〇nal functi〇n), for example, including AND logic gate . R logic gate and XOR logic logic combined logic function to process the input operation circuit 15 & and output the processed operation data. In this embodiment, the designer of the integrated circuit can plan the logic operation mode = 1 through a photomask layout. The combinational logic function executed by 1 4 is, for example, a logic operation module, 1 $ contains n input terminals. To receive n variable data, and the integrated circuit designer can plan the mask pattern layout to design the combination of the variable data processed by the logic operation module 14 and the corresponding logical function of the variable data, that is, the integrated circuit designer can Select the arithmetic circuit 1 5a, which uses sound, k variable data (η), or can be selected by the designer of the integrated circuit = ^

1 _ 594991 V. Description of the invention (11)-Calculation circuit 1 5 b, which is used to process k + m variable data (k + 仏 n). In other words, the designer of the integrated circuit can plan an appropriate mask pattern layout according to the desired combinational logic function to determine the operation circuit 15a or operation circuit 15b to be started by the logic operation module i4. Please note that in this embodiment, the β-Haiwa wafer is a basic component required for each calculation circuit 1 5 a and 1 5 b in the logic operation module 14 in advance, so the integrated circuit designer only needs to use One layer of mask can quickly set the relevant windings corresponding to the basic components to select the combinational logic function corresponding to the operation circuit 15a or the operation circuit 15b in the logic operation module 14. Please refer to FIG. 4, which is a schematic diagram of the first circuit of the logic operation module 14 shown in FIG. The logic operation module 14 includes an input circuit 20 and a logic gate circuit 22. The input circuit .2 0 includes a plurality of planning nodes 24a, 24b, and 24c, and a plurality of inverters (inverters) 25a, 25b, 25c, 26a, 26b, and 26c. The planning nodes 24a, 24b, and 24c are used for planning. (Program) The input terminals of the corresponding inverters 25a, 25b, 25c are connected to the ground voltage Gnd or the input signals la, lb,

Ic, and the inverters 25a, 25b, 25c, 26a, 26b, 26c are mainly used to output signals that are inverted to each other to the logic gate circuit 2 2, for example, the inverter 2 5 a can be output and input from the terminal A The signal I a is an inverted signal IA, and the inverter 2 6 a can output a signal IB in the same phase as the input signal I a from the terminal B. If the planning node 2 4a plans the ground voltage Gnd and inputs it to the inverter 2 5 a, then The signals IA and IB are of course ground voltage Gnd. In addition, the operation of the other inverters 25b, 26b, 25c, 26c is the same as that of the inverters 25a, 26a, and will not be repeated here.

Page 16 594991 V. Explanation of the invention (12). The logic gate circuit 22 includes a plurality of planning nodes 24d, 2 4e, 2 4 f, 2 4 g and a plurality of transistors 2 8 a, 2 8 b. The t planning node 2 4d, 24e, 24f, 24g is used for Let the signal of the input logic gate circuit 22 be a ground voltage G nd, an operating voltage V cc, a signal IA, or a signal 1 B. In this embodiment, the transistor 2 8 a is an n-type metal oxide semiconductor transistor (NMOS transistor), and the transistor 28 b is a p-type metal emulsion semiconductor transistor (PMOS transistor), and the plurality of transistors 2 8 a , 2 8 b can be formed through the conventional complementary metal oxide semiconductor transistor process. In addition, the η-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor are connected in parallel with each other (for example, two transistors 28a, 28b) and used as Transistor switches 30a, 30b. Therefore, the plurality of transistors 28a and 28b can correspond to different combination logic functions according to different plans of the planning nodes 24d, 2e, 2e, and 4g. For example, the planning node 2 4 f can plan the operating voltage vcc input logic gate circuit 2 2, the planning node 24 b plans the input signal I b input logic gate circuit 2 2 ′ and the planning node 2 4 c plans the input signal I c input logic gate Circuit 2 2 'Therefore, the series connection circuit of transistor switches 3 0 a and 3 0 b is an AND logic gate for input signals 1 b and I c, that is, only when the input signals I b and Ic are both high When the logic level is "1", the transistor switches 30a, 301) will be turned on at the same time. When the outputs of the transistor switches 30 a and 30 b pass through an inverter 32, an output signal lout is generated, that is, a NAND logic operation is finally corresponding between the output signal iout and the input signals b and Ic. In other words, in the logical operation module 14 of FIG. 3, the logical operation module 14 can be planned through the planning nodes 24a, 24b, 2 4 c, 2 4 d, 2 4 e, 2 4 f, 2 4 g. use

Page 17 594991 V. Input signals I a, I b and I c of the invention description (13) and corresponding input signals 丨 a ,! b 、 丨 ⑽ Combined logic function 'so the logic operation module 丨 4 can be applied to any combined logic function that requires one input signal, any combined logic function that requires two input signals' and any combined logic function that requires three input signals . Please refer to FIG. 5, which is a schematic diagram of the second circuit of the logic operation module 14 shown in FIG. The logic operation module 14 includes an input circuit 40 and a logic gate circuit 42. The input circuit 40 includes a plurality of planning nodes 44a, 44b, 44c, and 44d, and a plurality of inverters 45a, 45b, 45c, 45d, 46a, 46b, 46c, and 46d. Among them, the planning nodes 44a, 4 4b, 4 4 c, 4 4 d are used to plan the corresponding inverters 4 5 a, 4 5 b, 4 5 c, 4 5 d. The input terminals are connected to the ground voltage G nd or the input signals la, lb, Ic, Id, and the inverters 45a, 45b, 45c, 45d, 46a, 4 6b, 4 6 c, 4 6 d are mainly used to generate signals that are inverted to each other to the logic gate circuit 42. For example, the inverter 45a can output the signal IA inverted from the input signal I a from the terminal A, and the inverter 4 6 b can output the signal IB in phase with the input signal I a from the terminal B. The node 44a plans the ground voltage Gnd to be input to the inverter 45a, and the signals IA and IB are both ground voltage Gnd. In addition, the operation of the other inverters 45b, 46b, 45c, 46c, 45d, and 46d is the same as that of the inverters 4 5a and 4 6a and will not be repeated here. The logic gate circuit 42 includes a plurality of planning nodes 4 4 e, 4 4 f, 4 4 g, 4 4 h, 44i, 44j, 44k, 441, and a plurality of transistors 48a, 48b. Planning nodes 44e, 44f, 44g, 44h, 44i, 44j, 44k, 441 are used to

Page 18 594991 V. Description of the invention (14) ----- Planning the input logic gate circuit 4 2 The signal is ground φ

Vcc, signal ΙΑ, or signal IB. In this embodiment, the Gnd 'operating voltage is an n-type metal oxide semiconductor transistor, and the transistor 28 is an oxide semiconductor transistor, and a plurality of transistors \ 128b are p-type gold conventional complementary metal oxide semiconductor transistors. (A, 281) can be oxidized into P type metal via metal oxide semiconductor transistor and P-type metal ^ in parallel (for example, two transistors 48a, 48b) and the conductor transistors are used to connect each other ^ 〇 Use 朿 as a transistor to open Figure 5 shows the logic operation switch of the input signal of the circuit series operation mode, and the input signal of the operation mode of the operation mode of the crystal series. The corresponding group of the planning section of the crystal switch is the planning node of the planning section. Module 14 is similar to the architecture shown in Figure 4. 'The main difference is that the logic group 14 in Figure 5 can receive up to four round-in signals and plan the required combination of logical functions.' The logic shown in Figure 3 is shown. Group 1 4 can only receive at most two input signals and plan the required combinational logic function according to the three numbers. For the computing module U shown in Figure 4, 'planning node 24c corresponds to two transistors and the other planning node 24b corresponds to four (that is, 2 2) electricity'. Therefore, the logical operation module shown in Figure 3 Group 14 must use four points 24d, 24e, 24f, and 24g to control the four transistor switches corresponding to the planning node 24b. For the logic operation mode shown in Figure 5, the planning node 44d corresponds to two transistor switches. 44c corresponds to four (that is, a transistor switch, and the other point 44b corresponds to eight (that is, 2, transistor switches, because the logic operation module 14 shown must use eight rules)

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44e, 44f, 44g, 44h, 44i, 44j, 44k, 441 to control the corresponding eight transistor switches corresponding to the planning node 44b. In other words, in this embodiment, each time an input signal is added to the logic operation module 14, the planning node required for the logic gate circuit of the logic operation module 14 also needs to be doubled so that the logic operation module 14 can be planned. The combined logic function that is executed, that is, if the logic operation module 14 can process n input signals, the number of planned nodes required for its logic gate circuit is 2 (η1). To sum up, the logic operation module 14 of the present invention does not limit the number of input signals, that is, it can process various combined logic functions corresponding to the input signals. For example, the logic operation module 14 shown in FIG. 5 can Via planning nodes 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i, 24j, 24k, 241 to achieve any one of the corresponding input signals, two input signals, three input signals, or four input signals Combining logic functions. Please refer to FIG. 6, FIG. 7, FIG. 8, and FIG. 9 at the same time. Figure 6 is the first layout of the logical operation module 14 shown in Figure 4, Figure 7 is the second layout of the logical operation module 14 shown in Figure 4, and Figure 8 is shown in Figure 4 The third layout diagram of the logic operation module 14 and FIG. 9 are the fourth layout diagram of the logic operation module 14 shown in FIG. As shown in FIG. 6, the first layout of the logic operation module 14 shown in FIG. 4 is an element layer, which includes an oxide layer 92, polysilicon 94, and a contact pad. ) 96 and n-well 98, and the first metal layer (shown in the second layout diagram) and the second metal layer (shown in the third layout diagram) are arranged one by one above the element layer. To

Page 20 594991 V. Description of the invention (16) and the third metal layer (shown in the fourth layout diagram) to plan the winding. The first metal layer and the second metal layer respectively include the edges 100 and 2000 to define the basic connection of each element in the logic operation module 14, and the third metal layer is provided with corresponding planning nodes 2 Connection pads for 4 a, 2 4 b, 2 4 c, 2 4 d, 24e, 24f, 24g, ground voltage Gnd, and operating voltage Vcc. The semiconductor pedestal 10 of the integrated circuit of the present invention is prepared in advance by a wafer fab according to the first to fourth layout diagrams described above, so that a designer of an integrated circuit can design a third metal layer based on logic. Each of the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, 24g, ground voltage

Gnd and the connection pad of the operating voltage Vcc define the combinational logic function implemented by the logic operation module 14. Please refer to FIG. 4 and FIG. 10. FIG. 10 is a schematic diagram of the third metal layer 300 on the fourth layout shown in FIG. The third metal layer 300 includes a plurality of connection pads 106a, 106b, 106c, 106d > 106e ^ 106f ^ 106g ^ 107a > 107b > 107c ^ 107d ^ 107e, 107f, 107g, 107h, 107i, 107j, among which the connection The pads 106a, 106b, 106c, 106d, 106e, 106f, and 106g correspond to the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, and 24g, and the connection cheques 107a, 107b, and 107j correspond to the ground voltage. Gnd, connection pad i〇7 i corresponds to operating voltage V cc, connection 塾 1 〇 7 d, 1 〇 7 f, 1 〇 7 h corresponds to terminal B, and connection pad 1 〇 7 e, 1 〇 7 g corresponds to Endpoint A. In addition, the connection pad 107c is used as an output terminal to output the output signal Iout. As shown in FIG. 4, the planning node 2 4 a is used to plan an input signal I a or a ground voltage G n d. Therefore, the corresponding planning node on the third metal layer 3 0 0

Page 21 594991 V. Description of the invention (17) The connection pad 1 0 6 a of 2 4 a can be used to receive the input signal I a, or can be designed through a photomask pattern to form a connection through another semiconductor process 塾 1 〇6 & Winding between the connection pad 107a (corresponding to the ground voltage Gnd). Similarly, for the planning node 24g, the planned ground voltage Gnd, the operating voltage V cc, the terminal A, or the terminal B are connected to the logic gate circuit 22, so the corresponding connection on the third metal layer 300 The pad 1 〇6g can be formed by the photomask pattern design and subsequent semiconductor processes to form the connection pad 1 〇6g and the connection pad 丨 〇7 i. (Corresponding to the operating voltage Vcc), the connection pad 107d (corresponding to the end point B) , Connection pad 107e (corresponding to terminal A), or connection pad 107j (corresponding to ground voltage G nd). With regard to the connection pads 106b, 106c, 106d, 106e, and 106f corresponding to other planning nodes 2 4b, 2 4c, 2 4d, 2 4e, and 24f, the principles of their winding settings are all connected to the pad 1 〇6 g (corresponding to the planning node 2 4 a) is the same, so it will not be repeated here. In this embodiment, the connection pads i06a, i06b, and 106c corresponding to the planning nodes 24a, 24b, and 24c are arranged on the same horizontal track on the third metal layer 300, and correspond to the planning nodes 24d, 24e, 24f, 24g connection pads 106 (1, 〇6e, 〇6f, 〇6g are also placed on the second metal layer 300 to perform the same level, so the third metal layer 300 uses only four The grounding voltage, operating voltage, and connection pads of endpoints A and B can be set for each horizontal execution. Therefore, the third metal layer 300 can have a large space to set up the computing area. The windings among the logic different module 14, the drive module 16 and the storage module 1 & f in block 12 are used. In addition, in this embodiment, only one layer of mask is needed to plan the logic operation. The combined logic function of modules 14 and 4, therefore, for an integrated circuit using the semiconductor base 10, a photomask required for manufacturing the integrated circuit

Page 22 594991 5. The cost of the invention description (18) can be greatly reduced. The semiconductor base of the integrated circuit of the present invention is manufactured in advance with a plurality of arithmetic blocks through a wafer fab. Each arithmetic block is provided with a logic operation module, and the logic operation module includes a plurality of planning nodes. Therefore, for a logic operation module, an integrated circuit designer only needs one layer of mask design to plan the function of the logic operation module. Therefore, when the fab is designed based on the mask pattern, it can be used in another The windings on the metal layer to complete the functions of the logic operation module. In addition, in the logic operation module of the present invention, the plurality of planning nodes are arranged in a minimum horizontal orbit, so that in the same metal layer, there can be a large space to set the windings required between the operation blocks. . In other words, the logic operation module of the integrated circuit of the present invention can use fewer photomasks in the manufacturing process of the integrated circuit, thereby greatly reducing the production cost. In addition, the logic operation module of the integrated circuit of the present invention can apply the design flow (designf 1 0w) of the integrated circuit of a specific application to perform related logic synthesis, timing correction, and automatic layout of the logical operation module. And other operations, so when designing an integrated circuit based on the semiconductor base with the logical operation module of the present invention, there is no need to modify the design flow of the integrated circuit of a specific purpose, so the logical operation module of the present invention can Know the design process and implement it easily. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall all belong to the scope of the invention patent.

Page 23 594991 V. Description of the invention (19) Coverage. !! Page 24 594991 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic diagram of a semiconductor base of an integrated circuit of the present invention. FIG. 2 is a functional block diagram of the operation block shown in FIG. 1. FIG. 3 is a functional block diagram of the logic operation module shown in FIG. 2. FIG. 4 is a schematic diagram of a first circuit of the logic operation module shown in FIG. 2. FIG. 5 is a schematic diagram of a second circuit of the logic operation module shown in FIG. 2. FIG. 6 is a first layout diagram of the logic operation module shown in FIG. 4. FIG. 7 is a second layout diagram of the logic operation module shown in FIG. 4. FIG. 8 is a third layout diagram of the logic operation module shown in FIG. 4. FIG. 9 is a fourth layout diagram of the logic operation module shown in FIG. 4. FIG. 10 is a schematic view of the third metal layer on the fourth layout shown in FIG. Explanation of Symbols of the Drawings 10 Semiconductor base 12 Calculation block 14 Logic operation module 16 Drive module 18 Storage module 15a, 15b Operation circuit 20 ^ 40 Input circuit 22, 4 2 Logic gate circuits 24a, 24b, 24c, 24d 24e &24; 24f, 24g, 44a, 44b, 44c, 44d, 44d, 44e, 44f, 44g, 44h, 44i, 44j, 44k Planning 25a nodes, 25b, 25c, 26a, 26b, 26c, 45a, 45b, 45c,

594991 Schematic description of 45d, 4 6a, 46b, 46c Λ 4 6 d 28a, 28b, 48a, 48b φ NEC a 92 oxide layer 96 ^ 106a, 106b, 106c, 1 107a, 107b, 107c, 107d, 107i, l07j connection pads, 98n wells

94 Polycrystalline silicon 06d, 106e, 106f, 106g, 107e, 107f, 107g, 107h page 26

Claims (1)

594991 VI. Scope of patent application 1. A logic operation module formed on a semiconductor body of a semiconductor circuit, which includes: an input circuit including n output units, each output unit is electrically Connected to a first predetermined voltage level or a corresponding input terminal of the input circuit; and a logic gate circuit electrically connected to the input circuit, which includes 2 (input terminals, the 2 (η-υ input terminals) The at least one input terminal is electrically connected to the first output terminal or the second output terminal of the first output unit of the input circuit; wherein the logic operation module may be based on the n output units of the input circuit and the logic gate circuit. 2 (The positions where the input terminals are electrically connected correspond to a combinatorial function. 2. The logic operation module described in item 1 of the scope of patent application, wherein the semiconductor base includes a plurality of operation blocks And each operation block is provided with at least one logical operation module. 3. The logical operation module described in item 1 of the scope of patent application, which uses a layer of photomask (photomas k) forming a trace between the n output units and the 2 (n_1) input terminals to execute the combined logic function. 4. The logic operation module according to item 1 of the scope of patent application, wherein the logic gate The circuit contains a plurality of metal oxide semiconductor transistors (M0S transistor) ° Page 27 594991 6. Scope of patent application 5. The logic operation module described in item 4 of the scope of patent application, wherein the logic gate circuit is manufactured through a complementary metal oxide semiconductor transistor (CMOS) process. 6. The logic operation module according to item 1 of the scope of patent application, wherein the first predetermined voltage level is a ground voltage. 7. —A logic operation module formed on a semiconductor body of a semiconductor circuit, comprising: an input circuit including n output units, each output unit is electrically connected to a first A predetermined voltage level or a corresponding input terminal of the input circuit; and a logic gate circuit electrically connected to the input circuit, which includes only 2 (ηΜ) input terminals, each of the 2 (ηΜ) input terminals An input terminal is electrically connected to the first predetermined voltage level, a second predetermined voltage level 'or the first output terminal or the second output terminal of the first output unit of the input circuit; wherein the logic operation module may be based on The positions where the n output units of the input circuit and the 2 (ηM) input terminals of the logic gate circuit are electrically connected form a combined national function. 8. The logical operation module according to item 7 in the scope of the patent application, wherein the semiconductor base includes a complex unitary operation block, and each operation block is provided with at least one logical operation module. Page 28 594991 6. Scope of patent application 9. The logic operation module described in item 7 of the scope of patent application, which uses a photomask to form the n output units and the 2 (nl) input terminals. Trace to perform the combinational logic function. Page 29