JPH01287946A - Gate array - Google Patents

Abstract

PURPOSE:To contrive improvement in the efficiency of usage of a gate by a method wherein, in the basic cell, the field region on which a PMOS transistor and an NMOS transistor will be formed, is devided into two parts. CONSTITUTION:The field regions 10a and 10b, with which a PMOS transistor is formed, and the field regions 12a and 12b, with which an NMOS transistor is formed, are divided into two parts. For example, a NAND circuit is composed of two PMOS transistors of the field region 10a and the two NMOS transistors of the field region 12a, and an inverter circuit with which the signals 11 and 12 inputted to the NAND circuit are taken out to outside as a line separated from the internal signal line is constituted. The signals O2 and O3 taken out by an inverter are detected, and the arbitrary node signal of the internal circuit can be observed. As a result, even when the additional circuit such as a test circuit is constituted, the efficiency of usage of the gate can be enhanced without reducing the number of gates to be used for the intrinsic function.

Description

[Detailed Description of the Invention] (Technical Field) The present invention involves creating a master wafer in which basic cells are regularly arranged in advance, using that master wafer in common, and using different wiring masks for each product to perform different functions. The present invention relates to a gate array type semiconductor integrated circuit device that constitutes a logic circuit, and particularly relates to a gate array in which basic cells include MOS transistors having a CMO8 configuration.

(Prior Art) FIG. 9 shows a schematic plan view of one chip of an example of a gate array.

An input/output cell area 2 for transmitting and receiving input/output signals is formed around the chip, and an internal logic area (area surrounded by a broken line) 4 for configuring a logic circuit is formed inside the cell area 2. In the internal logic area 4, a basic cell column in which basic cells 6 including two or three pairs of PMOS transistors and NMOS transistors are arranged in a column to form a basic logic circuit, and a basic cell column are connected to each other. A wiring area 8 for connection is arranged.

FIG. 10 shows a conventional C:MOS type basic cell.

10 is a field region for forming a PMOS transistor, in which a P-type diffusion region is formed.

Reference numeral 12 denotes a field region for an NMOS transistor, in which an N-type diffusion region is formed.

14 is gate polysilicon. This constitutes two pairs of PMO3)-transistors and NMOS transistors.

In this basic cell, by wiring the field region 10.degree. 12 and the gate polysilicon 14, circuits such as an inverter, NAND, NOR, etc. can be constructed.

With the progress of miniaturization of processes, semiconductor integrated circuit devices have become highly integrated and highly functional, and testing of semiconductor integrated circuit devices has accordingly become extremely difficult. Testing of semiconductor integrated circuit devices requires test patterns with a high fault detection rate. It will be extremely difficult to create. Therefore, testability design that takes testing into consideration is required at the design stage of semiconductor integrated circuit devices. Therefore, it is necessary to add an extra circuit to control the logic values of nodes inside the semiconductor integrated circuit device and to make them easier to observe.

If a conventional gate array is to be designed for testability, the circuit added for this purpose will also be created using the basic cell shown in FIG. Adding test circuitry thereby reduces the number of gates available for actual functional implementation.

There is also the problem that the speed decreases due to an increase in the number of fan-outs due to the addition of a test circuit.

In logic circuits, delays may occur between gates.

Methods to introduce a delay include delay methods using gates,
Delay methods using polysilicon resistance and gate capacitance are known.

FIGS. 11 and 12 show a delay method using gates. Two stages of inverters are connected in series between nodes A and B to provide a delay. Therefore, one basic cell is used to configure a two-stage inverter as shown in FIG. 16 is a metal wiring, and 18 is a contact.

13 and 14 show a delay method using polysilicon resistance and gate capacitance (see US Pat. No. 4,516,312).

In this case as well, one basic cell is used to provide resistance and capacitance between nodes A and B.

However, according to these delay methods, the more the delay time is increased, the more basic cells must be used, and the efficiency in using the gates that can be used to realize the original function deteriorates.

(Objective) An object of the present invention is to provide a gate array that does not reduce the number of gates that can be used to achieve the original function even when additional circuits such as test circuits and delay circuits are configured. That is.

(Structure) In the gate array of the present invention, PM
The field regions in which the OS transistor and the NMo5 transistor are formed are each separated into two.

Additional circuits, such as test circuits and delay circuits, are constructed using portions of the isolated field area of the basic cell.

Examples will be specifically described below.

FIG. 1 shows a basic cell in one embodiment.

10a and 10b are field regions for forming a PMOS transistor, which are separated into two regions. P-type diffusion regions are formed in the field regions 10a and 10b. Field area 10a.

In 10b, one region 10a is large, and the other region 10b has a size that is the minimum size that allows the PMOS transistor formed there to operate. 12a, 1
2b is a field region for forming an NMOS transistor, which is also separated into two regions. N-type diffusion regions are formed in the field regions 12a, 1'2b.

Among the field regions 12a and 12b, one region 12a is large, and the other region 12b has a size that is the minimum size that allows the NMOS transistor formed there to operate.

FIGS. 2 and 3 show examples of the configuration of a NAND circuit using this basic cell to improve the observability of internal signals.

A NAND circuit is configured by two PMOS transistors in the field region 10a and two NMOS transistors in the field region 12a.
2 minimum PMOS transistors and field area 1
NAN by two minimum NMOS transistors of 2b
Each signal 11 inputted to the D circuit. An inverter circuit is configured to take out I2 to the outside as a line separate from the internal signal line.

In the figure, the hatched pattern 16 is the first layer metal wiring, the pattern 18 is the field contact, and the dashed pattern 20 is the second layer metal wiring, and the symbol 22 is the pattern 16 that is the first layer metal wiring. The pattern is a through hole that connects the second layer metal wiring 20 to the first layer metal wiring 16 and gate polysilicon 14.

In this way, the basic cell of this embodiment has one NAND
A circuit and two inverter circuits can be configured.

If the signals 02 and 03 taken out by the inverter are detected by some method, it becomes possible to observe the signal at any node of the internal circuit, and the failure detection rate in the chip state can be improved.

Since the inverter circuit for signal extraction is configured using the minimum MOS transistors, the test circuit does not need to be included in the circuit diagram that implements the original function, and there is less need to consider the test circuit.

If a conventional basic cell is used to construct the NAND circuit and inverter circuit shown in FIG. 3, one additional basic cell will be required to construct the inverter circuit. Furthermore, since the transistor size of the basic cell itself is originally large, adding an inverter circuit for signal extraction has the problem of reducing speed. However, the basic cell of this embodiment not only does not require an extra basic cell, but also the added inverter circuit uses the smallest size MOS transistor, so there is an advantage that the reduction in the original functional operation speed can be almost ignored. .

This is true not only when the original circuit is a NAND circuit, but also when the original circuit is a NOR circuit or an inverter circuit.

In this way, inverter circuits can be configured for the number of gate inputs in addition to the original function, and it is possible to configure as many signal extraction inverter circuits as the number of internal nodes.

FIGS. 4 and 5 show examples in which a multiplexer often used in test circuits is constructed using two basic cells of the embodiment.

Since the inverter circuit 24 for signal switching does not require high speed, it is configured with MOS transistors of minimum size. The signal take-out inverter circuit 26 is also composed of minimum MOS transistors.

If conventional basic cells were used, one additional basic cell would be required to configure these inverter circuits 24 and 26, but if one basic cell of this embodiment is used, this is not necessary.

FIG. 6 shows an example in which the multiplexer shown in FIGS. 4 and 5 is used as a counter test circuit.

A test circuit 27 shown in FIGS. 4 and 5 is provided between counters 28 and 30. 32°34.36 are test terminals. 32 is a terminal for inputting a test carry signal. 34 is a terminal for inputting a signal for switching between normal mode and test mode; when the switching signal is low level, the mode is normal mode; when the switching signal is high level, it is test mode. 36 is a test output terminal;
A carry signal of the counter 28 is output.

As already mentioned, this test circuit 27 can be configured with two basic cells (two gates when converted to two-manufactured NAND or NOR) in this embodiment, whereas it can be configured with three basic cells if conventional basic cells are used. basic cells (3 gates) are required.

As shown in Figs. 2 to 6, if a test circuit is configured using MOS transistors with separated minimum field regions, the observability of internal signal lines can be improved without any circuit modification. This can increase the failure detection rate. Furthermore, it is possible to suppress a decrease in internal signal speed due to the addition of a test circuit.

FIGS. 7 and 8 show an example of using the basic cell of this embodiment to produce a delay effect.

A two-stage inverter circuit Ix is provided between nodes A and H.

Connect Iy. These inverter circuits Ix.

Iy is Mo composed of separated minimum field regions
Since the S transistor is used, a more effective delay effect can be provided.

In order to provide the inverter circuit Iw with a delay effect in FIG. 8, it is also necessary to configure it using the minimum MoS transistor. The inverter circuit MIZ selects the transistor size based on the fan-out number.

By combining two large and small MOS transistors with different transistor sizes, it is also possible to delay either the rise or fall of the output. Therefore, even with the same logic element, gates with different delay characteristics can be constructed.

According to the embodiments shown in FIGS. 7 and 8, it is possible to provide an effective delay effect with good gate usage efficiency and good delay efficiency.

In the embodiment, only an example in which separated field areas are used in a separated state is shown, but the separated field areas (for example, 10a and 10b) can be connected and used in the same way as a conventional basic cell. You can also do that.

In the present invention, the field area is divided into two, but it can also be divided into three or more.

(Effects) In the gate array of the present invention, PM
Since the field regions where the OS transistor and NMo5 transistor are formed are separated into two, it is possible to improve the observability of internal signals, add a test circuit, or add a delay circuit to create a new basic cell. It is possible to configure a gate array with high gate usage efficiency.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing a basic cell of one embodiment, Fig. 2 is a plan view showing a circuit configuration example using the same embodiment, Fig. 3 is a logic circuit diagram thereof, and Fig. 4 is a plan view of the same embodiment. A plan view showing another example of a circuit configuration using basic cells, FIG. 5 is a logic circuit diagram thereof, and FIG. 6 is a circuit diagram showing an example of a design for facilitating testing of a counter using the circuit shown in FIG. 4 as a test circuit. FIG. 7 is a plan view showing an example of a delay circuit configured using the basic cell of the same embodiment;
9 is a schematic plan view showing an example of a gate array chip, FIG. 10 is a plan view showing a conventional basic cell, and FIG. 11 is a plan view showing an example of a conventional delay circuit. FIG. 12 is a logic circuit diagram thereof, FIG. 13 is a plan view showing another conventional delay circuit, and FIG. 14 is a circuit diagram thereof. 10a, 10b, 12a, 12b
--Separated field region, 14...gate polysilicon.

Claims (1)

[Claims] (1) Basic cells are arranged regularly, and each basic cell has P
A gate array that includes a MOS transistor and an NMOS transistor, and in which the fields in which both MOS transistors are formed are separated into two.