JPH05198751A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress a decrease in an operating speed of a logic circuit at the time of an ordinary operation and to reduce power consumption of a parity detector. CONSTITUTION:A two-input parity detector 8 is disconnected from a logic circuit (NAND circuit 16 and NOR circuit 17) by a transfer gate circuit 10 at the time of an ordinary operation. Thus, a decrease in the operating speed of the logic circuit is suppressed, and power consumption of the parity detector is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a test circuit.

[0002]

2. Description of the Related Art FIG. 8 is a plan view of a semiconductor integrated circuit device having a gate array. In FIG. 8, 1 is a semiconductor chip, 2 is an input / output pad, and 3 is a basic cell stage. FIG. 9 (a) is an enlarged plan view showing the basic cell stage 3 of FIG. Here, as an example of a basic cell stage, a gate gate type CMOS gate array is shown. In FIG. 9A, 4a is a source / drain region of a P-channel transistor, and 4b is a source / drain region of an N-channel transistor. 5a, 5b
Are the gates of the P-channel transistor and the N-channel transistor, respectively. 9 (b) is an equivalent circuit diagram of the basic cell stage 3 in FIG. 9 (a), and FIG.
In FIG. 6, 6 is a P-channel transistor, 7 is an N-channel transistor, and these P-channel transistor 6 and N-channel transistor 7 are circuits connected in series. In this way, the basic cell stage 3 of the gate separation system sets the gate of the transistor to VD so that the transistor at the position to be separated is turned off.
By connecting to the D power supply or the GND (ground) power supply, the transistors connected in series are divided, and the divided circuits are used to form a desired circuit. FIG. 10 shows a conceptual diagram when a desired circuit is formed on a gate array. In FIG. 10, 11 is NO
T circuit (inverter circuit), 15 is exclusive
An OR circuit, 16 is a NAND circuit, and 17 is a NOR circuit. It should be noted that FIG. 10 shows only the symbols of the gate circuits that form the desired circuit, and does not show their interconnections.

In such a semiconductor integrated circuit, it is becoming difficult to test the circuit due to the increase in the number of integrated gate circuits. Therefore, various test circuits have been proposed. For example, there are circuits such as parity detection and signature registers.

FIG. 11 is a conceptual diagram when a test circuit in which a parity detection circuit and a signature register are combined is applied to a gate array. In FIG. 11, reference numeral 8 is a 2-input parity detection circuit, and 9 is a multi-input signature register (hereinafter referred to as MISR). The 2-input parity detection circuit 8 may be an exclusive OR circuit or an exclusive NOR circuit (note that
In FIG. 11, it is indicated by an exclusive OR symbol).

Next, the operation of the conventional semiconductor integrated circuit device will be described with reference to FIG. NO during normal operation
A circuit having a certain function is realized so that a signal is input from an output stage of a logic circuit such as the R circuit 17 to an input stage of another logic circuit by wiring not shown. The 2-input parity detection circuit 8 can perform 2-input parity detection by itself, but a multi-input parity detection circuit is configured by inputting its output to the other 2-input parity detection circuit 8. Although a plurality of parity detection circuits are formed on the semiconductor chip, their outputs are input to the MISR 9. The MISR 9 is composed of a linear feedback shift register (LFSR) and compresses input data. The data compressed in the MISR 9 is output to the input / output pad 2 by the shift operation of the MISR 9 or the like, and the quality of the semiconductor chip is judged by an external LSI test device.

[0006]

As described above, in the conventional semiconductor integrated circuit device, the parity detection circuit is connected to the output stage of the logic circuit during the normal operation, so that the output stage of the logic circuit is equivalently connected. Since there is a state that a capacitor is connected, the output waveform of the logic circuit is blunted by this capacitor, and there is a problem that the operating speed of the logic circuit decreases.
Further, there is a problem that power consumption increases due to the operation of the parity detection circuit.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of reducing power consumption without slowing down the operation speed of a logic circuit. I am trying.

[0008]

A semiconductor integrated circuit device according to the first aspect of the present invention, as shown in FIG. 1, inputs an output signal of the logic circuit into a semiconductor chip 1 having a logic circuit, In a semiconductor integrated circuit device provided with a check circuit (2-input parity detection circuit 8) that outputs a check signal for determining the quality of the logic circuit, a gate circuit (transfer gate circuit 10) is provided at the input stage of the check circuit. Connected and provided. In the semiconductor integrated circuit device according to the second aspect of the present invention, when the check circuit is separated by the gate circuit as shown in FIGS. 4 and 5, the power supply (VDD power supply, GND power supply) applied to the check circuit is turned off. did.

[0009]

In the semiconductor integrated circuit device according to the first aspect of the present invention, since the check circuit is disconnected from the logic circuit by the gate circuit during normal operation, the reduction in the operation speed of the desired logic circuit is reduced. Moreover, since no signal is input to the check circuit, the power consumption of the check circuit can be reduced. A semiconductor integrated circuit device according to the second invention is
Since the power applied to the check circuit is also turned off when the check circuit is disconnected by the gate circuit, the power is not supplied to the check circuit when the check circuit is not used, so that the power consumption can be further reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a semiconductor integrated circuit device showing an embodiment of the first invention. In FIG. 1, 1 is a semiconductor chip, 2 is an input / output pad, 3 is a basic cell stage, and 8
Is a 2-input parity detection circuit as a check circuit, 9 is a multi-input signature register (MISR),
10 is a transfer gate circuit as a gate circuit,
Reference numeral 11 is a NOT circuit, 15 is an exclusive OR circuit, 16 is a NAND circuit, and 17 is a NOR circuit. The parts other than 10 are the same as those in the conventional example, and therefore, the same reference numerals are given and the following description is omitted. The transfer gate circuit 10 is provided so as to be connected between the input of the 2-input parity detection circuit 8 and the output of the NAND circuit 16 or the output of the NOR circuit 17. By turning off the transfer gate circuit 10 during the normal operation, the logic circuits of the NAND circuit 16 and the NOR circuit 17 are separated from the 2-input parity detection circuit 8.

2 (a) and 2 (b) are diagrams showing a configuration example of the transfer gate circuit of FIG. 1 by a CMOS circuit, and FIG. 2 (a) and FIG. 2 (b) are control signals inverted from each other. It is configured to work with. 2 (a),
In (b), 6 is a P-channel transistor and 7 is N-channel.
A channel transistor, 20 is a transfer gate,
TEST and TEST (inversion) are control terminals for inputting control signals, and XA and XD are data terminals through which data passes. The transfer gate 20 is configured by combining the P-channel transistor 6 and the N-channel transistor 7. Control terminals TEST and TEST
The (inversion) is connected to the N-channel transistor 7 or the P-channel transistor 6 and is connected to the P-channel transistor 6 or the N-channel transistor 7 via the NOT circuit 11. In the circuit of FIG. 2A, when the control terminal TEST is at the high level, the data terminals XD and XA are turned on, and the control terminal TEST becomes LO.
At the W level, the data terminals XD and XA are turned off. In the circuit of FIG. 2B, the control terminal TEST
When the (inversion) is at the LOW level, the data terminals XD and XA are turned on, and when the control terminal TEST (inversion) is at the HIGH level, the data terminals XD and XA are turned off.

FIG. 3 is a conceptual diagram of a semiconductor integrated circuit device showing an embodiment (second embodiment) of the second invention. In FIG. 3, reference numeral 12 is a test circuit element, and the other circuits are the same as those in FIGS. FIGS. 4A and 5A are circuit diagrams specifically showing the above test circuit.
(B) is a circuit diagram showing each circuit in more detail. In FIG. 4A, the control terminal TEST is connected via the N-channel transistor 7 and the NOT circuit 11 to one end of the power input of the P-channel transistor 6 and the 2-input parity detection circuit 8. The other end of the power input of the 2-input parity detection circuit 8 is connected to the power VDD side. FIG. 4B shows the circuit of FIG. 4A in more detail, and the NOT circuit 11 includes the P-channel transistor 6
g and an N-channel transistor 7g, the 2-input parity detection circuit 8 includes a P-channel transistor 6b.
.About.f and N-channel transistors 7b to 7f. On the other hand, in FIG. 5A, since the signal input to the control terminal TEST is inverted, the configuration shown in FIG.
Different from (a). That is, the control terminal TEST
The (inversion) is connected to one end of the power input of the N-channel transistor 7 and the 2-input parity detection circuit 8 via the P-channel transistor 6 and the NOT circuit 11. The other end of the power input of the 2-input parity detection circuit 8 is connected to the ground (GND). 5 (b) is shown in FIG.
Although the circuit (a) is shown in more detail, the structure is the same as that in FIG. As described above, in the second embodiment, as shown in FIG.
As shown in FIG. 5B, the 2-input parity detection circuit 8
It is characterized in that one end of the power supplied to is supplied from the NOT circuit 11. Then, when the transfer gate circuit 10 is in the ON state, power is supplied from the NOT circuit 11 to the 2-input parity detection circuit 8.

Next, the operation of the test circuit of FIG. 4A will be described. When the control terminal TEST is at HIGH level, N
The output of the OT circuit 11 becomes LOW level. At this time, P
The channel transistor 6 and the N-channel transistor 7 are turned on, and the data of the data terminal XD is transmitted to one input of the 2-input parity detection circuit 8. Since the output of the inverter circuit is LOW level, the GND power is supplied to the 2-input parity detection circuit 8 and the parity detection operation is performed. When the control terminal TEST is LOW level, the output of the NOT circuit 11 is HIGH level. At this time, the P-channel transistor 6 and the N-channel transistor 7 are turned off, and the data at the data terminal XD is not transmitted to one input of the 2-input parity detection circuit 8. And N
Since the output of the OT circuit 11 is HIGH level, the ground power is not supplied to the 2-input parity detection circuit 8 and the parity detection operation is not performed.

Next, the operation of the test circuit shown in FIG. 5A will be described. When the control terminal TEST (inversion) is LOW level, the output of the NOT circuit 11 becomes HIGH level. At this time, the P-channel transistor 6 and the N-channel transistor 7 are turned on, and the data at the data terminal XD is transmitted to one input of the 2-input parity detection circuit 8. NO
Since the output of the T circuit 11 is HIGH level, the VDD power is supplied to the 2-input parity detection circuit 8 and the parity detection operation is performed. When the control terminal TEST (inversion) HIGH level, the output of the NOT circuit 11 becomes LOW level.
At this time, the P-channel transistor 6 and the N-channel transistor 7 are turned off, and the data at the data terminal XD is not transmitted to one input of the 2-input parity detection circuit 8. Since the output of the NOT circuit 11 is LOW level, the VDD power is not supplied to the 2-input parity detection circuit 8 and the parity detection operation is not performed.

FIG. 6 is a layout diagram of the test circuit elements of FIGS. 4 and 5 on the gate array. FIG. 6 (a) is obtained by removing the wiring of the second layer and the through hole between the first and second layers from FIG. 6 (b) in order to clarify the wiring of the lower layer portion. FIG. 6B is a layout diagram when the circuit of FIG. 4B is realized on the gate array. The reference numerals of the transistors correspond to those of FIG. 4 (b). Further, in FIG. 6B, 23 is a contact hole, 24 is a first layer wiring, 25 is a through hole, and 26 is a second layer wiring. The contact hole 23 connects the first layer wiring 24 to the gates 5a and 5b of the transistor or the source / drain region 4a of the P-channel transistor and the source / drain region 4b of the N-channel transistor. The through hole 25 connects the first layer wiring 24 and the second layer wiring 26.

FIG. 7 is a logic circuit diagram and a layout diagram on the gate array when a 3-input NAND circuit is used. FIG. 7A is a logic circuit diagram, and the transistors 6h, 6i, 6j, 7h, 7i, and 7j in FIG. 7B form a 3-input NAND circuit 30. FIG. 7B is a layout diagram in which the circuit of FIG. 4A is combined with a 3-input NAND circuit. In the normal operation, the control signal TEST is at the LOW level, and as a result, the P-channel transistor 6 and the N-channel transistor 7 are in the OFF state.
Therefore, since the parity detection circuit is not connected to the 3-input NAND circuit, the operation speed does not decrease. As described above, in FIG. 7, the three-input NAND circuit is used as an example for description, but this circuit may be any desired circuit.

Although some of the data terminals XB of the test circuit element 12 are connected to the ground power source in FIG. 3, they may be connected to the VDD power source or another logic signal. Further, the test circuit element 12 of the present invention is a MIS.
You may use as a component of R. Further, as the control signal of the gate circuit, a latch circuit may be incorporated in the chip and supplied from the latch circuit or may be supplied from the outside via a shift register.

[0018]

As described above, according to the first aspect of the present invention, the gate circuit is provided in the preceding stage of the check circuit for judging the acceptability of the logic circuit, and the check circuit is changed from the logic circuit by the gate circuit during normal operation. Since the signal is not supplied to the check circuit during normal operation because of the disconnection structure, the operation speed of the logic circuit can be prevented from decreasing and the operation current of the check circuit can be reduced, which can reduce power consumption. According to the second invention, since the check circuit is not supplied with power when the check circuit is disconnected by the gate circuit, the power consumption can be further reduced in addition to the effect of the first invention. ..

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a semiconductor integrated circuit device showing an embodiment of the first invention.

FIG. 2 is a circuit diagram of a transfer gate circuit of the device of FIG.

FIG. 3 is a conceptual diagram of a semiconductor integrated circuit device showing an embodiment of the second invention.

FIG. 4 is a circuit diagram of test circuit elements of the apparatus of FIG.

5 is a circuit diagram of another test circuit element of the device of FIG.

FIG. 6 is a layout diagram on the gate array of the test circuit elements of FIGS. 4 and 5;

FIG. 7 is a logic circuit diagram and a layout diagram in which a test circuit element and another logic circuit are connected.

FIG. 8 is a conceptual diagram of a conventional semiconductor integrated circuit device.

9 is a diagram showing the basic cell stages that make up the gate array of the device of FIG. 8. FIG.

10 is a conceptual diagram when a logic circuit is connected to the device of FIG.

FIG. 11 is a conceptual diagram of a case where a test circuit is connected to the logic circuit of FIG.

[Explanation of symbols]

1 semiconductor chip 2 input / output pad 3 basic cell stage 4a source / drain region of P-channel transistor 4b source / drain region of N-channel transistor 5a gate of P-channel transistor 5b gate of N-channel transistor 6 P-channel transistor 7 N-channel transistor 8 2-input parity detection circuit 9 Multi-input signature register (MIS
R) 10 transfer gate circuit 11 NOT circuit 12 test circuit element 23 contact hole 24 first layer wiring 25 through hole 26 second layer wiring

Claims (2)

[Claims] 1. A semiconductor integrated circuit device provided with a check circuit for inputting an output signal of the logic circuit and outputting a check signal for determining pass / fail of the logic circuit in a semiconductor chip having the logic circuit. A semiconductor integrated circuit device, wherein a gate circuit is connected to an input stage of the check circuit, and the check circuit is disconnected from the logic circuit by the gate circuit during normal operation. 2. The semiconductor integrated circuit device according to claim 1, wherein the power applied to the check circuit is turned off when the check circuit is disconnected by the gate circuit.