JPH04320060A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit having a macro cell to be simply replaced with a macro cell having the same function in a stage of designing a semiconductor integrated circuit device by a master slice type. CONSTITUTION:In a master slice LSI in which a plurality of macro cells for constituting a predetermined logical function (2-input AND gate), formed of a combination of predetermined number (four) of basic cells 1-3 and 5, the cells for realizing the same logical function are formed by unifying the number of the basic cells and positions of input/output terminals A, B, Y. If a driving capacity is desirably altered without varying the function on the way of designing, mere replacement of the cell is sufficient, and necessity of altering disposition and wiring upon alteration of the cell having the same function is eliminated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit comprising a combination of a predetermined number of basic cells and a plurality of macro cells each having a predetermined logical function.

0002

2. Description of the Related Art FIGS. 3 and 4 show a case in which a semiconductor integrated circuit device is manufactured using the conventional master slicing method, in which a plurality of macro cells each consisting of a combination of a predetermined number of basic cells and having a predetermined logical function are arranged. LSI used for
(hereinafter simply referred to as "master slice LSI"). FIG. 3 shows a single-drive two-input AND gate, and FIG. 4 shows a double-drive two-input AND gate. ing.

As shown in FIG. 3, a single-drive two-input AND gate is composed of three basic cells 1 to 3 formed between a power supply and a ground level. Basic cells 1-3 are P-channel transistors 1a-3a, respectively.
and N-channel transistors 1b to 3b.

By combining basic cells 1 and 2, signals obtained from input terminals A and B are input, and a node between the drains of both P-channel transistors 1a and 2a and the drain of N-channel transistor 1b is input. A 2-input NOR gate with N1 as an output is configured, and the basic cell 3 connects the node N1, that is, the output of the 2-input NOR gate, as an input, and the node between the drain of the P-channel transistor 3a and the drain of the N-channel transistor 3b. An inverter is configured in which N2 is connected to output terminal Y.

[0005] In this manner, by connecting the input of one driving inverter to the output of the two-input NOR gate, a single-drive two-input AND gate is constructed.

On the other hand, as shown in FIG.
The input AND gate is composed of four basic cells 1 to 4 formed between power and ground levels. Basic cells 1 to 4 are P channel transistors 1a to 4, respectively.
4a and N-channel transistors 1b to 4b.

Similar to the single-drive two-input AND gate shown in FIG. 3, by combining basic cells 1 and 2, the signals obtained from input terminals A and B are used as input signals, and the node N1 is used as an output signal. 2 input NOR
The gate is configured and the basic cell 3 connects the node N1.
A first inverter is configured in which the input terminal N2 is connected to the output terminal Y and the node N2 is connected to the output terminal Y.

In addition, the basic cell 4 constitutes a second inverter which receives the node N1 as an input and connects the node N3 between the drain of the P-channel transistor 4a and the drain of the N-channel transistor 4b to the node N2. . That is, the first inverter and the second inverter are provided in parallel between the output of the two-input NOR gate and the output terminal Y.

In this way, by connecting the inputs of two drive inverters connected in parallel to the output of the two-input NOR gate, a double-drive two-input AND gate is constructed.

0010

[Problems to be Solved by the Invention] Conventional master slice LSIs are configured as described above, and even if each of the plurality of macro cells arranged inside has the same logic function, it is difficult to solve the problem due to differences in their driving capabilities. , Figures 3 and 4
Like the AND gate shown in , since the number of basic cells is different, the cell size is different. This is because the degree of integration can be increased by configuring the macrocell with the minimum necessary basic cells.

However, when designing an actual semiconductor integrated circuit device using the master slice method using a design means such as CAD, using the above-mentioned master slice LSI,
After performing placement and wiring using a certain macrocell, if it is found that the load capacitance applied to this macrocell exceeds the driving capacity of the macrocell, it is necessary to replace it with a macrocell that has the same logic function and has a larger driving capacity. be. At this time, there is a problem that if the cell size is different, as in the two-input AND gate shown in FIGS. 3 and 4, the entire layout and wiring must be performed again as the macro cell is changed. Furthermore, there is also the problem that even if the layout and wiring are re-executed, it is not always possible to successfully design a semiconductor integrated circuit device.

The present invention has been made to solve the above-mentioned problems, and is designed to provide a semiconductor integrated circuit having a macro cell that can easily replace a macro cell having the same function at the design stage of a semiconductor integrated circuit device using the master slice method. The purpose is to obtain.

[0013]

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention is composed of a combination of a predetermined number of basic cells, in which a plurality of macro cells having a predetermined logic function are arranged, and the macro cells realize the same logic function. The number of basic cells and the positions of input/output terminals are unified.

[0014]

[Operation] In this invention, the macro cells that realize the same logic function are configured with the same number of basic cells and the positions of input/output terminals, so even if they have different driving capacities, if they have the same logic function, , there is no change in the cell size of the macrocell or the position of the input/output terminals.

[0015]

Embodiment FIGS. 1 and 2 are circuit diagrams showing the configuration of one macrocell of a master slice LSI which is an embodiment of the present invention, and FIG. 1 shows a single-drive two-input AN
FIG. 2 shows a double-driven two-input AND gate.

As shown in FIG. 1, the single-drive two-input AND gate is composed of four basic cells 1 to 3 and 5 formed between the power supply and ground levels. Basic cells 1 to 3 and 5 are P channel transistors 1a to 3a and 5a and N channel transistors 1b to 5, respectively.
3b and 5b.

By combining basic cells 1 and 2, the signals obtained from input terminals A and B are used as input signals, and the signal between the drains of both P-channel transistors 1a and 2a and the drain of N-channel transistor 1b is A two-input NOR gate is configured with the node N1 as the output, and the basic cell 3 outputs the node N1, that is,
The output of the 2-input NOR gate is input, and the drain of the P-channel transistor 3a and the N-channel transistor 3b are connected to each other.
An inverter is constructed in which a node N2 between the drain and the output terminal Y is connected to the output terminal Y.

Furthermore, the basic cell 5 is a transistor block, and the internal P-channel transistor 5a and N-channel transistor 5b are kept in an electrically floating state, so that they are not involved in the logic function of the macro cell at all.

In this manner, by connecting the input of one driving inverter to the output of the two-input NOR gate, a single-drive two-input AND gate is constructed.

On the other hand, as shown in FIG.
The input AND gate, like the single-drive two-input AND gate shown in FIG. 1, is composed of four basic cells 1 to 3 and 5 formed between the power supply and ground levels. Basic cells 1-3 and 5 each include P-channel transistors 1a-3a and 5a and N-channel transistors 1b-3b and 5b.

[0021]The single drive AN shown in FIG.
Similar to the D gate, by combining basic cells 1 and 2, a 2-input NOR gate is configured with the signals obtained from input terminals A and B as input signals and the node N1 as an output. A first inverter is configured in which N1 is input and node N2 is connected to output terminal Y. Here, the positions of the input terminals A, B and the output terminal Y are made to match the positions of the input terminals A, B and the output terminal Y of the single-drive AND gate shown in FIG.

In addition, the basic cell 5 constitutes a second inverter having the node N1 as an input and the node N4 between the drain of the P-channel transistor 5a and the drain of the N-channel transistor 5b connected to the node N2. That is, the first inverter and the second inverter are provided in parallel between the output of the two-input NOR gate and the output terminal Y.

In this way, by connecting the inputs of two drive inverters connected in parallel to the output of the two-input NOR gate, a double-drive two-input AND gate is constructed.

As described above, if the macro cells arranged in the master slice LSI of this embodiment have the same logic function, the cell size can be reduced by configuring them with the same number of basic cells regardless of the magnitude of their driving capacity. unify the
Furthermore, the input and output positions are matched.

[0025] Therefore, by design means such as CAD,
When designing an actual semiconductor integrated circuit device using the master slice method using the master slice LSI of this embodiment,
After performing placement and wiring using the macrocell of this example, it was determined that the load capacitance applied to this macrocell exceeded its driving capacity, and it was necessary to replace it with a macrocell that had the same logic function and had a larger driving capacity. However, the design can be changed simply by replacing the macrocell with a macrocell that has the same cell size and input/output terminal positions, so there is no need to change the layout and wiring when changing the macrocell with the same logic function.

[0026]

[Effects of the Invention] As explained above, according to the present invention, macro cells realizing the same logical function are configured with the same number of basic cells and the positions of input/output terminals.
Even if they have different driving capabilities, if they have the same logic function, there will be no change in their cell size and input/output positions.

Therefore, the master slice LS of the present invention
When designing an actual semiconductor integrated circuit device using the master slice method using I, if you want to change the driving capacity without changing the logic function during the design process, you can simply replace the macro cell, and the same logic function There is an effect that there is no need to change the layout and wiring as the macro cell having the structure changes.

[Brief explanation of the drawing]

FIG. 1: A master slice LS that is an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of one macrocell in I. FIG.

FIG. 2: Master slice LS which is an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of one macrocell in I. FIG.

FIG. 3 is a circuit diagram showing the configuration of one macrocell in a conventional master slice LSI.

FIG. 4 is a circuit diagram showing the configuration of one macrocell in a conventional master slice LSI.

[Explanation of symbols]

Claims (1)

[Claims] Claim 1: In a semiconductor integrated circuit in which a plurality of macro cells are arranged, each consisting of a combination of a predetermined number of basic cells and having a predetermined logic function, the macro cells realizing the same logic function are arranged according to the number of basic cells and input/output. A semiconductor integrated circuit characterized by having a configuration in which the positions of terminals are unified.