TW200423404A - Integrated circuit with one metal layer for programming functionality of a logic operation module - Google Patents

Abstract

An integrated circuit with one metal layer for programming functionality of a logic operation module formed on a semiconductor body. The logic operation module has an input circuit and a logic gate circuit. The input circuit has n output units. Each output unit is electrically connected a first predetermined voltage level or a corresponding input port of the input circuit. The logic gate circuit is electrically connected to the input circuit, and has 2<SP>(n-1)</SP> input ports. At least an input port of the 2<SP>(n-1)</SP> input ports is electrically connected to a first output port of a first output unit or a second output port of the first output unit. The logic gate circuit performs a combinational function according to connections of the n output units of the input circuit and the 2<SP>(n-1)</SP> input ports of the logic gate circuit.

Description

200423404 V. Description of the invention (1) Technical field to which the invention belongs The present invention provides a metal programmable integrated circuit, in particular a integrated circuit that can use a single metal layer to plan its logic operation module. In the past, electronic components (such as capacitors, resistors, etc.) were connected to each other via a rigid circuit board. However, the development of semiconductor technology has further promoted integrated circuits (1C). In the same semiconductor process, not only the conventional electronic components are fabricated on a wafer, but the required traces are also set on the wafer at the same time. In recent years, semiconductor processes have used sub-micro process or deep sub-micro process manufacturing techniques to significantly reduce the line width of the wiring. Therefore, when planning a more complex circuit, The number of components that can be accommodated on the same wafer can be greatly increased. In the past, due to the limitation of semiconductor technology, a system circuit required multiple chips to implement a predetermined logic operation through appropriate external connections. However, with the advancement of semiconductor processes, the size of circuits that can be accommodated by a single chip has become larger and larger. A plurality of chips of the system circuit can be integrated to reduce the number of required chips and external wiring. For example, the industry has proposed an overview of System On a Chip (SOC).

200423404 V. Description of the invention (2) The idea of achieving a single chip is the goal of a system. However, such a complicated chip design requires more efficient design methods (meth0d〇1〇gy ^ computer-aided design (computer-aided design, CAD) software collaboration, helpers can be completed. The development of integrated circuit is also gradually Drive the development of electronic products. For example, electronic components that originally appeared as independent units on circuit boards were changed to be made in the form of body circuits. Compared to the past, electronic components were made of gold 1 f wires (such as copper wires). Connected, because of the integrated circuit and narrow wiring, the internal parasitic capacitance generated by the wiring = 'two, which makes the accuracy of integrated circuit operation greatly improved and excellent' so that it can be integrated in the same product stomach through semiconductor processing Hard, circuit electronic products are generally oriented towards light, thin, power dissipation products, power dissipation (uptop computer) and personal, for example (personal digital assistant Pda, &lt; Attention and welcome, so it further brings 'the party to the user's extensive development. In theory, any circuit =: portable device formed on a single chip' In practical terms, the size of the body circuit process path is not consistent. Among them, the digital product has the lowest power loss, so the component density can be greatly improved, and due to the power loss circuit, such as analog integrated circuit, RF product Because of its power loss,

R7 £ Page 7 200423404 V. Description of the invention (3) High or high frequency signal transmission causes energy loss in the transmission of high-frequency signals, so the component density cannot be increased under consideration of loose or signal transmission. Circuit improvement. Some low-power and high-speed analog circuits have been combined with digital circuits into mixed-mode integrated circuits. As mentioned above, integrated circuits have been widely used in various electronic products. It is also an important issue to plan the wiring between the internal components of the integrated circuit. Due to the advancement of semiconductor manufacturing processes, the circuit scale of integrated circuits has been expanded. For example, the chip design of a very large-scale integrated circuit (VLSI) has been beyond the manpower of a single engineer, so an integrated circuit The manufacturing process of the circuit is further divided into tasks such as manufacturing process, mask layout, and component testing. As is known in the industry as pattern independence, it separates the design of the mask layout from the actual semiconductor process of the wafer, and further regulates the light according to the applied semiconductor process technology (such as the allowable wiring interval). The geometric configuration of the components and wiring in the mask layout, that is, the pattern on the mask (pattern wide design) through a known design rule, so the integrated circuit design engineer can eliminate the need to understand the actual manufacturing details of the chip. Can be engaged in the design of a variety of integrated circuit chips; Similarly, the chip manufacturer does not need to know the performance details of the integrated circuit to engage in the manufacture of the integrated circuit. Because of the use of the design specification, the integrated circuit design The work is separated from the semiconductor process technology, which reduces the separate workload of circuit designers and chip makers.

200423404 V. Description of the invention (4) As long as the principles of this design specification are followed, the manufacture of integrated circuits is acceptable for yield. Zhizai to today's electronic products have successively adopted application specific integrated circuits (ASTC ^) to increase the functionality of the electronic product and reduce its cost. Many computer-side equipment products, such as hard drives and scanners Etc., each circuit is provided with its own special-purpose integrated circuit. The purpose of the special-purpose circuit is mainly to integrate the required circuits more efficiently on the one hand, and to protect the circuit design from being difficult on the other. It was easily stolen by competitors. However, the development of a prototype system was the bottleneck for the manufacture of integrated circuits for this specific purpose. In recent years, the industry has been looking for a prototype method for rapid system prototypes. The prototype of the system can be made in a short time, in order to verify the function of the special-purpose integrated circuit and debug the special-purpose integrated circuit, and then shorten the time to market of the special-purpose integrated circuit (tim. et〇—In order to increase its market competitiveness (competitiveness). In general, the current design methods of integrated circuits can be mainly divided into full Customer design (full-cust〇ln design) 'gate array design, and standard cell design, in which all-customer design refers to the integrated circuit layout work from the design of the basic transistor Beginning, so the integrated circuit design engineer needs to design the layout details such as the size of the component, the location of the component, and the wiring between the components. This design method can obtain the best performance (such as high operation speed and low Consume

I1H 200423404 V. Description of the invention (5) Power, etc.) and the highest component density (that is, the smallest chip area with a minimum m hinge) to obtain the lowest system u. Therefore, Wang ’s design method consumes the most manpower. The second bureau also has a long lead time. The design method of the standard cell prototyping and gate array is complicated, and the standard cell prototyping design cen library has a small design. In order to make a large-scale circuit, the main work is the placement of the internal mouthpiece module and the winding of the component module f 34 to 70 (routing). The component library is a small electrical component that has been developed in the past. Due to the verification of the characteristics of the small circuit contained in the component library in the previous development stage, the combined large-scale mine: ^ probability can operate correctly and have a high yield. In addition, the manpower consumed by the second two ^ can be Significantly reduced, so development time can be greatly reduced and shortened. The disadvantage is that the circuit structure of each component module is different. Therefore, when forming each component module on a wafer, each component The group itself needs a unique photomask design, that is, it requires more light. To produce the various component modules required, and the photomask designs of each component module are incompatible with each other, resulting in higher wafer manufacturing costs. In addition, the geometrical dimensions of the modules are not consistent, so it is not easy to effectively reduce the wafer area. On the other hand, for the design method of the gate array, it is one

A7Q

200423404 V. Description of the invention (6) (foundry) Provides standard transistors of a fixed size and allowable spacing between wirings. Therefore, the fab only manufactures transistors, that is, only the transistor arrays are formed on the wafer. The semi-finished product of the wafer, but does not perform the required wiring between the transistors, so the integrated circuit designer can design the windings between the transistors according to the hardware specifications of the transistors on the wafer, in other words The main work of the integrated circuit designer is to program the mask layout of the metal layer on the integrated circuit, and then send the mask layout to the fab for subsequent metal layers. The process is to complete the connection between the transistors, and finally a wafer containing the integrated circuit can be manufactured. As described above, since each transistor corresponds to the same hardware specification, the same photomask can be used repeatedly to manufacture the transistor. The crystal is on the wafer, so the cost of the photomask required to produce the transistor can be greatly reduced. In addition, in the conventional gate array design method, the semiconductor base is only manufactured in advance to a contact layer through a semiconductor process, so the designer of the integrated circuit must perform a photomask according to the function of the integrated circuit. The pattern is designed so that the semiconductor process forms a corresponding metal layer on the contact layer to set the required wiring to activate the functionality of the integrated circuit. However, with the rapid development of semiconductor process technology, the width of wiring lines in integrated circuits has also become narrower. In contrast, the photomasks required for semiconductor processes have become more and more precise. In other words, the grid of photomasks It will increase significantly with the progress of semiconductor processes. Therefore, because the conventional gate array technology requires multiple photomasks to generate windings on the metal layer, the cost of the integrated circuit produced by the conventional gate array technology is caused.

200423404 V. Description of the invention (7) The rise affects the competitiveness of the integrated circuit in the market. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an integrated circuit that can use a single metal layer to plan its logic operation module to solve the above problems. The patent application scope of the present invention provides a logic operation module formed on a semiconductor body of a semiconductor circuit, which includes an input circuit and a logic gate circuit. The input circuit includes n output units, and each output unit is electrically connected to a first predetermined voltage level or a corresponding input terminal of the input circuit. The logic gate circuit is electrically connected to the input circuit and includes 2 (ηM) input terminals. At least one of the 2 (η_1) injection terminals is electrically connected to the first output unit of the input circuit. The first output terminal or the second output terminal. The logic operation module may correspond to a combined logic function according to the positions of the n output units of the input circuit and 2 (n_υ Yu input terminals) of the logic circuit. combinational function) 〇

The patent application scope of the present invention further provides a logic operation module formed on a semiconductor body of a semiconductor circuit, which includes an input circuit and a logic gate circuit. The input circuit package includes n output units, and each output unit is electrically connected to a first predetermined voltage level or a corresponding input terminal of the input circuit. The logic gate circuit is 200423404 V. Description of the invention (8) il) Electrically connected to the input circuit 'It only contains 2 (η-υ input terminals, each) of the input terminals are electrically connected to The first predetermined electrical calendar level | position is a second predetermined voltage level, or the first output terminal or the second output terminal of the first output I unit of the input circuit. The logic operation module 丨 can form a combined logic function according to the n output units of the input circuit and the position of the 2 (input terminals electrically connected to the logic circuit).丨 Module, | the logic | said, I, the complex number, so there should be less water in the present invention, the I layer, the line. The swap circuit reduces the productive operation of the product and the logical operation of the product. The implementation of this logical leveling track in round waste can hold the cost of manufacturing production

First, a logic operation pattern is set on the planning node to design the operation module. The operation module mask is designed on the required operation pattern of the winding node system to form the block. Therefore, the fab-based logic operation is used to plan the module. You can decide the function, a metal layer. In addition, the windings laid out between the most formed metals can greatly increase:

Page 13 200423404 V. Description of the invention (9) Please refer to Figure 1 for the abbreviation of C, and refer to Figure 1. Figure 1 is a schematic diagram of the semiconductor body (semiconductor body) 10 of the integrated circuit of the present invention. The semiconductor base 10 includes a plurality of computing blocks (basic unit) 12. In this embodiment, the computing blocks 12 are arranged in a matrix on the semiconductor base 10 to enable the computing blocks. The setting of 12 corresponds to a higher element density, that is, a smaller area required for the semiconductor base 10 and a reduction in the size of the integrated circuit. In addition, the operation blocks 12 can also be arranged on the semiconductor substrate 10 in other arrangements, for example, arranged in the same row (row) or the same column (column) to form an array. The semiconductor pedestal 10 is first manufactured by a fab, and then an integrated circuit designer can perform a related photomask layout for each operation block 12 of the semiconductor pedestal 10 to plan each operation block. 1 2 winding, at last the fab will form at least one gold layer on the semiconductor base 10 according to the photomask layout provided by the integrated circuit design to set each computing block 12 to implement its corresponding function The required connection, and then each operation block 12 can perform its function to make the integrated circuit operate normally according to the design of the integrated circuit designer. Please refer to FIG. 2, which is a functional block diagram of the operation block 12 shown in FIG. 1. The operation block 12 includes a plurality of logic operation modules 14. In this embodiment, the logic operation module 14 is used to perform a logical function operation. In addition, the operation block 12 may also include a driving module 16 and a storage module 18. The storage module 18 can be used to perform data storage functions, and the drive module 16 can be used to drive a predetermined signal, such as a data signal (data

ft§3 p. 14 200423404

= ignal or clOck signai, that is, driving f 尸 ke to drive the data signal or the clock signal, and then input the data signal or the clock signal to the logic operation module 丨 4 Or the storage module or the driving module 16 can also be used to drive the nose operation result of the logical operation module 14 or the storage data of the storage bottle group 18 and then enter another logical operation module i 4 of the same operation block 12 or another A storage module i 8. In addition, the driving module 16 can also be used to drive the operation result of the logical operation module 14 or the storage data of the f module 18 and then input the logical operation module of another operation block 2 and 1 4 or storage module 1 8. Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a functional block diagram of the logic operation module 14 shown in FIG. The logic operation module 丨 4 includes a plurality of operation circuits 15a and 15b. Each operation circuit i5a and 15b is used to execute a combined logic function, for example, operation circuit 15a may include an AND logic gate. , Logic logic gates, logic logic gates, X0R logic gates and other combined logic functions to process the input operation circuit 15a data, and output the processed computing data. In this embodiment, the designer of the integrated circuit can plan a combined logic function executed by the logic operation module 14 through a photomask layout. For example, the logic operation module 14 includes n input terminals for Receiving n variable data, and the designer of the integrated circuit can plan the layout of the mask pattern to design a combination of the variable data processed by the logic operation module 14 and the corresponding logical function of the variable data, that is, the integrated circuit design The operator may select an operation circuit 15a, which is used to process k variable data (η), or the designer of the integrated circuit may select an operation circuit

§34 Page 15 200423404 V. Description of the invention (11) The arithmetic circuit 15b is used to process k + m variable data (k + mg η). In other words, the designer of the circuit of the non-integral body can plan an appropriate mask pattern layout according to the desired combinational logic function to determine the operation circuit 15a or operation circuit 15b to be started by the logic operation module i4. Please note that, in this embodiment, the wafer fab prepares the basic components required for each operation circuit 15a, 15b in the logic operation module 14 in advance, so the integrated circuit designer only needs to use one layer The photomask can quickly set the relevant windings corresponding to the basic components to select the combined logic function corresponding to the operation circuit 15 a or the operation circuit 15 b in the logic operation module 14. Please refer to FIG. 4, which is a schematic diagram of the first circuit of the logic operation module 14 shown in FIG. 2. The logic operation module 14 includes an input circuit 20 and a logic gate circuit 22. The input circuit 20 includes a plurality of planning nodes 24a, 24b, and 24c, and a plurality of inverters 25a, 25b, 25c, 26a, 26b, and 26c. The planning nodes 24a, 24b, and 24c are used for planning ( (program) The input terminals of the corresponding inverters 25a, 25b, 25c are connected to the ground voltage Gnd or the input signals la, lb,

Ic, and the inverters 25a, 25b, 25c, 26a, 26b, 26c are mainly used to output signals that are inverted to each other to the logic gate circuit 2 2, for example, the inverter 2 5 a can be output and input from the terminal A The signal I a is an inverted signal IA, and the inverter 26a can output a signal IB in the same phase as the input signal U from the terminal B. If the planning node 24a plans the ground voltage Gnd to be input to the inverter 25a, of course, the signals IA and IB are both Is the ground voltage Gnd. In addition, the operation of the other inverters 25b, 26b, 25c, 26c is the same as that of the inverters 25a, 26a, and will not be repeated here.

9ΛΚ page 16 200423404 V. Explanation of the invention (12). The logic gate circuit 22 includes a plurality of planning nodes 24d, 24e, 24f, 24g and a plurality of transistors 28a '28b, of which the planning nodes 24d, 24e, 24f, 24g are used to plan the signal input to the logic gate circuit 22 as ground Voltage G nd, operating voltage V cc, signal IA, or signal IB. In this embodiment, the transistor 28a is an n-type metal oxide semiconductor transistor (NMOS transistor), and the transistor 28b is a p-type metal oxide semiconductor transistor (PMOS transistor), and a plurality of transistors 2 8 a, 2 8 b can be formed by a conventional complementary metal oxide semiconductor transistor process. In addition, an η-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor are connected in parallel with each other (for example, two transistors 2 8 a, 2 8 b). It serves as a transistor switch 30a, 30b. Therefore, the plurality of transistors 28a and 28b can correspond to different combination logic functions according to different plans of the planning nodes 24d, 2e, 2e, and 4g. For example, the planning node 24f may plan the operating voltage Vcc input to the logic gate circuit 2 2, the planning node 2 4 b to plan the input signal I b input to the logic gate circuit 2 2, and the planning node 2 4 c to plan the input signal I c to input the logic gate Circuit 2 2 'Therefore, the series connection circuit of the transistor switches 3 0 a and 3 0 b is an AND logic gate for the input signals lb and Ic, that is, only when the input signals ib and I c are south logic standards. When the bit 1 is set, the transistor switches 30a and 30b are turned on at the same time. When the outputs of the transistor switches 30 a and 30 b pass through an inverter 32, an output signal lout is generated, that is, a NAND logic operation is finally corresponding between the output signal iout and the input signals lb and Ic. In other words, in the logical operation module 14 of FIG. 3, the logical operation module η used by the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, and 24g can be planned.

R9.a Page 17 200423404 V. Description of the invention (13) The input signals I a, I b, I c and the combined logical functions corresponding to the input signals I a, I b, I c, so the logic operation module 1 4 It can be applied to any combinational logic function that requires one input signal, any combinational logic function that requires two input signals, and any combinational logic function that requires three input signals. Please refer to FIG. 5, which is a schematic diagram of the second circuit of the logic operation module 14 shown in FIG. 2. The logic operation module 14 includes an input circuit 40 and a logic gate circuit 42. The input circuit 40 includes a plurality of planning nodes 44a, 44b, 44c, and 44d, and a plurality of inverters 45a, 45b, 45c, 45d, 46a, 46b, 46c, and 46d. The planning nodes 44a, 44b, 44c, and 44d are related to each other. The input terminals for planning the corresponding inverters 45a, 4 5b, 4 5c, 45d are connected to the ground voltage Gnd or the input signals la, lb, Ic, Id, and the inverters 45a, 45b, 45c, 45d, 46a, 46b, 46c, and 46d are mainly used to generate signals that are in antiphase to each other to the logic gate circuit 42. For example, the inverter 45a can output the signal IA inverted from the input signal I a from the terminal A, and the inverter 4 6 b can output the signal IB in phase with the input signal I a from the terminal B. The node 44a plans the ground voltage Gnd to be input to the inverter 45a, and the signals IA and IB are both ground voltage Gnd. In addition, the operation of the other inverters 45b, 46b, 45c, 46c, 45d, and 46d is the same as that of the inverters 4 5a and 4 6a and will not be repeated here. The logic gate circuit 42 includes a plurality of planning nodes 44e, 44f, 44g, 44h, 4 4i, 4 4 j, 4 4 k, 4 4 1 and a plurality of transistors 4 8 a, 4 8 b. Planning nodes 44e, 44f, 44g, 44h, 44i, 44j, 44k, 441 are used to

200423404

The signal of the input logic gate circuit 42 is planned to be a ground voltage Gnd, an operating voltage Vcc, a signal IA, or a signal IB. In this embodiment, the transistor 28 &amp; is a π-type metal oxide semiconductor transistor, and the transistor 28b is a p-type metal oxide semiconductor transistor, and the plurality of transistors 28a, 28b may be passed through a conventional complementary metal oxide semiconductor transistor. It is formed by a crystal process. In addition, a 0-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor are connected in parallel with each other (for example, the two transistors 48a and 48b) and are used as a transistor switch. The logical operation module 14 shown in FIG. 5 is similar to the logical operation module 14 shown in FIG. 4 in the circuit structure. The main difference is that the logical operation module 14 shown in FIG. 5 can receive at most. Four input signals, and the required combinational logic function is planned according to the four input signals. The logic operation module 14 shown in Figure 2 can only receive up to three input signals, and according to the three input signals To plan the required combinational logic function. For the logic nose module 14 shown in Fig. 4, 'planning node 2 4 c corresponds to two transistor switches' and the other planning point 2 4 b corresponds to four (that is, 29 electric circuits). Crystal switch, so the logic operation module shown in Figure 3 must use four planning nodes 24d, 24e, 24f, and 24g to control the corresponding four transistor switches corresponding to planning node 24b. For the logic shown in Figure 5, For the computing module 14, planning node 4 4 d corresponds to two transistor switches, and the other planning node 44 c corresponds to four (that is, 20 transistors 3 bodies, and the other planning node 44 b Corresponding to eight (ie, 2 3) transistor switches, so the logic operation module 14 shown in Figure 4 must use eight cut nodes

200423404 V. Description of the invention (15) 44e, 44f, 44g, 44h, 44i, 44j, 44k, 441 to control the corresponding eight transistor switches corresponding to the planning node 44b. In other words, in this embodiment, each time an input signal is added to the logic operation module 14, the planning node required for the logic gate circuit of the logic operation module 14 also needs to be doubled so that the logic operation module 14 can be planned. The combined logic function that is executed, that is, if the logic operation module 14 can process n input signals, the number of planned nodes required by its logic gate circuit is 2 (η_υ. In summary, the logic operation module 1 of the present invention 4 does not limit the number of input signals, that is, it can process various combined logic functions corresponding to n input signals. For example, the logic operation module 14 shown in FIG. 5 can be passed through the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i, 24j, 24k, 241 to achieve · Corresponds to one input signal, two input signals, three input signals, or any combination of four input signals. See also the figure 6, Figure 7, Figure 8, and Figure 9. Figure 6 is the first layout of the logical operation module 14 shown in Figure 4, and Figure 7 is the first layout of the logical operation module 14 shown in Figure 4. Second layout, figure eight FIG. 4 is a third layout diagram of the logic operation module 14 shown in FIG. 4, and FIG. 9 is a fourth layout diagram of the logic operation module 14 shown in FIG. 4. As shown in FIG. 6, FIG. The first layout of the logic operation module 14 is an element layer, which includes an oxide layer 92, polysilicon W 94, a contact pad 96, and an n-type well (η -well) 98, and a layer above the element layer is provided with a first metal layer (shown in the second layout diagram) and a second metal layer (shown in the third layout diagram) one by one.

SS9 Page 20 200423404 V. Description of the invention (16) and the third metal layer (shown in the fourth layout diagram) to plan the winding. The first and second metal layers respectively include windings 100 and 200 to define the basic connection of each element in the logic operation module 14, and the third metal layer is provided with corresponding planning nodes 24a. , 24b, 24c, 24d, 24e, 24f, 24g, connection pads for ground voltage Gnd, and operating voltage vcc. The semiconductor pedestal 10 of the integrated circuit of the present invention is prepared in advance by a wafer fab according to the first to fourth layout diagrams described above, so that a designer of an integrated circuit can design a third metal layer based on logic. Each of the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, 24g, ground voltage

Gnd and the connection pad of the operating voltage Vcc define the combinational logic function implemented by the logic operation module i4. Please refer to FIG. 4 and FIG. 10. FIG. 10 is a schematic diagram of the third metal layer 300 on the fourth layout shown in FIG. The third metal layer 300 includes a plurality of connection pads 106a, 106b, 106c, 106d, 106e, 106b, 106g, 107a, 107b, 107c, 107d, 107e, 107b, 107g, 107h, 107b, 107j, Among them, the connection pads 106a, 106b, 10 6c, 106d, 106e ', 106f, and 10g correspond to the planning nodes 24a, 24b, 24c, 24d, 24e, 24f, and 24g, and the connection pads 107a, 107b, and 107j are Corresponds to the ground voltage Gnd, the connection pad 107 i corresponds to the operating voltage Vcc, the connection pads 107d, 107f, and 107h correspond to the terminal B, and the connection pads 10 7e and 107g correspond to the terminal A. In addition, the connection pad 107c is used as an output terminal to output the output signal lout. As shown in FIG. 4, the planning node 24a is used to plan an input signal Ia or a ground voltage Gnd, so the corresponding planning node on the third metal layer 300

RQQ Page 21 200423404 V. Description of the invention (17) The connection pad 106a of 2 4 a can be used to receive the input signal Ia, or can be designed through a photomask pattern to form a connection pad through another semiconductor process 106 and connection Winding between pads 107a (corresponding to ground voltage Gnd). Similarly, for the planning node 24g, the planned ground voltage Gnd, the operating voltage V cc 'end A' or end B are connected to the logic gate circuit 22, so the corresponding connection pads on the third metal layer 300 1 0 6 g can be formed through the photoresist pattern design and subsequent semiconductor processes to form a connection pad 1 0 6 g and a connection pad 1 07i (corresponding to the operating voltage Vcc), a connection pad 107d (corresponding to the end point B), and a connection pad 107e (corresponds to terminal A), or the connection between 107j (corresponds to ground voltage Gnd). For the connection pads 106b, 106c, 106d, 106e, and 106f corresponding to other planning nodes 24b, 24c, 24d, 24e, and 24f, the winding setting principles are all connected to the pad 1 0 6 g (corresponding to the planning node 2 4 a) It is the same, so it will not be repeated here. In this embodiment, the connection pads 1 0 6 a, 10 6 b, 1 0 6 c corresponding to the planning nodes 2 4 a, 2 4 b, 2 4 c are arranged on the same horizontal track on the third metal layer 3 0 0 , And the connection pads 106d, 106e, 106f, and 106g corresponding to the planning nodes 24d, 24e, 24f, and 24g are also arranged on the same horizontal track on the third metal layer 300, so the third metal layer 300 uses only four horizontal tracks, ie Connection pads corresponding to the planning node, ground voltage, operating voltage, and endpoints A and B can be set. Therefore, the third metal layer 300 itself can have a larger space for setting the wiring between the logic operation module 14 in the computing block 12, the driving module 16 and the storage module 18. In addition, in this embodiment, only one layer of mask is needed to plan the combined logic function of the logic operation module 14. Therefore, for an integrated circuit using the semiconductor base 10, a mask required for manufacturing the integrated circuit

Page 22 200423404 V. Description of the invention (18) The cost can be greatly reduced. The semiconductor base of the integrated circuit of the present invention is manufactured in advance with a plurality of arithmetic blocks through a wafer fab. Each arithmetic block is provided with a logic operation module, and the logic operation module includes a plurality of planning nodes. Therefore, for a logic operation module, an integrated circuit designer only needs one layer of mask design to plan the function of the logic operation module. Therefore, when the fab is designed based on the mask pattern, it can be used in another The windings on the metal layer to complete the functions of the logic operation module are implemented. In addition, in the logic operation module of the present invention, the plurality of planning nodes are arranged in a minimum horizontal orbit, so that in the same metal layer, there can be a large space to set the required routing between different transport blocks. line. In other words, the logic operation module of the integrated circuit of the present invention can use fewer photomasks' in the manufacturing process of the integrated circuit, thereby greatly reducing the production cost. In addition, the logic operation module of the integrated circuit of the present invention may apply des i gn f 1 0w of the integrated circuit of a specific application, to perform related logic synthesis of the logical operation module. Timing correction, and automatic layout operations, so when designing an integrated circuit based on the semiconductor base with the logical operation module of the present invention, there is no need to modify the design flow of the integrated circuit of a specific purpose, so the logic of the present invention The computing module can be easily implemented through the conventional design process. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall all belong to the scope of the invention patent.

200423404 V. Description of the invention (19) Cover range.

I

Bill Page 24 200423404 Brief description of the drawings Brief description of the drawings The figure is a schematic diagram of a semiconductor base of a bulk circuit according to the present invention. Figure 1 is a functional block diagram of the operation block shown in Figure 1. Figure 2 is a functional block diagram of the logic operation module shown in the figure. FIG. 4 is a schematic diagram of a first circuit of the logic operation module shown in FIG. 2. FIG. 5 is a schematic diagram of a second circuit of the logic operation module shown in FIG. 2. FIG. 6 is a first layout diagram of the logic operation module shown in FIG. 4. FIG. 7 is a second layout diagram of the logic operation module shown in FIG. 4. FIG. 8 is a third layout diagram of the logic operation module shown in FIG. 4. FIG. 9 is a fourth layout diagram of the logic operation module shown in FIG. 4. FIG. 10 is a schematic view of the third metal layer on the fourth layout shown in FIG. Explanation of the Γ symbol of the schema

10 Semiconductor base 12 Calculation block 14 Logic operation module 16 Drive module 18 Storage module 15a, 15b Operation circuit 20 '40 Input circuit 22 ^ 42 Logic gate circuit 24a, 24b, 24c, 24d, 24e 24f, 24g, 44a, 44b, 44c '44d, 44d, 44e, 44f 44g, 44h, 44i, 4 4j, 4 4 k Planning nodes 25a, 25b, 2 5 c, 2 6 a, 26b 26c' 45a '45b, 45c, 594 Page 25 200423404 Brief description of the diagram 45d, 46a, 46b, 46c, 46d Inverter 28a, 28b, 48a, 48b Transistor 9 2 Oxide 9 9 Polycrystalline silicon 96, 106a, 106b, 106c, 106d, 106e, 106f, 106g, 107a, 107b, 107c, 107d, 107e, 107f, 107g, 107h, 107i, 107j connection pads 98n wells

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Claims (1)

200423404 6. Scope of patent application 1. A logic operation module formed on a semiconductor body of a semiconductor circuit, which includes: An input circuit including n output units, each output unit is electrically connected At a first predetermined voltage level or a corresponding input terminal of the input circuit; and a logic gate circuit electrically connected to the input circuit, which includes 2 (ηΜ) input terminals, and the 2 (ηΜ) input terminals The at least one input terminal is electrically connected to the first output terminal or the second output terminal of the first output unit of the input circuit; wherein the logic nose module can be based on the n output units of the input circuit and the logic gate circuit. No. 2 (the position of the input terminals electrically connected corresponds to a combinatorial function. Block calculation and operation. Each group of digital and analogue complex calculations has operation It is as few as two to two. It has half of its group modulo calculation. ^ 1 Set the block calculation side I in the description of the logic I each and 3. · As the logical operation module described in the first scope of the patent application, it is use A layer of photomask forms a trace between the _ output unit and the 2 (η-υ input terminals) to execute the combined logic function. 4 · The logic operation module described in item 1 of the scope of patent application, The logic gate circuit includes a plurality of metal oxide semiconductor transistors (Mos transistor) ° Page 27 200423404 6. Scope of patent application 5 · The logic operation module as described in item 4 of the scope of patent application, wherein the logic gate circuit is manufactured through a complementary metal oxide semiconductor transistor (CMOS) process. 6. The logic operation module according to item 1 of the scope of patent application, wherein the first predetermined electric dust level is a ground voltage. 7 · —A logic operation module formed on a semiconductor body of a semiconductor circuit, including: an input circuit including n output units, each output unit is electrically connected to a first A predetermined voltage level or a corresponding input terminal of the input circuit; and a logic gate circuit electrically connected to the input circuit, which includes only 2 (η_υ input terminals, each of the 2 (input terminals) Electrically connected to the first predetermined voltage level, a second predetermined voltage level, or the first output terminal or the second output terminal of the first output unit of the input circuit; wherein the logic operation module may be based on the The output unit of the input circuit and the logic gate circuit 2 (&quot;-[The position of the M solid input terminal is electrically connected to form a combined logical function (combinational function). 8. The logical operation described in item 7 of the scope of patent application A module, wherein the semiconductor base includes a plurality of arithmetic operation blocks, and each operation block is provided with at least one logical operation module. 200423404 6. Scope of patent application 9. The logic operation module described in item 7 of the scope of patent application, which uses a photomask to form the wiring between the n output units and the 2 (n_1) input terminals ( trace) to execute the combinational logic function.