TWI297446B - Delta information design closure in integrated circuit fabrication - Google Patents

Description

1297446 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating an integrated circuit component or a wafer. [Prior Art]

In ultra-large integrated circuits (VLSI), designing and manufacturing highly complex electronic circuits requires a few steps. A typical system chip (System_on_Chip, s〇c) or wafer design consists of a conceptual wafer feature, including a wafer, and various input and output terminals required. This wide-ranging design concept is transformed into a _ design, which contains various kinds of singularities described by Cai Wei, and their various functional units are described in a more detailed but still non-specific way, such as paste logic gates. Unit of the ship. Finally, these logics are converted into integrated circuit layouts and then applied to make real wafers. Therefore, the integrated circuit layout is the basis for the final fabrication of the wafer. Between design and manufacturing, people will add analytical integration tools to ensure that manufacturing and design are in line with each other. These analysis tools can detect layout errors in many ways, such as violation of design criteria (^esign-mle), or higher design errors, such as circuit logic chain errors, short circuits, or improper power supplies. One of the basic analytical techniques is the analysis technique involved in analyzing the signal time in the integrated circuit layout. The “time limit” in the integrated circuit design, which represents the transistor in the circuit, must be switched in a limited and pre-planned time margin. The time margin is pre-rhythm based on the delay of the components in the circuit... Deep submicron system chips may operate at a frequency of one billion hertz (Hz) or higher, so the transistor must be in the hundreds of megahertz In one-second time margin, the switching is completed, and the switching time is about one hundredth of a second. Therefore, high speed operating system chips require less time margin. Very small time margins are sensitive to component size and how the components are connected, especially in deep submicron system die designs. Therefore, in the design of the integrated circuit, the use of fine dimensions has a bad influence on the margin. For example, resolution enhancement techniques (i, es〇luti such as 1297446 te-ques, fat τ) can result in significant transistor switching time extensions, as they can cause the actual length and set-up of the polycrystalline spine (4) (4). Offset error (--η). Or chemical machine - mechanical grinding, CMP) will result in significant wire delay time ... prolonged, because it will cause dish-shaped effect in the high-density connection area (4) effects). Because the products made in the system 00 wipes have offset errors in various rulers and original designs, they will affect the performance. ... The chip's collection process is dominated by a high-yield wire with a high yield, and a lot of offsets are generated. However, the various time issues caused by the circuit designer must be designed to achieve a large time lag. For example, add an extra buffer to the necessary path to improve the non-gap time error. These over-specified designs make the circuit description database more complex, thus increasing manufacturing costs, die area, and wafer yield. The main reason for the above problems is the gap in the typical design and manufacturing process of the semiconductor industry. In terms of frequency, the wafer is in the design stage, the time before the production of the off-line is verified, and the wafer is used in the design (4) and the circuit (4) (netUst) is only used in the design, and will not be used in the process. Similarly, the final image printed on the wafer will not be provided to the designer. , · Yu Yu, a kind of integrated design and process in the chip design process, at the same time can establish the design ^ process groove __ improve the time and the analysis of the hybrid analysis, [invention content] v this issue, related - difficult The method of "product" is a method for systematically making integrated circuit components or wafers; the integrated design process (integrated)

Des^Manufacturing, , ^ (4) and the practice of the subdivision, and the human face circuit design. The biasing process is a progressive 4 包含 which includes a skewed shape time prediction program and/or a skewed time shape pre-requisite to process line characteristic parameters and different information. This difference in the heterozygous _ _ characteristic parameter bites 1297446 bias information 'independently re-characterizes an integrated circuit design. The biasing process provides a progressively biased output' that enhances or re-characterizes the corresponding parameters in the component and the joint without having to generate new line characteristic parameters and without having to reprocess all of the information in the circuit design. [Embodiment] An integrated design and manufacturing process having a system and a method for improving the time and shape relationship in an integrated circuit process is disclosed as follows: σ °H The system and method for manufacturing an integrated circuit is hereinafter referred to as integrated design and manufacturing. Program (g ated Desigl>Manufactiiring Processes, IDMP), which integrates information about time and shape offset errors in the integrated circuit process, and uses the method of containing the biased shape to predict the time and the deviation time Cheng, to lie in the integrated circuit design. Figure A is a block diagram of the integrated design process ((4)(4)(10)d^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The biased time profile is pre-formed by _4^% of materials to operate independently or in combination. The weaving design system _ sequence 100 Α and the time and shape constraints in the process, the fine integration of the shape of the η 合 财 财 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该After the 移 model shift error procedure, it can produce -_ chest (four) her marriage in the design stage oblique time error frr bed leak A ..., 丨 的 时间 时间 时间 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The integrated design of the 1GGA side of the sequel is based on the measurement of the size of the m drum, and is used to generate the model of the integrated circuit design (4). The rule 10 offset d rule, the order is used to provide a different process m to the integrated circuit design and used to generate bias or difference information to correspond to the product.

"Subtraction used by π. 4 different processes 1G system work together, continued (10) different information, for the face of the design and manufacture of components and the structure of the required _ parameter silk circuit design and manufacturing. 5 Hai The skewed output can be defined here as 7 1297446 Enhanced Deviation Parameter Information, "Enhanced Bias Parameter", or "Differential Information". The enhanced bias parameter information generated by the bias stream 101 can be It is introduced into the typical integrated circuit design and manufacturing process, first, for example, the automation electronic system (electr〇nic desjjgn aut〇mati〇n, eda, system), the enhanced bias parameter information has several kinds of applications The type of integrated circuit design.

For example, it can provide a separation result corresponding to various parameters, including bias information of various parameters. The enhanced bias parameter information may also include a modified or redefined _ body circuit design database, which may include linking or appending the enhanced partial parameter information to a circuit description file (netlist) ^ SPICE netlist ^ » m ^k〇Berkeley short-channel IGFET model (BSIM); it can also contain the information of the enhanced bias parameter to directly replace the circuit description in the case. Additional link points and/or component models can be imported without any restrictions based on experience, actual size, or both. In contrast to the frequency setting of the system, the bias has the difference in generating and applying parameter deviations to define the frequency circuit design. For example, the scale deviation may include one or more time differences in the integrated circuit design (may be referred to as time offset error, deviation time, or unloading and size difference (may be referred to as size offset error, deviation size) Or, the difference may also include circuit parameters for defining the integrated circuit design, such as leakage energy (4), which is not limited to, for example, resistance difference, capacitance, and electrical, and leakage as described above. The program can include a program for processing the wheeled information, such as biased information, and a program for generating a biased predetermined allocation based on one or more components or joint points. The 4-biased predetermined allocation generated by 1 may include difference information corresponding to any number of parameters, for example, including but not the resistance wire, the difference difference, the electrical difference, or the component parameter, the shape parameter, the number between the sword and the like, etc. Weaver information may be derived from other biased processes or other EDA and/or design manufacturing systems, but is not limited to the above examples. The singularity of the private 101 also produces a biased output to violate the difference or affect the circuit design. The source or the enemy of the difference is calculated. The bias output can generate 1297446, independent output depending on the source, and 5fl', for example, represents the difference of the independent capacitance value c of the components in the circuit. The divergence information of the Buqian process 101 can be provided to the Xu Xi program in the integrated circuit design process. _ These additional bias information can reduce the information and efficiently provide information on the database and other information. Use for circuit parameters. Reducing the dependency on the database can increase the efficiency of the circuit design because it reduces the number of simulation operations. Even more so, the rhythm information allows simulation operations only on the source of the difference, rather than adding new ones. After the parameters, the entire circuit needs to be re-simulated. In the following (four) towel's will introduce the detailed features of the shirt to enhance the design of the design of the body = marginal solution. Any secret this person _ this program You can understand that this i==:= mystery is used in combination, or combined with other systems, etc., but the above ^2 (four) ^ clearly understand the principle and function of the invention 'to avoid this The system of the integrated circuit is misunderstood by the implementation principle of the first method. Figure B is the block diagram excitation of the integrated design process program, and the others are in the manufacturing integrated circuit, according to the embodiment. , the whole design process ^ B w but not limited to one or more circuit design procedures 1 电路, circuit layout program η (including time analysis program 14, shape verification program life resolution enhancement technology process ^ shape pre-靡 Guo ^ Qing ___. Miscellaneous money package green "Miscellaneous time pre-order H) 2 and the deviation time shape prediction program 1Q4, but other = row operation 'or select more than several different shape time prediction program i〇2 time The shape prediction program 104 operates simultaneously. ^ Simultaneous circuit design program 10, circuit layout program 12 (InTent processes) l〇4 can be used in combination with the public, or other dragons can choose; Sequence 20, resolution enhancement technical program 22, process 庠? 4,5 ’ ^ ^ Investigating the near-private needs to select the required combination of parts, • Blood A is a private order, and can be integrated with other integrated circuit processes. 9 1297446 ^ While the s 'circuit contains _ turn the number of drums, so electronic circuit designers often rely on computer programs to assist and automate the circuit design process. This integrated design process program is a ena system or other auxiliary design and system. Therefore, in the following description of the dirty design of the integrated design process, the subroutines of the integrated design process can be individually subdivided into one or more automated electronic design systems or other ancillary design and manufacturing systems. The integrated design is based on a high-order hard-brain language, such as VHDL, Verilog, etc., and then translated into a low-level description language, such as a circuit description broadcast (nethst). A circuit description file describes the design, components, junctions, and connections of the integrated circuit, etc., which can be converted into a closed circuit image where each connection point has a corresponding connection. In a higher-order abstract description, a category circuit describes the generic netlist ^ - ^ ^ (technology-independent rirr: es). Hybrid 歧 办 办 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The technical characteristics database is also known as the unit database (4) Ijry) 'or = the poor library (device version (4), which contains the logic type, used to estimate the time and electricity alcohol number of the road (four). The process program 100B system stores the circuit description file, and then processes and verifies the circuit description file to produce a borrowing layout format, which can be directly fabricated in the production of wealth, and manufactures an integrated circuit component of the entity. The compiler converts money in electricity, produces a description language, and describes the design, such as using a hardware description language such as Verilog or VHDL. The high-order hardware description is converted into a circuit description program that describes the circuit. The components that make up the circuit and the wires that connect the components to each other (that is, the "link" or "network" of the circuit). The circuit description does not represent the position of these components on the true (four) wafer, and the forest represents the physical wire shouting route. The integrated design process program uses the circuit formula in the layout program 12 to generate a physical layout map. The decoration program 12 is determined by, for example, a configuration program and a connection program. The configuration of the components and the connection route of the wires. The component configuration program utilizes the layout of the lightning circuit. The function of the program is different from the position of each component. The position information usually includes two axial directions, such as the axis and丫, (4). 位 的 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί The data structure of the output position (x, y) of the program.

The integrated device _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ This path connects the end of the connection of the data component (4) to produce a wire layout. The path is connected to the record subtraction method, the link path, the button determines the solid line connection path, and the wires are arranged at appropriate positions on the wafer. = wire position data structure 'and component position' material structure will be used to determine the final shape of the poor material library for the manufacture of solid volume circuits.

The integrated design process program combines the integrated circuit data with the biased shape time prediction program 〇2 through any combination of programs. In addition to this, the skew shape inter-k prediction program 1〇2 may also receive size offset error information, for example, by one or more mother-shaped offset error programs. In other actual wipes, the size shift information can also be obtained from a selected combination of one or more of the programs 10-24. The size offset lag information includes at least one horizontal and/or vertical offset error information (Ad) related to the component, such as length or width mismatch, thickness offset error _, and other component parameter offsets. Errors and so on. Circuit components include components and joints that are used in general integrated circuit design. The dimensional offset error thus includes, but is not limited to, the material of each layer in the wafer and the disparate shape information of each position (x, y) (which can be expressed as "adjacent shape Ad/At" or "Δ(1/Δί"). In other words, the photoetching skew shape offset error Ad/At in an embodiment, and/or other proximity-based changes, may result in a shape offset error. The error At represents a thickness offset error that can be caused by the systematic nature of the layers of material in the wafer. The skew shape time prediction program 102 typically uses the skew shape Ad/At to integrate the time and shape offset error program in the integrated circuit 1297446 process. , that is, a program for disturbing design information in the process, such as resolution enhancement technology (RET), detection, etc., and then importing the result into the layout of the integrated circuit design. For the above purpose, the different shape The temporal prediction program 102 integrates the skewed shape Δ(1/Δί and introduces it into the circuit model to form a time description and/or an enhanced circuit model. The skewed shape temporal prediction program 102 can be used from a strong resolution Technical output forecasting tools, to generate said biasing oddly shaped Ad / At the result.

In the integrated design process program 1〇〇B, the component grain sequence including the skew shape time prediction program 1〇2 is used, and the enhanced circuit model is used to generate a model for the integrated circuit design simulation, and according to the model generation The time offset error information (Δτ) is described in more detail below. The integrated set-up process program 100 耦合 couples the time offset error information into the time analysis program 14, and can also integrate the time offset error information into one or more circuit design programs (1), layout program 12, shape verification program. The 〇, the resolution enhancement technical program 22, and the process program % may be replaced by various known EDA programs. The integrated design process can also couple time offset error information into the InTent processes 1〇4. The biased time profile program just uses the time offset error information to generate a biased feed or _, in the subsequent integrated circuit process 'and the integrated design process procedural surface, including the skewed shape _ test program ship Used in , as described below. The biased time shape deletion program has just output a different shape △_, which will be difficult to make a miscellaneous _ towel, which is condensed by Wei Ru _ technology, and can be coupled to other verification procedures in the design manufacturing process. . Figure 2 is a detailed block diagram of the integrated design process, which includes a biased flow 'application money k integrated circuit towel. According to another embodiment, the integrated design process program 3 is not limited to one or More than one circuit design program 10, circuit layout program 12 (package 3 and connection (point), a intervening analysis program M, shape verification program 2〇, solution = order 22 ' _ 蹲 24, partial paste program (4) = = between the shape _ transfer Fu (10) called just. The function of each of the above procedures can be shown in the Zhaotu t. At the same time 'the bias shape time prediction program is fragilely received from one or more sets of 12 1297446 mouth ten catch The private shape 15 and/or the shape information Δ_ of the manufacturing process 25, but is not limited thereto, to generate verification and/or time prediction. In addition, the deviation time profile deletion program has just received one or more design flows 15 and / or the shape information of the manufacturing process μ, but is not limited thereto, in order to generate the appearance gap (Δ_ estimator), and then splicing it with the different shape to consume one or more design flows 15 And/or manufacturing process 25 and/or partial __program 102. In a different shape The biasing process in the time prediction order 1〇2 usually receives information from the integrated circuit design and the different shapes as its input, which can be—or multiple forms. Then the deviation = time prediction program moves Can be taken from it and related to the increase in circuit parameters

The biased Λ'4 circuit turns are used to define or characterize a 元件 multiple components and/or junctions in an integrated circuit design. The procedural program contains information about objects related to any circuit design: and is not limited to components or joints. The extracted disparity information can include the value of the biased capacitance, the value of the distorted resistance, and/or the value of the transposed inductance. It can also be recorded in any other _ design + bribe: the time prediction program 1〇2 can also be generated. A biased (or cumulative) output that represents the source and/or location of the disparity information for a breach or a complex circuit design. For example, the partial capacitance value μ = the differential resistance value △ can represent a specific value of a capacitance c and a singular resistance r, respectively.

〇Γ 人 人 人 人 人 人 人 人 人 人 人 人 人. The skewed_inter prediction program I In the integrated circuit design, the time and shape restrictions are as described above. Time Alien ___Orders Depending on the embodiment, the skewed shape typically receives an integrated circuit design that includes many components and joints. The deviation of two = 1 = take _ information' will lead to the design. The predicted shape time is predicted to be outside the j. In addition to the partial 敝5 shape time prediction program 102 can still use the resources generated by the prediction program; Bao Qiang application of the database information in the embodiment, ^ for example; two forensic, and applied in the definition of integrated circuit design The difference in the parameters of the parameters, is not limited to resistance, capacitance, inductance, circuit or component parameters, shape parameters, and time 13 1297446 fresh shore can be designed to process the program to include the different shape time scaling and / or its: : Deviated information to produce an electronic model for use in integrated circuit design. Information, to bias "He (10) from the tiredness of the surface of the design of the design of the parameters of the different parameters of the two - and in the integrated circuit design process in the unit database and the connection point database according to ^ i change can be used to bias In the process, the development of the biased capital 'a U ", library or even, and the point of the library. In the database, the output is repaired: after the change of information 5. Early 70 w using the bias information on the original tree model The database performs appropriate progressive refinement 'the different shape time deletion program receives the entity from the integrated circuit layout and size of the partial data, and at least contains the length deviation Δ (1, and thickness deviation Lightly different At material. The entity can make a bribe == =:_ like _ or a word job. The biased shape of the coffee program is removed in the function of the entity reading the singular Ad and the link 阙 skewed _ accumulative Body circuit=When considering the components in the layout, the skew shape time prediction program can be moved—the parameter offset of the component is poor, for example, the offset capacitance value AC is extracted by the disparity information of each component. Deviation information of the parameter offset difference. The different shape ΙΙ^ΙΤ offset block difference (four)' and domain In the integrated design process, the data of the original unit database. The enhanced original database information includes independent results for each parameter offset error, and/or the use of partial or modified data library components. The modification of the model may include linking or appending parameter offset difference information to one or more circuit description programs, or models such as SPICE netlist or Berkeley short-channel IGFET model (BSIM), etc. The information contained in the _ with the difference in the parameter offset replaces the information in the original description program. The part of the joint point in the f layout, according to Wei block 122, corresponds the different shape to the rhyme circuit of a solid. Block 123, the different shape time compensation 14 I297446 = 02 by obtaining the bias information from the different shapes of the joint points △ jia, to one or more of the joint points of the two layouts The value Ac, the value of the distorted resistance is from the = sense value AL information _ _ Qin intestine block 124, the bias information obtained by using the bias information AC / △ hidden L to enhance the information of the original link database, Supply and fit the design process uses Enhanced database information includes the results for partial exclusive information △ linen, separate, and / or partial exclusive information ΔσΔΚ / Δ] ι correction seam Teaching with righteous database connected node model information.,

The modification of the component model can include a different information aC/arml link or attach to a solid circuit description program, or a towel. Yuan Lai's correction can also replace the information in the original circuit description program with information that has a biased information. In the function block 125, the 'magic shape time prediction program 1〇2 uses the enhancement model to generate the electronic model required for the integrated circuit according to the enhancement of the component and the joint point database model, and simultaneously performs time analysis of the integrated circuit model. The time analysis result includes, but is not limited to, a time offset difference M of the circuit model. According to function block 126, the different shape time prediction program 1 产出 2 produces a time result that includes a time offset difference Δτ. Figure 4 is a block diagram of the skewed shape temporal prediction program 1021, which is applied to generate a skewed δ apostrophe to correspond to the connection architecture, according to an embodiment. The different shape time prediction program 1〇21 receives one or more from the circuit design, library exchange format (LEF/design exchange format, DEF) file 402, a technical file 404 ' And a standard parasitic delay format (SPEF) file, 406. The different shape time prediction program i〇2l also receives a partial file of 4Q8, the partial shape information of the joint point. Replace the format/design exchange format (LEF/design exchange format, DEF) file 402, the technical file 404, the standard parasitic delay format (SPEF) file 406, and the information contained in the Ad file 408. It can represent one or more pre-defined integrated circuit ranges, or the entire integrated circuit design, but not limited to this. The different shape time prediction program 1021 utilizes integrated circuit design information as well as biased shapes 15 1297446 = == 二ΐ=Γ41G represents the progressive difference of the circuit parameters, to determine ^ \ ° and ° ten, the circuit parameters include but not limited The divergence resistance value ΔΪΙ and the divergence electric money different parameter are applied in the continuous surface collision control program. The partial Japanese prediction program can also use the partial function summary to generate an updated flap II to enhance The information contained in the SPEF trough 406. The enhanced spef standard 406 includes the correspondence, connection, or addition of one more than 10% of the poor to the SPEF privileged lion, as described above. 104 output differential shape Δί1/Δί rule, referring to Figure 5 of the above Figure 1 is a flow chart of the different time shape prediction program 104, according to an embodiment. The pass-away time shape prediction program has just received from one or more The time offset of the circuit model is divided into 1 time offset error information Δτ, as illustrated in the figure. In the function block (4), the = time shape prediction program will misinterpret the time offset between the single and the connected points in the circuit model. The time gap is divided by the block of t. In function block 143, 'the offset error Δτ valley contains the time offset error Δτ of the maximum and minimum values, and the time gap partition of each unit and/or the joint point. Separate次€次祖块块144, the deviation time shape prediction program 104_时_shift error ^, 4, the differential resistance value ΔΚ, the differential inductance value AL and other circuit models are biased The equation is represented by 丨·7. The above method includes, for example, the description of the unit in the m ΔΤ Τ 疋 疋 时间 时间 时间 单元 单元 单元 单元 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 5 7 In the force block 144, the deviation time shape compensation program 1〇4 uses the time-biased signal, and takes the bias information H of the county-connection point coffee offset error Δτ" to generate, for example, a bias capacitance value. Δ(:, the value of the differential resistance value, the differential inductance value, and the deviation information of the specific point. The above method includes, for example, using a time offset error of a joint point in the joint database to describe and update the link. To determine or calculate the divergence information W△ in the connection point. In function block 145, the divergence time shape prediction program 16 1297446 corresponds to each 7L fine and partial miscellaneous, and the sub-phase should be decomposed or compared. The heterogeneous message △ 〇 / △ position, in order to produce a different shape Ad. This example exemplifies the biased time shape pre-process: the process 104 can obtain the partial information of the singularity of the ship's ancestor, the second definition of any deviation information. The road right leaf diagram is a block diagram of the integrated design process program _, which includes a partial shape prediction program' and a skewed time shape prediction program for application in the integrated circuit process, according to Figure 2 and Figure 3. _ and the embodiment of Figure 5. This financial integrated design process _ It is not possible to predict the specific coupling between the program ship and the skewed time shape prediction program (10) and the system included _order 6() 2_626. The different shape time prediction process 102 and the deviation time shape prediction program The functions of 1〇4 are as described in the manual, and can also be carried out in the two-step system of Quanzhao Diagram 2 and Figure 5. The scales included in the Hall·626 are the same as the functions of the “General”, but not limited to this. ” Integration The various procedures for the sequence of training will be (4) the original (four) Cunui, to produce the tfU de-encryption unit: the miscellaneous library, the Laizu _ program. As the face, the Miaoqiang or the modified component view can be corrected. The original component _, which contains the sculpt component ^ different shape Ad. The process includes modeling each component so as to be able to extract the capacitance offset error Δ of each component from the different shape (: the above component parameter correction or The process of updating the characteristics utilizes the multi-principle principle 'the towel' is the more riding component and the domain element type is completely her. At the same time, the component parameters of the updated feature are also fully compatible with the signal delay model. The signal delay can be expressed. For Signal Delay = k(Vdd/WIon)(Cin + C〇ut + Cwire). And the component parameters of the 's-new update feature provide current conservation. According to the following current expression, the immersion-source current ("Ids,,) n(w/L^[(Vg_Vt)Vds-( m/2)Vds2] The modified component model (or IDMP component model) assumes that a transistor used in the component library does not actually have a single gate length. Moreover, the IDMp component model is疋 Assume that the transistor does not have a single gate length, and Figure 7 is a transistor 7〇〇 block diagram of an IDMP component model, the component model having a non-single gate length, according to an embodiment. The transistor 7〇〇 assumes that its gate 71〇 has a non-zero offset error at the gate length of 17 1297446. This assumption is derived from empirical data. Therefore, the gate length of the gate 710 is about 1 〇〇 nm (the gate length offset error Ad is about +10 nm) from the end point 7 〇 2 of the junction point and the end point of the polysilicon 〇 7 〇 4 It is about 80 nm (gate length offset error Δ〇1 is about -10 nm). The gate length offset error μ is +i 〇 nm and (10) as shown in this example, and is expressed everywhere in the gate length. The application of the IDMP component model is not limited to transistors having the above characteristics. The IDMP component model can also place the effect of gate length offset error on component parameters into the model. In general, because of the non-uniformity of the gate length, the IDMP component model assumes that a component contains many parasitic capacitances due to the gate length offset error Ad. For example, Figure 8 is a block diagram of a gate/junction capacitance of a transistor 700 of an IDMP component model, in accordance with an embodiment. The transistor 700 includes a substrate 802, a source region 804, a gate region 806, a depletion region 808', and a gate 810. The parasitic capacitance in the model, for example, includes at least one gate-source capacitance (Cgs), gate-drain capacitance (Cgd), source-base capacitance (Csb), gate-based Plate capacitor (Cgb), and the drain base capacitor (Cdb).

Using these parasitic capacitances, the IDMP model assumes an input capacitance (4Cin55) of the device to be approximately [

Cin = Cgs + Cgd + Cgb.

The IDMP model also assumes an output capacitance (uCout55) of the device to be approximately

Cout = Cdb + Cgd.  Using these parasitic capacitances, the IDMP model assumes that an input capacitor Cin can be expressed as Cin = Cgs + Cgd + Cgb.  The IDMP model also assumes that an output capacitor Cout can be expressed as Cout = Cdb + Cgd. It can be found in this example that the IDMP model of the transistor 700 utilizes a gate generated by a uniform idle length model and a parasitic capacitance model. The extreme length offset error Ad information can enhance the component parameters of the unit database. 18 1297446 Figure 9 illustrates a modified component model parameter 900 of a transistor having a gate length of deep sub-micron (about 1 〇〇 nm), according to an embodiment. The gate length offset error Δ of the transistor (1 is used to correct the parameters of the component model 900, including the effective channel length, the turn-on voltage, the Cgd/Cgs overlap capacitance value, the input capacitance value, the output capacitance value, and other various parameters. The gate length offset error Ad can be used to modify the parameters of other component models applied to the component. Figure 10A and Figure 10B relate to the effect of gate length offset error Ad on component operation. The signal delay of the transistor model of an integrated design process program is 1〇1〇 corresponding to the gate length offset error 1020, according to an embodiment. FIG. 10 is a saturation of the transistor model of an integrated design process program. The current 1012 corresponds to a graph of the gate length offset error 1020, according to an embodiment. In addition to the enhanced unit database, other programs of the integrated design process program also utilize the modified original EDA system to include the bias of the joints in the design. The different shape Δ〇1/Δί, resulting in a modified joint point database, as described above. The correction includes modeling the joint point so that it can be from each joint point, by The biased shape Ad/At takes one or more capacitance offset errors Δ (:, resistance offset error AR, and inductance offset error AL data. The joint point parameter (join point database) is corrected or updated by The wide IDMp junction point model begins. ^, Figure 10 - is a cross-cut of the IDMP junction point model, according to the embodiment. The junction point model 1100 comprises a metal wire view having a dimension d and a thickness t. The metal wire 11〇2 is connected with at least one element 11〇4 in the same layer in the element. The metal wire 1102 is spaced from the element 11G4 by a distance ——, and the element can be any component or joint point. And / or other circuit design can be a structure. _ metal wire 11G2 _ element 1 just between a coupling capacitor Cc. In addition to the same layer of the same layer of the material 1104, the metal wire 11 〇 2 is also in the wafer A layer of 1112. The connection layer 1112 can be any layer or a base plate in the circuit design. The grounding capacity cg is the result of the metal wire 11G2 being connected to the connection layer 1112. Referring to the IDMP connection point model, integration Design process includes And developed - 19 1297446 sets of functional sets that describe the design of t-differentiation AdMt and time offset error. The relationship between the two includes the use of a different shape in the circuit design to generate a time offset. Wrong . Difference Δτ (precursive shape time prediction procedure as described above), and using the time offset error Δτ to produce. The shape of the deviation (the deviation time shape prediction program as described above) and the like. The skewed shape of the joint point Μ/Δί includes the offset error Δ of the dimension d of the wire 1102 (1, and the offset s of the wire 11〇2 s. The difference is At. The assembly hypothesis of the integrated design process program The resulting fractal shape Δ is small relative to the actual dimension d/t of the wire, which is based on the _ perturbation theory. • The above function set is a linear function group (_丨4_ functions), It describes the relationship between the skew shape Δd/At and the resistance offset # ar (or called the progressive parasitic junction resistance) and the capacitance offset error ΔC (or the progressive parasitic junction capacitance (6). The total resistance value includes the coupling capacitor Capacitance and the grounding capacitor Cg, then C = Cc + Cg (Equation 1). The integrated design process program can be expressed as -At/t when describing the relationship of the skew shape resistance offset error ar. - Ad/d (Equation 2) f (5) Riji's integrated design process program can be expressed as AC/C ^ (Cc/C) when describing the relationship between the differential shape and the capacitance offset error _ (At/t) + (Cc/C)(Ad/2s) + (Cg/C)(Ad/d) (Equation 3), _ The above integrated design process procedure Correct these relationships to include one or more of the modulation factors or variables in them. These modulation factors can be expressed as K1, 〇, 〇, and verb 5, which can be changed by any disturbance. The wrong contact, and the additional capacitance added to the _combined capacitor (4). The modified relationship between the above-mentioned different shape and the resistance offset error AR (Equation 2) can be expressed as ΔR/ after considering the modulation factor. R bis-kl(At/t)-k2(Ad/d) (Equation 4) Simultaneously with the modified relationship between the above-mentioned skewed shape AdMt and the capacitance offset error (Equation 3), 20 1297446 after considering the modulation factor It can be expressed as AC/C ^ k3(Cc/C)(At/t) + k4(Cc/C)(Ad/2s) + k5(Cg/C)(Ad/d) (Equation 5).  Taking the capacitance offset error AC as an example, comparing the results of Equation 4 and Equation 5 in a circuit simulation (for example, generated by SPICE simulation), the capacitance offset error (normalized) and the metal wire size d can be obtained. The relationship between the perturbation M (expressed as a percentage of a dimension d) is a nearly linear relationship. Figure 12 is a normalized capacitance offset error AC 1210 corresponding to the joint point perturbation Δ (! 1220 in a graph of the percentage of a d dimension, according to an embodiment. Similarly, in a circuit simulation Comparing the results of Equation 4 and Equation 5, the relationship between the capacitance offset error aC (normalized) and the perturbation At of the metal wire size t (expressed as a percentage of a dimension t) is also approximately linear. Figure 12 is a graph of the known capacitance offset error AC 1310 corresponding to the percentage of the joint point perturbation 1320 in a t-size, according to an embodiment. The above program also describes the bias. The relationship between the different shape Ad/At and the time offset error Δτ. Using the same assumptions as above, and referring to Equations 1-5, the integrated design process describes the time offset error Δτ and the resistance offset error and capacitance offset. The relationship of the error AC, which can be expressed as 丨Δτ/τ ^ AR/R + AC/C (Equation 6).  Substituting Equation 4 and Equation 5 into Equation 6, we obtain AR/R + AC/C = [k3(Cc/C) - kl]( Δτ/τ) + k4(Cc/C)(M/2s + [k5(Cg/C) - k2](Ad/d) (Equation 7) Comparing the results of Equation 6 and Equation 7 in the -circuit simulation, the time offset error ^ can be obtained. And the relationship between the perturbation Δ of the metal wire size d (1 (expressed as the percentage of the dimension d) is also a nearly linear relationship. ' Figure 14 is a normalized time delay 1410 corresponding to the joint point perturbation Δ(1142〇 is a graph 1400 of a percentage of a d size, according to an embodiment, the above equation exemplifies, in one embodiment, the use of a program within a biasing process to describe a skewed shape, a skewed time , the relationship between the bias capacitor, the bias resistor, and the bias inductor. However, there are many different functions of the Shanghai, the 21 212974 high-order equation function, and the combination of many different functions can be in accordance with the disclosure of this specification. It is used in other embodiments. • Figure 15A, Figure 15B, Figure 15C is a connection point structure diagram after the partial parameter extraction • 15〇〇, according to an implementation The junction structure 1500 includes a metal power grid (spld) 1502 connected to a metal power supply line 15〇4 via two vias 1506. The power supply line 1504 has a a dimension d and a thickness dimension t. The power supply lead 15〇4 has a first adjacent structure 1510 and a second adjacent structure 152〇 in the same layer. The first structure 1510 has a size d1 and a thickness dimension t, and It is spaced apart from the power supply lead 15〇4 by a distance S1. The second structure 1520 has a size core and a thickness dimension t and is spaced apart from the power supply lead 1504 by a distance S2. Figure 15A shows the parametric parameter The previous joint structure 15〇〇A is taken. Before the partial parameter extraction procedure, the joint structure 1500A has about ten child nodes, or the changed region (this (10) area) 1530. Figure 15B shows the use bias The different shape information updates the joint structure 1500B after the joint shape. After the joint shape is updated by the shape information of the different shape, the joint structure 15 has about forty child nodes, or the area 153 is changed. : , i Figure 15 C shows the joint structure of an end point view 1 $ (8) ◦ (the joint structure of the point • 15 〇ΟΑ / 15 端点 end view), which has size parameters and correspondingly different shapes for The biased capacitance is used. According to the biased shape time prediction procedure in the specification, the partial capacitance can be obtained according to the following equations 8 and 9, • ^ = (ec/condition)^ + 0C/3sl) Asl + (5C /3dl)Adl + 0C/3s2)As2 + , (State Ship 2) Ad2 + (3C/3t)At (Equation 8) and △C = C(d + Ad,si + Asl, dl + Adl, s2 + As25 d2 + Ad2) - C(d5sl5dl3s2?d2) (Equation 9) · Equations 8 and 9 represent the implementation of a biased capacitor. Other variants, such as bias and bias inductors, can also be used. Gifts are taken; and not wei, such as higher-order equation functions, 22 1297446 and different combinations of functions can be carried out according to other descriptions in the specification. The above-mentioned joint structure of the joint structure 15〇〇, gg___ is used in the circuit design, when the shape information of the shape is formed by the integrated circuit, the processing efficiency meter is facing a new special number. Significant «, because of the redundancy of the typical department. > The number and the deviation of the message need to be completely reprocessed. The above-mentioned divergent process (including the H1 shape_program in the case of a different shape) utilizes the progressive process, which utilizes the design disk = = partial symmetry to re-characterize - integrated circuit design. The deviation process mentions: there is no need to generate new characteristic parameters, and there is no need to re-process it: 哪: Where also provides the bias information output 'The deviation process is reduced' in the program:: = library =: library === electricity _~ = degree, because it reduces (or eliminates) many of the checks that are usually required to be performed in the design process, which is not necessary for generations or After multiple parameters, the entire circuit is reprocessed so it can increase the efficiency, accuracy and accuracy of the integrated circuit design program. The aforementioned joint model shows that the biased shape for each node is allowed, her information, the links in the office One or more of the polarization capacitance △ and / or the polarization inductance of the point or the joint point area. The deviation information μ, AR shadow or AL also = enhanced nano frequency enh_d eha_rizatiGn pa_ (four) _ self-being ^ (four) _deh_terizati () np__). The number of hours of riding can be ton of capacitance, remainder, and/or electricity. The miscellaneous record can also be = △C^RML, read Yinglin corrected Lianchi's silk miscellaneous money, material secrets ^ New values for capacitance, resistance, and/or inductance. Di, inverse, and dot according to Figure 2 and Figure The skewed shape time prediction program 1〇2 or other integrated design wears the order of the secrets in the private order, and the Δ◦, △&, and/or AL are extracted from the different shapes corresponding to the joint points. Biased information. It will use the direct calculation of the procedural process (this (10) eaiculati such as the extraction process) or the extrapolation of the procedural process (4) as (4) said (10) from the genius (3) (8) to extract the eclipse AC 'AR, And 7 or AL, the following describes the extraction process, but not limited to this, other embodiments can also use other mining procedures to extract information. Direct juice calculation program to reduce or eliminate the integrated circuit manufacturing process In the case of the unit database, it is calculated by directly calculating the deviation parameter information ΔC/ARML and/or the deviation time ^ according to the different shape Δ_. By directly calculating the extraction program, the integrated design process The program forms _ « relationships or functional equations between the different shapes and at least one of the biased information Δ (:, from, and the domain & for example, in the skewed shape time prediction program ι〇2, according to Every lyrics is lion-like, and μ7, Directly calculate the biased 'AR' of each link ^, and / or ^. In another embodiment, the skewed shape time pre-procedure: the program can also query each by - or multiple lookup tables - The deviation information of the joint point ^, , and / or AL, wherein the joint table can directly calculate each joint point by the differential shape Δ sac according to each joint point, and the equation I-7 Bias information hr, and domain this. The key points in the library are secret, and the information about the deviation is Ac, ar, and / or 虬. Figure 16 is the - external _ _ _ 16GG, _ _ positive parameters, According to - real _. The recorded t / l money point repair value m ± push v to take the program 1600 in the function block _, the different shape fiber, and the exact & physical circuit ° and 50 layout description corresponding to the partial ^ ride. ^ The connection point of the male game, from the beginning of the census. △ _ ϋΓ ϋΓ ϋΓ 转 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏The county is connected to, and. The point of the point corresponds to the point of connection m Λ θ is not much _. It contains the inward of the design shape y ′′ 'sheng to $ to represent the sampling point deviation shape Adβ partial shape time prediction program translation. The contour 』 (5) drink. ♦ 麟成—Multiple points, discuss as one Figure 17 is a square connection of a polygon with a point Π00, according to the solid surface. The variant 24 1297446 time prediction program is modified by the original size (DC) of the interval or part of the original edge node 175G. The joint is polygonized (ie, the structure between endpoint A and endpoint b.) The correction uses the size offset error Μ (vector, and rs) to form a new joint 1 = size (Ad profile). /,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +pure, to correct the silk size d〇 of the first-interval_ to form a new size of the first-period phase, and then apply the second dimension in the second interval of the joint, wherein the skewed shape prediction program By increasing the - corresponding size offset error. To correct the original size DO' of the second interval (10) to form a new size D2 of the second interval (10). The polygon program acts on the third interval 17〇3 of the joint point, wherein the skew shape time prediction program corrects the original size d〇 of the third interval test by increasing the size offset error·3 Three intervals Π〇 3 - new size D3. The polygon program finally acts on the fourth interval of the joint point, wherein the skew shape time prediction program does not correct the original size of the fourth interval 17〇4 because its corresponding size offset error is zero. In the function block, it has completed the polygon program (returning to the program), and in function block 1612, the different shape time prediction program regains corresponding to one or more original joint points (non-polygon) And the original characteristic parameters (capacitance, resistance and / or inductance) of the junction database. The procedure for retrieving the original characteristic parameters includes, for example, using one or more view tables to retrieve the information, but other ways of retrieving information via the library or other sources may also be applied in other embodiments. In function block 1614, the different shape time prediction program retrieves the original characteristic parameters from the comparison of one or more original joint point intervals and the modified joint point interval, and then generates a mad parameter gambling In the joint point interval of the surface storage. The comparison program contains 'as shown by the needle seven, comparing the original joint point interval d〇 and the corresponding Μ contour interval size m. The different shape time prediction program uses the comparative information (ie, the difference in size (D0-D1) )) to extrapolate the correctness of the silk money (capacitance, resistance and / 25 1297446 or inductance). This correction parameter can be extrapolated or interpolated from the original capacitance, resistance and domain inductance but other embodiments Additional and/or alternative original link information may be utilized to obtain or extrapolate new parameters. • 纟 Function Block 1616, Job Shape Time Program Generation - Correct Link Point Data Library, which includes the use of the modified link Point parameter correction link point model data; Park connection point database information. Correct link point database can also include adding bias information to - or (4) circuit description pin. It can also contain _ contains new The data of △CMRML is used to replace one or more original circuit description files. The more than one positive connection point database can also contain the new value of the capacitance of the phase and the back connection point ^^ and/or electricity Sense, to replace the data of one or more circuit description files. Include the eccentricity _ 靡 峨 _ _ 卵 卵 卵 卵 卵 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The dependence of the library's error is made by using the information of the different shape to provide direct determination of the characteristic parameters of the characteristic parameters to achieve its purpose. In the design and manufacturing process, each segmentation point is replaced by the Liji Temple = calculation method. Extrapolation, the job and / or other design and manufacturing system can shoot the different function of the different function, and / or extrapolation procedures, because the system / ... file can use direct calculation bias Different information means to retrieve the information, instead of retrieving the information program in the way of viewing. Refer to Figure 1, 2, 3, 5, 丄 for 丄丄jcr to reduce the cry nu Γ 10 /, 'know these programs at least need In more than one process, the control is not limited to this. Generally, those skilled in the art can create the original syllabus x zhonglikou stone code, program logic array or 苴 in the flow chart and detailed description. He uses the invention According to these flowcharts, 'memory, which is also related to the processor, can be stored in non-volatile by physical connection or pre-programmed into the wafer, such as EEPROM, semiconductor j or any of the above requirements. Combination, but not limited to this. He 't-type: a process program, which contains programs that can be executed in the -EDA computer system or its system, etc. These programs can be implemented as code, but Stored in 26 1297446 machine readable or computer readable recording of the Wei domain or computer component processing system. Μ (4) Although there are many computer systems that can be used to use the integrated design process, Figure 18 • · The computer system 1 of the integrated design process program, according to the implementation - ^, Μ 糸 1800 1800 generally contains a central processing unit (CPU), or central processing unit 1802, to manage money and age... f龙流排面_合龙CPU(10)2 to AC H-volatile memory 1804 (for example, random access m_ (4) (1) to store the dynamic information from the secondary side and the instructional brain system t • ^ (4) optical storage element 1 dirty, _合_ _ Data storage row ⑽ Shu Wu and member 24 or the read-lean storage reservoir 1808 may include one or more erasable memory to demagnetization by an optical storage medium that is computer-readable. Various combinations of volatile memory, non-volatile hockey (10)6, and/or storage element (10)8 store the data structure describing each program in the integrated setup process, but the integrated design process is not Limited to being stored = within the above media. The computer system 18GG can also include at least one or more optical display elements 18ω. The user is connected to the busbar 18G1 to display information to the user of the computer system. The computer system Lion II can also contain one or more wire input components (8) 2, which are coupled to the busbar spring 180 For transmitting information and instructions selected to the CPU 18〇2. Alternatively, the computer system surface can include an optical cursor control or pointing component 1814 that is coupled to the busbar to communicate information and commands selected by the user to the CPU 1802. The computer system can also contain two. One or more optical signal conversion elements 1816 (e.g., transmitters, receivers, modems, etc.) are coupled to busbars 1801 to provide a communication interface with other computer systems. The system and method for manufacturing an integrated circuit as described in the specification includes a method of utilizing one or more functional deviation parameters and a circuit design of at least „_size offset error of the connection point, corresponding to at least- A method of directly generating a progressively different parameter, wherein the biased parameter includes one or more differences in the number of tables in the electronic parameter capable of characterizing the joint. " 27 ^97446 The system and method for fabricating an integrated circuit includes a method for utilizing a size offset error of a joint point and one or more circuit corrections for characterizing pre-mosquito information of the electronic parameters of the joint point The method for directly generating a tired and progressive parameter corresponding to at least one joint point, wherein the bias parameter includes one or more difference information of each parameter in the electronic parameter capable of characterizing the link and the point. The system and method for manufacturing an integrated circuit as described in the present specification includes a method of utilizing, fixing, or modulating a parameter and the component A circuit of size offset error = a method of directly generating a progressively different parameter corresponding to at least one component, wherein the bias parameter comprises one or more electronic parameters capable of characterizing the component, each parameter Differences tft 〇^ The system and method for manufacturing integrated circuits described in this specification includes a method that utilizes the dimensional offset error of a 7L piece and one or more electronic parameters that characterize the element. In the circuit design of the information of the first domain, the method of directly generating the progressive divisor is corresponding to at least one component. The bias parameter includes one or a number of electrons capable of characterizing the component, each of which Difference information of parameters. The system and method for manufacturing an integrated circuit described in the present specification, j includes a method including a plurality of components and a plurality of components, and a difference in size in the line to pre-line a progressive bias parameter and a progressive time difference of at least one of the designs, wherein the bias parameter includes one or more capable of characterizing at least one component and a link Number of revolutions = difference information; and integration of at least one line design towel size difference, progressive bias parameter, and 2 and * progressive time difference, modify the line design. 'The above method includes at least - size difference, progressive bias Different parameters, as well as the difference in progressive time, to produce a model of the circuit design. * The above method further includes at least a size difference, a progressive differentiation parameter 'and a difference between the progressive %, to enhance the model of at least one component and the connection point. The above method further includes adding at least one size difference, a progressive deviation parameter, and a progressive time difference to one or more line descriptions, wherein the line description has at least two 28 1297446 image data representations, and A text slot representation. The above method further includes utilizing information including at least one size difference, progressive differentiation parameter, and progressive time difference to discard the relevant information portion of one or more line descriptions. - The above method further includes re-characterizing at least one component and the junction using at least one dimensional difference, progressive differentiation parameter, and progressive_time difference. The prediction method in the above method further includes utilizing the size difference, and the progressive differentiation parameter is extracted from at least one component and the connection point. This culling method involves matching the size difference to the line design. The culling method further comprises at least one or more of _- or more functional relationships between the size difference and the 35-parameters; and the straight-forward size difference and the functional relationship generate the bias parameter. The progressive bias parameter in the above method includes a progressive difference in circuit parameters that can characterize at least one component, a joint point, and one or more joint point intervals. The circuit parameters in the above method include at least one resistor, inductor, and capacitor. , junction capacitance, gate-source capacitance, gate-drain capacitance, source-base capacitance, gate base capacitance, drain-base capacitance, and effective gate length. The difference in the dimension size includes at least the difference in the use of the progressive time difference and the gap delay time between 70 pieces and the joint point to determine the gap delay time. This method further includes the gap time delay of the profit distribution to generate fresh The forward bias parameter corresponds to at least one component and the joint point. The circuit design correction in the above method further comprises using the predicted progressive skew parameter to generate the size difference rule. /, the progressive time difference includes the signal transmission delay of the circuit. The above method further includes obtaining the difference in size by shape verification analysis of a circuit. Integrating at least one size difference , the method of squeezing different parameters, and the difference between the scales includes a circuit description of at least one size wire, a deviation difference, and a scale difference thief to an entity. The entity description is at least one image data. And a text file. The system and method for manufacturing an integrated circuit as described in the present specification includes a method comprising: 29 1297446 at least one circuit design for receiving a plurality of components and a connection point; receiving corresponding to the component and the connection size Differences; · The ruler nucleus takes the component and the progressive bias parameter in the joint point, wherein the heterozygosm contains - or more can characterize at least one or more components • • and the difference of the joint points Wei: Xiang at least - A size difference money deviation parameter to produce this. The difference between the scales of the design; and the different parameters of the design that should be designed in the present specification. The system and method for manufacturing integrated circuits described in this specification include an integrated design method. One or more circuit devices that receive a plurality of components and connection points are used to achieve a progressive correction of the component model and the joint point model by using the dimension offset error of the component and the joint point, and the model is modeled using the modified component and the joint point model. The integrated circuit is generated by using the model; the time offset error information of the circuit is generated by using the model; the offset error of the component and the joint is generated by using the time offset error information; and the offset error of the component and the joint is utilized to generate Dimension offset error rules for components and joints. The system and method for manufacturing an integrated circuit described in the present specification includes an integrated design manufacturing method including at least one circuit design for receiving a plurality of components and a joint point; using the enhanced component and the joint model, and simultaneously The pottery design produces a circuit model in which the enhanced component and joint model integrates at least one capacitive offset error, resistance offset error, and component offset error from the component and the joint point. And an inductance offset error; generating a time offset error information by using the circuit model; and using the time offset error information to generate a rule that can control a size error of the component and the joint point, wherein the rule integrates at least one or more The capacitance offset error from the time offset error information of the circuit model.  Difference, resistance offset error, and inductance offset error. The system and method for manufacturing an integrated circuit described in the present specification includes a system including at least one means for electronically processing; and means for storing information electronically; receiving a circuit including a plurality of components and connection points Means of designing a means for predicting progressively different parameters and progressive time differences of at least one circuit design using dimensional differences in corresponding circuit designs, wherein the biasing parameters include one or more parameters that can characterize at least one of 1 1 297 446 The above components are connected and connected. Point, the difference between the progressive time and the circuit design size difference segment; and · Integrate the size difference of at least one circuit design, the progressive difference parameter, and the time difference to correct the circuit design. The above system further includes _ at least a size difference, a progressive bias parameter, and a progressive time difference to produce a model of the circuit design. The above system further includes at least a difference in size, a g-adjustment parameter, and a difference in progressive time to enhance at least the information of the paper and the model of the joint. The above system further comprises at least one size difference, a progressive deviation parameter, and a progressive time difference item or a deducted line financial statement segment, the line job description has at least one image data representation, and A text file indicates. The system described above further includes means for re-characterizing at least one component and joining points using at least one dimensional difference, progressive biasing parameter, and progressive time difference. The above-described means for predicting the system further includes a means of extracting the progressively different parameters using the size difference. The progressive bias parameter in the above method includes a progressive difference in circuit parameters that can characterize at least one component, a joint point, and one or more joint point intervals.电路 The circuit parameters in the above method include at least one resistor, inductor, capacitor, gate _ source pole valley gate and pole valley, source-base plate valley, gate base capacitor, and drain _ base plate capacitance. The predictive size difference system in the above method further includes at least one means for determining the gap delay time by using the difference between the progressive time and the gap delay time between the component and the joint. The means further includes utilizing the gap time delay of the separation to produce means for the progressive bias parameter to correspond to at least one of the elements and the joint. The means of modifying the system further includes means for utilizing the predicted progressive bias parameters to generate rules for the size difference. The circuit design corrections in the above system further include means for utilizing the predicted progressive skew parameter to generate the size difference rule. The above system further includes means for obtaining the difference in size from the shape verification analysis of a circuit. 31 1297446 The revised secret segment further includes a circuit description corresponding to at least one dimensional difference, a differential parameter, and a progressive time difference to an entity (10) and a method, including an element, Include at least one or more means for receiving a plurality of components and a connection circuit design; utilizing a corresponding size difference in the circuit design to compensate for at least one of the progressive differentiation values of the circuit and the means for the difference in the progressive time, wherein The biased operand contains one or more differences information that can characterize at least one or more components and joint points; a means to predict the difference in size of the circuit design; and at least one of the integrated circuits Dimensional differences, progressive deviation parameters, and progressive time differences to correct the circuit design. ', '' The manufacturing integrated circuit (4) described in this specification 'system and method, including - machine reading medium' contains The executable age can be recorded in an L-line, and the content includes the reception of a plurality of components and the connection of the scale design, and the size of the silk road design. At least - (iv) a pre-equivalent parameter and a difference between the repetitive circuits in the design of the remuneration circuit, wherein the disparity parameter includes difference information of one or more parameters, which can characterize at least one or more components and joint points, and utilize the progressive It is difficult to distinguish the size difference of the line design, and at least one size difference, progressive deviation parameter, and time-testing wire in the domain_integrated circuit design to correct the circuit design. The system for manufacturing the integrated circuit described in the specification sheet and The method comprises a __method comprising at least one or more Wei-containing complex elements and a connection 阙 circuit layout; receiving corresponding components and a size difference of the continuation; a size wire, which is progressively derived from at least the 侃 and the connection points The deviation I number 'the towel's bias parameter contains __ or more of the parameters of the difference 'the characterization of at least more than one; ^ and the joint point; and at least one or more dimensional differences and partial Different parameters, the difference between the components on the _ at least _ and the joint point. The above method further includes at least one size difference, progressive differentiation parameter, and tired The time difference is used to generate a model of the circuit design. The progressive-derivative parameters of the embodiment include the size difference corresponding to the circuit layout. The above method further includes using at least „dimension difference, progressive differentiation parameter, and progressive 32 1297446 Time difference 'to enhance the information of at least the components and the model of the connection point. .  The above method further comprises adding at least one size difference, a progressive deviation parameter, and a progressive time difference to one or more line descriptions, wherein the line description has at least one. - Image data representation, as well as a text file representation. The above method further includes updating the relevant information portion of the one or more circuit description standards by using information including at least one dimensional difference, progressive differentiation parameter, and progressive time difference. The above method further includes at least one size difference, a progressive neck number, and a progressive φ time difference to re-characterize at least one component and the joint point.取取-实关中纽偏异参_方方包:; in the size difference to correct the bias parameter 'form-one or more functional associations, and / or use the functional relationship directly from the size difference Generate bias parameters. - The progressive differentiation parameter of the connection point in the embodiment includes a line parameter (four) difference, which is characterized by at least one or more of the connection points and the interval of one or more of the connection points. The parameter of an embodiment includes at least one capacitor, resistor, and inductor. - The above method further includes using the difference in progressive time to determine the delay time and/or the delay time of the split and the link. The method further includes the separation of the gap time delay, so as to generate the progressive deviation parameter corresponding to the at least one component and the joint point. The method further includes utilizing the separate gap time delay to generate the progressive skew parameter to correspond to at least one of the joint points. The method further includes utilizing the generated progressive bias parameter to generate a rule that controls the size difference. The system and method for manufacturing a surface circuit described in the specification, including a method for receiving - a circuit design including a plurality of components and a connection point; and a financial difference design road towel integrating at least one or more components and a connection point; The ruler finger takes at least one or more components and the linked progressive differentiation parameter, and the deviation parameter includes the difference between the one or more electronic parameters capable of characterizing at least one component and the connection point; And using the progressive bias parameter information to achieve time analysis, while generating a progressive time difference. 33 1297446 Time result of the difference in progressive time. The difference in size and the progressively different parameters to produce a method as described above further includes generating a model comprising the above method and more than utilizing at least the circuit for use. - The difference between the bursts of the embodiment towel includes the signal transfer delay of the circuit towel. The above method further includes the *-f road heterogeneous analysis analysis of the size difference of the silk. The integration in the embodiment - the size difference in the embodiment includes the difference in the size corresponding to the physical description of the circuit - the embodiment of the actual description is at least - like the upper image (four) face word slot case. ‘, clothing The above method also includes at least one company's dimensional error, bias parameters, and time difference, to at least one of the social components to retract the information. The piece of flight model information contains additional one or more dimensional differences, deviation parameters, and time difference to one or one circuit description lion. The enhanced component model information includes the use of at least one or more dimensional differences, bias parameters, and time difference information to replace the information in the original circuit description job. Enhancing the joint model information involves re-characterizing the joint using at least one dimension and time difference. : i The singularity of the f-flap is included in the sizing parameters of the sizing. • Forms one or more functional relationships, and/or determines the difference between the parameters, which can take advantage of the functionality. Relationships, directly utilizing dimensional differences to re-characterize at least one component and joint. • Taking the progressive bias parameter in an embodiment further includes confirming one or more parameters capable of characterizing at least one of the elements and the joint; and/or utilizing one or more interpolations and determining the parameters after 5 The component and the skew parameter of the joint are formed, wherein the number of strands after the confirmation can characterize at least one of the components and the joint. The progressive differentiation parameter of the connection point in an embodiment includes a progressive difference in line parameters that characterizes at least one or more of the joint points and one or more intervals of each joint point. The electronic parameters in an embodiment comprise at least one of a capacitor, a resistor, and an inductor. 34 1297446 + One piece of electronic 4 packs to more than 4_s of gate/source capacitance, gate 4 and pole valley, source-base capacitor, gate-base capacitor, and pad Edition capacitor. • This _ book towel describes the manufacture of miscellaneous electricity _ secret and green, including - integrated design system · · = ·, party I contains at least one or more of the circuit components that contain multiple components and connection points The size is shifted by m ' to achieve the progressive correction of the component model; the size offset of the joint point is used as the difference to achieve the progressive correction of the joint model, and the modified component and the joint model are used to generate the model of the integrated circuit. The model transmits delay information; and uses the signal to convey delay information to verify the shape of the model. • σ The above method further includes dividing the component and the gap delay time between the connection points, wherein the signal transmission delay information includes the component slot delay time; using the segmented gap delay time to generate the component offset error; using the segmentation gap delay The time generates a joint offset error; and/or uses a component offset error and a joint offset error to generate a rule that can control the size offset error of the component and the joint. - The component offset error of the actual wipe contains at least a progressive size difference and a progressive difference in the circuit parameters, wherein these differences can characterize each component. The joint offset error in the example includes a progressive size error. The point depends on the parameters of the Wei-containing circuit (4), and its energy characteristics are less than one point on the connection point and one or more connection points. The junction offset error may also include at least one of a capacitance offset error, a resistance offset error, and an inductance offset error. The system and method for manufacturing an integrated circuit as described in the specification, including a system having at least one means for processing electronically; and means for storing information by electronic means, receiving-including components and links Point means of circuit design layout; receiving means corresponding to the 7C piece and the connection size difference; the means for obtaining the at least one of the 7 pieces and the progressive deviation parameter of the connection point by the difference in the size, wherein the deviation parameter A difference information containing one or more parameters, which is less confusing - more than one component money connection point; and a prediction of at least one component and a progressive time difference of the joint point, which utilizes at least one or more dimensional differences and deviations parameter. 35 1297446 The system described above further includes means for generating a model of a circuit design using at least one dimensional difference, progressive bias parameter, and % difference. The system described above further includes means for matching the size difference to the circuit layout. The system described above further includes means for enhancing the information of at least one component and the model of the connection point by using at least one size difference, a progressively different number of tables, and a difference between & ', the above system further includes adding at least one dimension difference, the accumulated time difference to one or more line description segments/introversion parameters, and the progressive system further includes at least one dimensional difference, the progressive time difference Information, to update a different, number and part of the means. * Update one or more circuits to describe the relevant information in the slot case. Gate = it! 1 It also includes the use of at least one size difference, progressive differentiation parameter, and progressive time difference, and at least one component and the continuous time period. Or eight to say: use the difference between the progressive ridges to determine the gap delay time, and / Gou. 1] means for 7G parts and gap delay between connection and force points. The _= system further includes the separation of the gaps, which is the means by which the progressive line deviation parameter corresponds to at least one component and the joint point. : It is also a means of generating (four) different records to produce rules that control differences. The system and method for manufacturing an integrated circuit described in the present specification includes H, a device having a T-including a circuit arrangement of a plurality of elements and a connection point, and a connection (4). ':' occupies the difference in size of the hand & shed size wire ' Φ at least - a component and the means of extracting progressively different parameters in the joint point 'where the bias parameter contains - or more of the difference between the parameters 'The means of at least the above-mentioned components and joint points; and at least one of the nucleus and the deviation parameter's at least one element and at least one element and the difference in the progressive time of the joint point. The means of the exemplification-embodiment further comprises at least one or more means for forming one or more functional relationships between the size difference and the number of the different parameters 36 1297446; and directly utilizing the size difference and the functional relationship to generate the The means of biasing parameters. ‘The above devices further include means for generating a model of a circuit design using at least one dimensional difference, progressive bias parameter, and progressive time difference. • The above devices also include means for matching the size difference to the circuit layout. The apparatus described above further includes means for enhancing the information of at least one component and the model of the connection point using at least one dimensional difference, progressively different parameter, and progressive time difference'. The system and method for manufacturing an integrated circuit described in this specification includes a machine readable medium containing executable instructions that can be executed by a processing system, the content of which includes receiving a plurality of components and a circuit design of the connection points. Receiving a difference in size of the corresponding component and the joint point, using the difference in size 'from the at least one component and the joint point to extract a progressive deviation parameter, wherein the deviation parameter includes information on the difference of one or more parameters, which can be characterized At least one or more elements and junction points, and/or predictions of at least one of the elements and the difference in the time of the junction, utilizing at least one of the dimensional differences and the skew parameters. The system and method for manufacturing an integrated circuit described in this specification can be utilized with various types of force. The midnight circuit is in the process of 'containing programmable logic components (PLDS)) such as field programmable gate arrays (FPGAs), programmable array logic ((4) Inhibition of this array (array (pal)) components, electronic 叮, flat-range logic and brother memory components and standard cell-based devices, such as special application integrated circuits (ASIC). Other methods and methods that can be used to implement the integrated circuit include: a microprocessor with memory, such as an EEPROM, embedded micro.  Processor, firmware, software, etc. Alternatively, the system and method for fabricating an integrated circuit can be implemented in a U-processor having a software library circuit simulation, discrete logic, system components, neural logic, quantum components, and a mixed mode of the above-described cells. In addition, basic component fabrication techniques can be used to provide a number of implementation options, such as metal oxide semiconductor field effect transistor (MOSFET) technology, such as complementary to oxide semiconductor (CMOS), dual carrier technology, such as shots. Polar | Mahe logic, polymer technology 37 1297446 (such as dioxide dioxide common polymer and metal amalgam metal structure, etc.), as well as mixed analog digital technology and so on. - The towel should be noted that, in the system and the method towel, the components contained in it can be used as electrical information-assisted design tools, and are expressed as information of various tangible media or instructions. Models, register transfers, logic components, transistors, layout shapes, and/or other special materials, which are included in the actual format and objects but do not implicitly support the behavioral language, such as C awu, Venlog, And HLDL; supports the format of the scratchpad hierarchy description language, such as RTL, and formats that support the shape description language, such as (5) guilt, (5) view, coffee ιν, Φ CIF, MEBES, and any other styles and languages. The computer readable medium of various data and/or instructions may include, but is not limited to, various non-volatile media, such as optical, magnetic or semiconductor storage, and may be wireless, optical or optically transmitted "age and its mixed square wire". A carrier that transmits secret footwear and/or instructions. For example, a, the new arrival of this secret ^ chemical / send (upload, download, email, etc.) and or other computer network through a or = such as HTTP 'FTP, SMTP, etc.). When a computer system transmits electricity through the second == (4) f message, the above-mentioned various data and/or instructions can be = n skewed - the processing entity (10) such as - or more (four) Turn (4) power is difficult, it includes the limit 2 knot program and its _ strip. The "style" layout of the nucleus is in addition to the face, the domain is defeated, the "include", the package - is an open statement, and the fine statement; meaning "including two." 'f' refers to two or more related items, which means any related project, combined with all related projects. The embodiments of the system and method of the system are not intended to limit or otherwise limit the system (4) and the square and the core of the integrated circuit are merely illustrative of the system and the circuit, rather than limiting the manufacturing product. The genus and branches of the body. The above embodiments are modified and changed in the case of the technical principle and spirit of the system and method of the road. Therefore, the scope of protection of the system and method for manufacturing an integrated circuit should be as set forth in the application patents described later. The various items disclosed above and the manner of actuation can be combined into other embodiments. Some of the changes in the systems and methods for fabricating integrated circuits can be accomplished in accordance with the description of the details. The following patent application scope should not be construed as limiting the systems and methods for making integrated circuits in the disclosures disclosed in the specification, but rather should be construed as including the stipulations of all of the fabricated circuit circuits. The following items are determined by the scope of the invention, and are not intended to limit the scope of the system and method of manufacturing the integrated circuit disclosed herein. The scope of the system and method for manufacturing an integrated circuit is disclosed in the following claims. Thinking, for example, when a point in the system is interpreted to be implemented by a machine readable medium, other points of view are also interpreted as being implemented by a chicken readable medium. [Simple diagram of the diagram] Figure A is the block diagram of the Integrated Design_Manufactoing Process 'IDMP, which contains a biased turn, which contains a pre-shaped tear of 4 1G2 ' and / Or the biased time shape prediction program just, according to the embodiment. Figure B is a block diagram of an i-blade leafless process sequence, including a biasing process, which is used in the fabrication of integrated circuits, in accordance with an embodiment. 〃 Figure - Another block diagram of an integrated design process that includes a biasing process that is used to fabricate integrated circuit pads, according to another embodiment. Figure 3 is a departure time prediction process (InTime processes), according to an embodiment. Figure 4 is a block diagram of the skewed (four) inter-test procedure, which takes care of the bias signal to correspond to the connection architecture, according to an embodiment. Figure 5 is a flow chart of the skewed time profile prediction program (InTentP_sses), according to an embodiment. 39 1297446 and the embodiment of Fig. 5 is an electro-crystal according to the component model of the enhanced integrated design process. Figure 8 is a gate/junction capacitor block of a component model of an integrated design process program, according to an embodiment. " Figure 9 illustrates - modified transistor element model parameters, according to an embodiment.

Figure j * Block diagram of the full-scale 3 and 50 process, which contains the partial shape 睥μ-order 'for application in the integrated circuit process, the root broadcast ®- ^ according to Figure 2, the block diagram, the root Fig., Root diagram: A graph of the signal delay of the electro-gambling type of the A-system-integrated design process program corresponding to the closed-off offset error, according to an embodiment. Figure 10B is a graph of saturation current versus free polarity offset error for a transistor model of an integrated design process, according to an embodiment. Figure 10 - Cross-sectional view of the connected-integrated design process, the example. Fig. 12 is a diagram of the normalized capacitance offset error of the joint point model of the integrated design process program. Corresponding to the graph of the percentage of the connection perturbation Ad in one d dimension, an embodiment of the root pants.

Figure 13 is a graph of normalized capacitance offset error for a joint point model of an integrated design process program, corresponding to a perturbation Δί, a percentage of a t-size, according to an embodiment. Figure 14 is a graph of the normalized time delay corresponding to the joint model of an integrated design process program. The graph of the percentage of the connected perturbation Ad in one d dimension, according to an embodiment. Figure 15A, Figure 15B, Figure 15C is a connection point structure diagram after the partial parameter extraction, according to an embodiment. Figure 16 is an extrapolated program flow chart, used The modified parameter of the modified joint point is obtained according to the embodiment. Figure 17 is a block diagram of a polygon joint point according to an embodiment. Figure 18 is a schematic diagram of a computer system for controlling the integrated design process program. According to an embodiment. 1297446 In the figure, the same figure number represents the same or substantially the same object or clearly identifies the unseen or action of each—when the object appears first time, its figure A mark will be attached. (For example, object 1〇2 means it is discussed and explained for the first time in Figure 1.) [Main component symbol description] ', 1210 normalized capacitance offset error 1220 joint point perturbation Δ (1 1310 Normalized capacitance offset error 1320 joint point perturbation At

1410 normalized time delay 1420 joint point perturbation Ad 10 circuit design program 100B integrated design process program block diagram 100A integrated design process program 101 different process 1010 signal delay 1012 saturation current 102 skew shape time prediction program 1021 partial Different shape time prediction Xupi 1020 gate length offset error 104 skew time shape prediction program 1100 joint point model 1102 metal wire 1104 element 1112 connection layer 12 circuit layout program 1200 graph 122 function block 123 function block 124 function block 41 1297446 125 Function Block 1300 Curve Figure 14 Time Analysis Program 1400 Curve Figure 142 Function Block 143 Function Block 144 Function Block 145 Function Block 15 Design Flow 1500C Joint Point Structure 1500B Joint Point Structure 1500A Joint Point Structure 1502 Metal Power Grid 1504 Metal Power Supply Wire 1506 through hole 1510 first adjacent structure 1520 second adjacent structure; 1530 change area 1600 extrapolation program flow chart 1610 function block 1614 function block 1616 function block 1700 polygon connection point block diagram 1701 first interval 1702 second interval 1703 third 1704 1750 between the fourth portion of the original non-polygonal section of the connection point 1800 of the integrated control program design process computer systems 421,297,446

1801 Bus 1802 Central Processing Unit 1804 Volatile Memory 1806 Non-volatile Memory 1808 Optical Storage Element 1814 Pointing Element 1816 Optical Signal Conversion Element 20 Shape Validation 200 Integrated Design Process 22 Resolution Enhancement Technical Program 24 Process Procedure 25 Manufacturing Process 402 Database Replacement Format/Design Replacement Format File 404 Technical File 406 Standard Parasitic Delay Format File 408 △ d File 410 Deviation Parameter 412 Updated SPEF File 600 Integrated Design Process Program 602 Circuit Design 604 Layout 606 Physical Circuit Description 608 Original Unit Database 610 Original Link Database 612 Generate Electronic Circuit Model 614 Delay Calculation 616 Dynamic Time Analysis ^ 618 GDSII 620 RET 43 1297446 622 Correction GDSII 624 Fabrication 626 Wafer Development 700 Transistor 702 Junction End 704 Endpoint 710 Gate 802 Base 804 Source Region 806 > and Polar Region 808 Depletion Region 810 Gate 900 Component Model Parameters

Claims (1)

Scope of application, patent application: Patent Application No. 94101967, Patent Application Revision 96.10.26. 1. A method for characterizing circuit design using characterization parameter deviation information corresponding to circuit design, comprising the following steps: a circuit design comprising a plurality of cells and an interconnect structure; determining a biased geometrical information for the circuit design; using the biased geometrical tribute of the decision to design a difference in nose progression time for the circuit; and estimating the defensive budget for a time The difference in progressive time is used to determine the gap time in the circuit design; and the gap time rule is generated for the circuit design based on the gap time of the decision. 2. The method of claim 1, further comprising dividing the calculated progressive time between the plurality of cells separating the circuit design from the junction. 3. The method of claim 2, further comprising configuring the time budget between the plurality of cells of the circuit design and the junction. 4. The method of claim 3, wherein configuring the time budget includes configuring information about differences in 1C characterization parameters. 5. The method of claim 2, further comprising separating the gap time indicated by the difference in the time of progression between the plurality of cells and the junction. 6. The method of claim 5, further comprising generating a time-varying database comprising the plurality of cells separated from the link 1295446 10 15 The maximum and minimum time variation of the separation associated with the gap time of the point. 7. The method of claim 6, further comprising deriving the bias information from the time variation corresponding to a cell to the cell. 8. The method of claim 1, wherein the step of estimating the difference in progressive time comprises generating a maximum/minimum time variation database of one of the progressive time differences, and a time variation from each of the plurality of connected points Produce biased characterization information for a cell. 9. The method of claim 1, wherein the method further comprises generating a return in the circuit design that is a source of disparity in the budget for the time. 10. The method of claim 1, wherein the generating a dimension difference rule for the circuit design comprises performing a shape bias budget based on the skew geometry information and the time budget. 11. The method of claim 1, further comprising generating a biased budget allocation for one of the cells or junctions corresponding to the circuit design. 12. The method of claim 1, wherein the biased geometric information comprises at least one of length, width, and thickness variation information associated with the component of the circuit design. 13. A computer program product comprising a computer usable medium carrying computer code for causing a computer device to characterize the circuit design using a bias information corresponding to a characteristic parameter of a circuit design, the characterization The action comprises: receiving a circuit design, comprising a plurality of cells and a joint point; determining a biased geometric information of the circuit design; calculating the circuit design by using the determined geometric information of the decision 46 20 12 9^744, Π i:w 10 15 The difference in the time of the entry; and the difference in the progressive time against the estimated time budget to determine the gap time in the circuit design; and the size difference rule for the circuit design based on the determined gap time. 14. The computer program product of claim 13 further comprising a difference in the progressive time between the plurality of cells separating the circuit design and the joint. 15. The computer program product of claim 14, further comprising configuring the time budget between the plurality of cells of the circuit design and the junction. 16. If the computer program product of claim 15 is applied, the time budget is configured to include information on the difference between the 1C characterization parameters. The computer program product of claim 14, further comprising dividing the gap time between the plurality of cells and the joint point by the difference in the progressive time. 18. The computer program product of claim 17, further comprising generating a time variation database comprising maximum and minimum time variations associated with the gap time of the division of the cells and the junction. 19. The computer program product of claim 18, further comprising the derivative information derived from the time variation corresponding to a cell. 2 (λ) The computer program product of claim 13 of the patent scope, wherein the estimated time difference includes a maximum/minimum time variation database that produces a difference in progressive time, and a time from each of the plurality of connected points Change 47 20 1297 [446I year month r, ¥ replace page difference to generate a singular characterization information. 21. The computer program product of claim 13 of the patent scope, which further includes the generation of defiance in the circuit design One of the time budgets differs from the source's return. 10 15 22. The computer program product of claim 13 wherein the method for generating a dimension difference for the circuit design comprises performing a shape gap budget based on the bias geometry information and the time budget. 23. The computer program product of claim 13, further comprising generating a biased budget allocation corresponding to one of the cells or junctions of the circuit design. 24) The computer program product of claim 13, wherein the biased geometric information includes at least one of length, width, and thickness variation information associated with the component of the circuit design. 25. A computer system for characterizing a circuit design using a bias information corresponding to a characteristic parameter of a circuit design, comprising: a processor; and communication coupled to a memory of the processor, wherein the processor The memory is configured to perform the following operations: receiving a circuit design comprising a plurality of cells and an interconnect structure; determining a biased geometrical information of the circuit design; calculating the circuit design using the determined geometric information of the decision The difference in progressive time; and the difference in the progressive time estimated to defy the one-time budget to determine the gap time in the circuit design; and 48 20 1 if- Η The size difference rule for this circuit design is generated based on the gap time of this decision. 26. The computer system of claim 25, further comprising separating the calculated progressive time difference between the plurality of cells of the circuit design and the junction. 27. The computer system of claim 26, further comprising configuring the time budget between the plurality of cells of the circuit design and the junction. 10 15 28. The computer system of claim 27, wherein configuring the time budget includes configuring information about differences in 1C characterization parameters. 29. The computer system of claim 26, further comprising separating the gap time between the plurality of cells and the junction point by the difference in the progressive time. 30. The computer system of claim 29, further comprising generating a time-variant database comprising maximum and minimum time variabilities associated with the gap time for the plurality of cells and the separation point of the joints . 31. The computer system of claim 30, further comprising a biased information derived from a time variation corresponding to a cell. 32. The computer system of claim 25, wherein the estimated time difference comprises a maximum/minimum time variation database that produces a difference in progressive time and a time variation from each of the plurality of interconnect structures A characteristic characterization of a cell. 33. The computer system of claim 25, further comprising a 49 20 L, ~, > tJiW, !-, '-Ί generating a source of variation in the circuit design that is defying the time budget |,Μ,Ι(„* - · ♦ I报. 34. The computer system of claim 25, wherein the size difference rule for generating the circuit design includes executing the shape according to the bias geometry information and the time budget The gap budget. 5 35. The computer system of claim 25, further comprising generating a biased budget allocation corresponding to one of the cells or the connection points of the circuit design. 36. A computer system wherein the biased geometric information includes at least one of length, width, and thickness 10 variability information associated with the component of the circuit design. 37. Using a singularity parameter corresponding to a circuit design A system for characterizing a circuit design, comprising: means for receiving a circuit design comprising a plurality of cells and an interconnect structure; 15 for determining a skew geometry of the circuit design Means for calculating a progressive time difference of the circuit design using the biased geometric information of the determination; and means for determining a gap time in the circuit design for estimating the difference in the time difference against the budget of one time; 20 means for generating a dimensional difference rule for the circuit design based on the determined gap time.