200811704 / 九、發明說明： ^ 【發明所屬之技術領域】 本發明係有關全加器電路設計之技術，特別是在低電 晶體數量條件下所設計具有高速低能耗、低操作電壓與高 驅動能力之全加器電路。 【先前技術】 一般來說，全加器在設計架構上都是以卡諾圖 • (Karnaugh Map)化簡，並以所得化簡結果直接設計全加 器；然而’此種設計方式在電晶體數量下降到最低限度1〇 個電晶體（10 Transistors ; 10T)時，其電路的輸出訊號電壓 將會有所衰減，尤其應用在多位元串接的加法器時，此一 衰減現象將會顯得十分重要。這是因為在串接的應用上， 訊號在最差的情況之下可能必須從最低位元一直傳遞到 最高位元，因此，較差的訊號驅動能力將會大幅的影響到 整個電路速度上的效能，及更多功率的消耗。 籲 一般造成輸出電位的衰減是由於在電路結構上為了 降低電晶體數量(transistor-count)，而使用傳輸電晶體邏輯 (Pass Transistor Logic)的方式實現電路架構，因此造成在 某些特定的狀況之下會有輸出電壓準位衰減，稱為臨界電 壓衰退問題(threshold loss problem)。以N型金氧半導體 (NM0S)來說，在NM0S電晶體打開的情況之下傳遞高電 位的訊號，其輸出訊號將會衰減一個Vtn的電壓值 (Vdd-Vtn)，其中 Vtn是 NM0S 的臨界電壓 5 200811704 (NMOS-Threshold Voltage)(在 0.35um 製程考慮基體效益 . 的情況下典型值為〇·6〜0.8V)，意即輸出電位並不為操作 電壓’而是比操作電壓低一個Vtn的電壓值。同樣的問題 亦發生在P型金氧半導體(PMOS)，當PMOS在傳遞低電 位的時候輸出訊號會比低電位高出一個Vtp的電壓值，其 中 Vtp 是 PMOS 的臨界電壓（PMOS-Threshold Voltage)(在 〇·35腿製程考慮基體效益的情況下典型值為 -0·7〜_0·95ν)，意即輸出電位並不為操作電壓，而是比操 # 作電壓高一個Vtp的電壓值。要解決這個問題一般都是在 電路結構裡面加上反相器提供互補的控制信號，並同時使 用PMOS和NMOS傳遞訊號，即所謂的傳輸閘架構 (transmission gate)。例如[A· Shams and M· Bayoumi，“A Novel High-Performance COMS l_Bit Full-Adder Cell” IEEE Trans. Circuits and Systems-II, Vol.47 No.5, May 2000·][ N· Zhuang and H· Wu，“A New design of the CMOS full adder，” IEEE J· of Solid state circuits, Vol· 27, No. 5, _ ρρ·84〇-844, May 1992·]。不過此伴隨而來的是整體電路電 晶體數量和晶圓面積（silicon area)的上升，以及功率消耗的 增加。 此外，當電路結構是以MOS作為開關元件時，以此 開關作串接的應用會有訊號傳遞延遲的問題，在沒有將串 接的開關使用缓衝器或反向器（buffer or inverter)作分割補 償的情形之下，訊號傳遞的速度和串接的級數(N)約呈平方 級數(N2)的衰減’此現象稱為Elmore定理。上述之高電晶 6 200811704 體的加法器設計雖解決了臨界電壓衰退問題（threshold loss problem)，但其Elmore問題依舊存在。 然而，目前的十個電晶體（10T)的全加器設計[Hung Tien Bui, Yuke Wang and Yingtao Jiang; “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates” IEEE Transactions on Systems II: Express Briefs, Volume: 49，Issue: 1，pp. 25 - 30· Jan· 2002]，[R· Shalem，E· John，and L· K· John，“A novel low _ power energy recovery full adder cell，” in Proc. Great Lakes Symp. VLSI, pp· 380-383·，Feb· 1999]，共計超過 40 以上 的設計，其輸出訊號準位除了有衰減兩次的Vt的問題 (2 Vtn+Vtp或者2Vtp+Vtn)，在學術上稱為多重臨界電壓衰 退問題(multi-threshold lose problem)。該多重臨界電壓衰 退問題表現出目前的十個電晶體全加器設計在串接的驅 動上面將有更嚴重的Elmore效應，除此之外其操作電壓亦 無法低於2.8V(0.35um製程），因而大大的降低了這類加法 •器的實用性。 十個電晶體（10T)組成的加法器在佈局面積上有絕對 的優勢，但在這種極端少量電晶體數目的設計技巧下，如 何保有高效能與低動作電壓的特點，將是一個嚴苛的設計 考驗。以10T中性能最好的靜態能量恢復全加器（static energy-recovery full-adder ; SERF)來說明，如「第 1 圖」 SERF的電路架構示意圖所示。其所依據的全加器的演算 法公式為：Sum=(A〇B) · Cin+(A㊉B) · Q ; C_=(A㊉B) · 200811704200811704 / IX, invention description: ^ [Technical field of invention] The present invention relates to the technology of full adder circuit design, especially designed under the condition of low number of transistors, high speed, low power consumption, low operating voltage and high driving capability The full adder circuit. [Prior Art] In general, the design of the full adder is simplified by Karnaugh Map, and the full adder is directly designed with the result of the reduction; however, this design is in the transistor. When the number drops to a minimum of 1 transistor (10 Transistors; 10T), the output signal voltage of the circuit will be attenuated, especially when applied to a multi-bit serial adder, this attenuation phenomenon will appear Very important. This is because in the case of serial applications, the signal may have to be transmitted from the lowest bit to the highest bit in the worst case. Therefore, the poor signal driving capability will greatly affect the performance of the entire circuit speed. , and more power consumption. The general cause of the attenuation of the output potential is due to the use of Transistor Logic (Pass Transistor Logic) to implement the circuit architecture in order to reduce the transistor-count in the circuit structure, thus causing certain conditions. There will be an output voltage level attenuation called a threshold loss problem. In the case of an N-type metal oxide semiconductor (NM0S), a high-potential signal is transmitted while the NM0S transistor is turned on, and its output signal will attenuate a voltage value of Vtn (Vdd-Vtn), where Vtn is the critical value of NM0S. Voltage 5 200811704 (NMOS-Threshold Voltage) (typical value is 〇·6~0.8V in the case of 0.35um process considering matrix benefit.), meaning that the output potential is not the operating voltage 'but a lower Vtn than the operating voltage Voltage value. The same problem occurs in P-type metal oxide semiconductor (PMOS). When the PMOS is transmitting low potential, the output signal will be higher than the low voltage by a voltage value of Vtp, where Vtp is the PMOS threshold voltage (PMOS-Threshold Voltage). (Typical value is -0·7~_0·95ν in the case of the 〇·35 leg process considering the matrix benefit), meaning that the output potential is not the operating voltage, but a voltage higher than the operating voltage by a voltage of Vtp. To solve this problem, an inverter is added to the circuit structure to provide complementary control signals, and at the same time, PMOS and NMOS are used to transmit signals, so-called transmission gates. For example [A· Shams and M· Bayoumi, “A Novel High-Performance COMS l_Bit Full-Adder Cell” IEEE Trans. Circuits and Systems-II, Vol.47 No.5, May 2000·][ N· Zhuang and H· Wu, "A New design of the CMOS full adder," IEEE J. of Solid state circuits, Vol. 27, No. 5, _ ρρ·84〇-844, May 1992·]. However, this is accompanied by an increase in the number of integrated circuit transistors and the silicon area, as well as an increase in power consumption. In addition, when the circuit structure uses MOS as the switching element, the application of the switch as a series connection has a problem of signal transmission delay, and the buffer or inverter is not used for the serially connected switch. In the case of split compensation, the speed of signal transmission and the number of series (N) are approximately squared (N2) attenuation'. This phenomenon is called Elmore's theorem. Although the adder design of the high-crystal crystal 6 200811704 body solves the threshold loss problem, the Elmore problem still exists. However, the current ten-cell (10T) full adder design [Hung Tien Bui, Yuke Wang and Yingtao Jiang; "Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates" IEEE Transactions on Systems II: Express Briefs, Volume: 49, Issue: 1, pp. 25 - 30· Jan· 2002], [R· Shalem, E·John, and L·K·John, “A novel low _ power energy recovery full Adder cell," in Proc. Great Lakes Symp. VLSI, pp. 380-383,, Feb 1999], a total of more than 40 designs, the output signal level in addition to the problem of Vt attenuated twice (2 Vtn+ Vtp or 2Vtp+Vtn) is academically called a multi-threshold lose problem. The multi-threshold voltage decay problem shows that the current ten transistor full adder designs will have a more severe Elmore effect on the series drive, and the operating voltage cannot be lower than 2.8V (0.35um process). Therefore, the practicality of such an adder is greatly reduced. Tenth transistor (10T) adder has an absolute advantage in layout area, but under the design skill of this extremely small number of transistors, how to maintain high efficiency and low operating voltage characteristics will be a harsh The design test. The static energy-recovery full-adder (SERF) is the best performance in 10T, as shown in the circuit diagram of SERF. The formula for the full adder based on it is: Sum=(A〇B) · Cin+(A 十B) · Q ; C_=(A 十B) · 200811704
Cin+(A0B) · A。當第一級XN〇R邏輯區塊i其兩個輸入 加數A和被加數B同時為高準位時(A=1，B=1)，上方的 兩個PMOS電晶體是關閉的，該第一級XN〇R邏輯區塊1 的輸出Q1將是由下方兩個NMOS電晶體傳高準位所得， 由於NMOS電晶體傳高準位將有電壓衰退問題(thresh〇ld loss problem)，因此其最高準位將只能到vdd_Vtn。此一輸 出又必須控制最後產生一和輸出Suin的第二級XN0R邏 輯區塊2，及產生一進位輸出c_之二對一多工器3等邏 • 輯電路中電晶體的閘極(gate)，再加上該第二級xn〇R邏 輯區塊2及二對一多工器3内NM0S電晶體之電壓衰退， 其進位輸出C〇ut之隶南準位將只能到vd(j-2Vtn，其最低準 亦因二對一多工器3内PM0S電晶體之電壓衰退而上升到 |Vtp|，使得最後輸出會有多重臨界電壓衰退的問題。 同樣的情況亦會發生在其他目前已發表之十個電晶 體全加器上，因此目前10T的全加器，其操作電壓不能太 低，該操作電壓不能低於2Vtn+|Vtp|(或2|Vtp|+Vtn)，否則 參 將會造成它無法使用於低電壓操作的電路中。此外，一般 加法器在使用上大都是串聯組成多個位元使用，那麼進位 輸出的傳遞將是要考慮的，在此情況下這類電路的進位輸 出準位會造成它的驅動能力不佳，使得串聯的效能不彰， 加上此種設計架構在串接上也會有Elmore效應的問題，造 成效能低落，使得目前1〇τ的全加器的應用困難，這兩個 缺點同時嚴重的影響其串接上的效能。 習知為解決這個問題，可使用較多的電晶體，也就是 200811704 使用PMOS和NMOS同時傳遞信號就不會面臨這個問題， 這個架構稱為傳輸閘架構(Transmission gate)。例如原先的 的傳輸電晶體邏輯若使用一個NMOS電晶體，使用傳輸閘 架構架構中要除了要使用MOS+PMOS還要多一個反相器 (2T)，因此傳輸閘架構實際要比傳輸電晶體邏輯多出三個 電晶體，換言之，在10T的限制下將無法使用傳輸閘架構。Cin+(A0B) · A. When the first stage XN〇R logic block i has two input addends A and an addend B simultaneously at a high level (A=1, B=1), the upper two PMOS transistors are turned off. The output Q1 of the first stage XN〇R logic block 1 will be obtained by the lower two NMOS transistors passing the high level. Since the NMOS transistor high level will have a voltage decay problem (thresh〇ld loss problem), Therefore, its highest level will only be able to go to vdd_Vtn. This output must in turn control the second stage XN0R logic block 2 that ultimately produces one and output Suin, and the gate of the transistor in the logic circuit that generates a carry output c_ two to one multiplexer 3 (gate ), plus the voltage decay of the NM0S transistor in the second stage xn〇R logic block 2 and the two-to-one multiplexer 3, the carry-in output C〇ut's sub-location will only reach vd(j) -2Vtn, the minimum accuracy also rises to |Vtp| due to the voltage decay of the PM0S transistor in the two-to-one multiplexer 3, so that the final output will have multiple threshold voltage degradation problems. The same situation will occur in other current Ten transistors have been published on the full adder, so the current 10T full adder, its operating voltage can not be too low, the operating voltage can not be lower than 2Vtn+|Vtp| (or 2|Vtp| + Vtn), otherwise It will cause it to be used in circuits with low voltage operation. In addition, the general adder is mostly used in series to form multiple bits, then the transfer of the carry output will be considered. In this case, the circuit The carry output level will cause its driving ability to be poor, making the series effect Inadequate, plus this design architecture will also have the Elmore effect in the series connection, resulting in low performance, making the application of the current 1 τ full adder difficult, both of which seriously affect its serial connection. In order to solve this problem, it is known that more transistors can be used, that is, 200811704 will not face this problem when transmitting signals simultaneously using PMOS and NMOS. This architecture is called a transmission gate. For example, the original If the transmission transistor logic uses an NMOS transistor, the transmission gate architecture uses an inverter (2T) in addition to MOS+PMOS, so the transmission gate architecture is actually three more than the transmission transistor logic. A transistor, in other words, will not be able to use the transfer gate architecture under the 10T limit.
前述架構仍是使用MOS電晶體傳遞信號（一個NMOS 或PMOS或兩個MOS同B寸傳)都還是有Eimore效應的問 題，只是傳輸閘架構架構中因為準位沒衰減，加上傳輸時 是PMOS+NMOS並聯一起傳，所以其等效的傳輸電阻比 較小，因此Elmore效應影響會小一點。 綜合來說，目前的10T的全加器有兩大問題：〗.多重 臨界電壓衰退的問題，使得全加器操作電壓不能太低。2. 嚴重的Elmore效應造成效能低落，使得目前ι〇τ的全加 器的應用困難。 而’其它使用較高電晶體的全加器設計雖可以解決 述的問題，但確需使用们6〜28個電晶體(或更如 出設計成本’也電晶發數量的増加也將增加不 L發明内容】 爰是，本發明之主要目的在於提供—種 :構並::路架構之全加器可以在串接 = 性，並在串接應用上，可以不用額外増加補償電= 200811704 之下保有一定水準的效能，以減低設計上的複雜度和成本 的浪費。 本發明係一種互補式進位邏輯電壓補償之全加器，其 包括一第一多工器，其兩輸入端分別輸入一進位輸入及一 進位反向輸入，及一選擇端輸入一加數訊號；一第一反向 器，其輸入端接入該第一多工器之輸出訊號；一第二多工 器，其兩輸入端分別輸入該加數及一被加數，及一選擇端 輸入該第一反向器之輸出訊號，且該第二多工蒸之輸出端 • 產生一進位訊號；一第二反向器，其輸入端接入該第二多 工器之輸出訊號產生一進位反向訊號；及一第三多工器， 其兩輸入端分別輸入該被加數及該第二反向器產生之進 位反向訊號，及一選擇端輸入該第一反向器之輸出訊號， 且該弟二夕工ι§之輸出端產生一總和訊號。 其中’該弟一、第二及第三多工器係由兩個電晶體， 一 PMOS電晶體做為第一輸入端之開關，及一 NM〇s電晶 體作為一第二輸入端之開關元件。 • 當該第—多工器之第—輸人端接人該進位輸入，且第 二輸入端接入該進位反向輸入，藉此該第一多工器之輸出 訊號再經$該第-反向器之反置’形成- XNOR邏輯電 路且該第一多工器之第一輸入端接入該被加數，第二輸 入端接入該加數；該第三多m人端接入該第二 反向器產出之進位反向訊號，第二輸入端接入該加被數。 當，第一多工器之第一輪入端接入該進位反向輸 入’且弟二輸人端接人該進位輸人，藉此該第—多工器之 200811704 輸出訊號再經過該第-反向II之反置，形成—職邏輯 電路且該第—多U—輪人端接人該加數，第二輸 入端接t該被加數；該第三多4之第—輸人端接入該加 被數f一輪入端接入該第二反向器產出之進位反向訊 號。 如是，本發明提出一種全新十個電晶體的全加器之電 路架構，在不增加電晶體數量的限制之下將兩個反向器電 路成功的沿著進位傳遞路徑嵌入全加器電路架構之中，以 • 降低其十個電晶體全加器設計輸出的訊號準位衰減幅度 並增近效成，使原本有哀減兩次Vt才能達到正確的邏輯 運鼻功能’進一步改良為只哀減一個Vt的電壓幅度。 而在串接的部份，在進位訊號傳遞的最長路徑 (Critical Path)裡，本發明之電路架構並不會出現冗長的傳 輸電晶體邏輯(Pass Transistor Logic)串接的情形，這是由 於電路架構中的反相器恰好在進位傳遞的最長路徑上，因 此，每一次的訊號傳遞，後面都會接上一個反相器隔開與 Φ 下一級的開關直接傳遞的機會，減輕上述Elmore效應的問 題，並且將上一個開關在特定情況所衰減的電位修正回 來0 【實施方式】 茲有關本發明之詳細内容及技術說明，現配合圖式說 明如下： 請先參閱「第2圖」所示，係為所有十個電晶體加法 11 200811704 器皆可適用之真值表(Truth Table)。當推導本發明互補式進 位邏輯電壓補償之全加器，由於是採用互補進位方式設 计’因此在輸入訊说搁位中須將G (上一級的反置進位輸 出）一起列入考慮。而選擇訊號，它是由第一級的X〇R邏 輯或XNOR邏輯型態運算後產生，為10T電路中之内部主 要控制訊號，其功能是用來當作總和訊號Sum輪出結果和 進位訊^虎Cout產生為的貢料選擇線。依設計需求可採用 XOR(A㊉B)邏輯或者是XNOR(AOB)邏輯型式實現。而 • 最後的輸出訊號攔位除了加法器中原有的總和訊號Sum 與進位訊號C^t之外，亦列出了本發明所需的進位反向訊 號 c〇ut 〇 以第一級的XOR邏輯型式之本發明的總和訊號Sum 為例子，當輸入的加數A和進位輸入Cin同時為低電位時， 該選擇中A㊉Cin之結果為0,此時我們期望的總和訊號 Sum的結果，在被加數B=0時會一樣為0,而當被加數B=1 時總和訊號Sum也一樣為1 ;而當加數A和進位輸入Cin • 同時為高電位時，A㊉Cin之結果亦為〇，也是如上述的情 況；換句話說當A㊉Cin之結果為〇時，總和訊號Sum之 結果將可由輸入訊號被加數B提供。而當輸入加數A和進 位輸入Cin不相等時（不同時為高電位或是低電位）使得 A㊉cin之結果為1，那麼總和訊號Sum的結果將可以由進 位反向訊號^7⑽提供。同樣的道理，當表中選擇的A㊉Cin 之結果為〇，進位訊號C_之電位將可以從輸入的加數A 獲得；而當選擇的中A㊉Cin之結果為1，進位訊號c_的 12 200811704 電位將可以由輸入的被加數B所提供The foregoing architecture still uses the MOS transistor to transmit signals (one NMOS or PMOS or two MOS and B-inch transmission). There is still the problem of Eimore effect, but the transmission gate architecture is not attenuated because of the level, and the PMOS is transmitted. + NMOS is transmitted in parallel, so its equivalent transmission resistance is relatively small, so the effect of Elmore effect will be smaller. In summary, the current 10T full adder has two major problems: 〗. Multiple threshold voltage degradation problems, so that the full adder operating voltage can not be too low. 2. The severe Elmore effect causes low performance, making the current application of ι〇τ's full adder difficult. And 'others use the higher transistor design of the full adder can solve the problem, but it is necessary to use 6~28 transistors (or more like the design cost), the number of cells will also increase. The content of the invention is that the main purpose of the present invention is to provide a kind of structure: the full complement of the road structure can be connected in series=sexuality, and in the serial connection application, the compensation power can be added without additional compensation = 200811704 The utility model has a certain level of performance to reduce the complexity of design and waste of cost. The invention is a full complement of complementary carry logic voltage compensation, which comprises a first multiplexer, and two inputs are respectively input into one a carry input and a carry reverse input, and a select terminal input an add signal; a first inverter, the input end of which is connected to the output signal of the first multiplexer; a second multiplexer, two of The input terminal inputs the addend and the addend, respectively, and a select terminal inputs the output signal of the first inverter, and the output of the second multiplex steam generates a carry signal; a second inverter , the input terminal is connected to the second more The output signal of the device generates a carry reverse signal; and a third multiplexer, the two input ends respectively input the addend and the carry reverse signal generated by the second reverser, and a select end inputs the The output signal of the first inverter, and the output of the second-party device generates a sum signal. The 'the first, second and third multiplexers are composed of two transistors, one PMOS transistor The switch is used as the first input terminal, and a NM〇s transistor is used as the switching element of the second input terminal. • When the first input end of the first multiplexer is connected to the carry input, and the second input The terminal is connected to the carry reverse input, whereby the output signal of the first multiplexer is further formed by the inverse of the first inverter to form an XNOR logic circuit and the first input end of the first multiplexer Accessing the added number, the second input terminal accesses the addend; the third multi-m human terminal accesses the carry reverse signal generated by the second reverser, and the second input end accesses the add-on number When the first round of the first multiplexer is connected to the carry reverse input 'and the second input terminal is connected to the carry Thereby, the 200811704 output signal of the first multiplexer is further reversed by the first-reverse II to form a logic circuit, and the first-multi-U-wheel terminal terminates the addend, and the second input end The third multi-fourth-input terminal accesses the add-on number f and the round-in end accesses the carry reverse signal generated by the second inverter. If so, the present invention proposes a The circuit structure of the new ten-cell full adder, successfully inserting two inverter circuits along the carry transfer path into the full adder circuit architecture without increasing the number of transistors, to reduce its Ten signal crystals are designed to output the signal level attenuation amplitude and increase the effect, so that the original Vt can be achieved by reducing the Vt twice to further improve the voltage amplitude of a Vt. In the serialized part, in the critical path of the carry signal transmission, the circuit architecture of the present invention does not have a lengthy transmission transistor logic (Pass Transistor Logic) series connection, which is due to the circuit. The inverter in the architecture happens to be in The longest path of the bit transfer, therefore, each time the signal is transmitted, an inverter is connected to the next pass to separate the switch with the next level of Φ, alleviating the above Elmore effect, and the previous switch is specific. The potential attenuation is abruptly corrected. [Embodiment] The details and technical description of the present invention are as follows: Please refer to "Figure 2" for all ten transistor additions. The Truth Table is applicable to all 200811704 devices. When the full adder of the complementary carry logic voltage compensation of the present invention is deduced, since it is designed by the complementary carry mode, G (the inverted carry output of the previous stage) must be taken into consideration in the input speech shift. The selection signal is generated by the first stage X〇R logic or XNOR logic type operation, and is the internal main control signal in the 10T circuit, and its function is used as the sum signal Sum round result and carry signal ^ Tiger Cout produces a tribute selection line. According to the design requirements, XOR (A 10 B) logic or XNOR (AOB) logic type can be used. • The final output signal blocker, in addition to the original sum signal Sum and the carry signal C^t in the adder, also lists the carry reverse signal c〇ut 本 required by the present invention with the first level of XOR logic. The sum signal Sum of the present invention is an example. When the input addend A and the carry input Cin are simultaneously low, the result of the A ten Cin in the selection is 0, and the result of the sum signal Sum we expect is added. The number B=0 will be the same as 0, and when the addend B=1, the sum signal Sum is also 1; and when the addend A and the carry input Cin • are simultaneously high, the result of A ten Cin is also 〇, It is also the case as described above; in other words, when the result of A ten Cin is 〇, the result of the sum signal Sum will be supplied by the addend B to the input signal. When the input addendum A and the carry input Cin are not equal (not high or low at the same time), the result of the A ten cin is 1, and the result of the sum signal Sum can be provided by the carry reverse signal ^7 (10). By the same token, when the result of A C Cin selected in the table is 〇, the potential of the carry signal C_ can be obtained from the input addend A; and when the result of the selected A ten Cin is 1, the carry signal c_ is 12 200811704 potential Will be provided by the added addend B
號Cout輸出之電路。而進位万 進位反向訊號q係採用一反相器No. Cout output circuit. The carry-in unidirectional reverse signal q uses an inverter
T麵istor Logic)方式❸設収下，此反相器還可將衰退的 輸出準位拉回，因此本發明之電路可以很有效的同時改良 鲁上述傳輸邏輯方式在串接和輸出電壓衰減之兩個問題，並 使用同樣數量的電晶體（十個電晶體）。 由於本發明在架構上所需要達到的增加輸出驅動能 力以及在串接上的速度提升，其電路架構相較於一般的全 加器電路除了有加數A、被加數b、進位輸入Qn、總和訊 號Sum以及$位訊號c_五個輸入輸出腳位之外，多了進 位反向輸入Q輸入和反置進位輸出（Q)，這也是本發明之 電路架構的最大特徵。 _ 進一步前述之分析後，本發明之在設計上將基本全加 器的演异法改寫成如下兩式：The T-surface istor Logic method is set to receive, and the inverter can also pull back the output level of the decay. Therefore, the circuit of the present invention can effectively improve the above-mentioned transmission logic mode in series and output voltage attenuation. Two problems and use the same number of transistors (ten transistors). Due to the increased output drive capability and the speed increase in the series connection required by the present invention, the circuit architecture has an addendum A, an addend b, and a carry input Qn compared to a general full adder circuit. In addition to the sum signal Sum and the bit signal c_ five input and output pins, the carry inversion input Q input and the inverted carry output (Q) are added, which is also the biggest feature of the circuit architecture of the present invention. _ Further, after the foregoing analysis, the present invention is designed to rewrite the basic full adder's algorithm into the following two forms:
Sum=(A ㊉ Cin) · c-+(A0Cin) · B ; C0Ut=(A ㊉ Cin) · B+(A0Cin) · A 〇 由演算式所推導出本發明的全加器架構圖如「第3圖」 所示，本發明係一種互補式進位邏輯電壓補償之全加器， 其包括一第一多工器11，其包含兩輸入端inO、ini分別輸 入進位輸入Cin及一進位反向輸入G，，及一選擇端sei 13 200811704 輸入一加數訊號A; —第一反向器21，其輸入端接入該第 一多工器之輸出訊號；一第二多工器12,其兩輸入端in〇、 ini分別輸入該加數A及被加數B，及一選擇端sel輸入該 第一反向器之輸出訊號，且該第二多工器12之輸出端產 生一進位訊號Cout ; —第二反向器22，其輸入端接入該第 二多工器12之輸出訊號產生一進位反向訊號Q ;及一第 三多工器13，其兩輸入端in〇、ini分別輸入該被加數B 及該第二反向器產生之進位反向訊號，及一選擇端sel輸 ❿ 入該第一反向器21之輸出訊號，且該第三多工器13之輸 出端產生一總和訊號Sum。 其中，該進位輸入Cin係為上一級輸出的進位訊號 Cout，且該進位反向輸入G係為上一級輸出的進位反向訊 號C⑽ί 〇 其中，該第一、第二及第三多工器11、12、13僅須 使用一個兩個電晶體構成之多工器即可完成，——PMOS電 晶體做為第一輸入端inO之開關，及一 NMOS電晶體作為 籲一第二輸入端ini之開關元件。 當該第^多工11之弟一輸入端inO接入該進位輸入 Cin，且第二輸入端ini接入該進位反向輸入Q，藉此該第 一多工器11之輸出訊號再經過該第一反向器21之反置， 形成一 XNOR邏輯電路。且該第二多工器12之第一輸入 端inO接入該被加數B，第二輸入端ini接入該加數A;該 第三多工器13之第一輸入端比0接入該第二反向器22產 出之進位反向訊號。，第二輸入端ini接入該加被數b。 200811704 該第二反向器22與第三多工器13組成另一個類似XNOR 功能而獲得總和訊號Sum的同時’並有效運用該第二反向 器22將準位拉回。 請再參閱「第4圖」所示，係本發明之另一全加器架 構圖示意圖。當該第一多工器11之第一輸入端in0接入該 進位反向輸入C/w，且第二輸入端接ini入該進位輸入Cm， 藉此該第一多工器11之輸出訊號再經過該第一反向器21 之反置，形成一 XOR邏輯電路。且該第二多工器12之第 _ 一輸入端in〇接入該加數A，第二輸入端ini接入該被加 數B;該第三多工器13之第一輸入端比0接入該加被數B， 第二輸入端ini接入該第二反向器22產出之進位反向訊號 c咖，該。 請參閱「第5圖」所示，為本發明依照XNOR邏輯形 式之十個電晶體全加器電路圖。本發明完成第一級的 XOR/XNOR邏輯運算的電路是以一個兩輸人之多工器搭 配互補的進位訊號所取代，該第一多工器11由加數A選 • 擇其輸出的結果是進位輸入Cin或是進位反向輸入Q，由 於在電路的設計上本發明能產生互補的進位輸出訊號Cout 與^^ ，因此本發明之輸入訊號比一般加法器多一個Q的 原因）。本發明在產生第一級訊號(XOR/XNOR邏輯運算） 時將僅須使用一個兩個電晶體一 PMOS電晶體，及一 NMOS電晶體作為輸入端之開關元件，且其餘第二及第三 多工器12、13也僅須使用一個兩個電晶體構成之多工器 即可完成。因此，可以看出本發明第一級的運算結果緊接 15 200811704 著被其輸出後的第一反相器21將準位拉回之後，再控制 最後的總和訊號Sum與進位訊號Cout的輸出電晶體之閘 極，因此在關心的準位問題方面，本發明之加法器電路中 最後總和訊號Sum的輪出電壓準位最多只衰減一個Vt的 幅度，同樣的進位訊號Cout最多只會有衰減一個vt的幅 度，至於另一個Q則是完美的輸出準位訊號。 另一方面’在串接的應用上，本發明在多位元的串接 應用上該進位訊號和進位訊號出必須接到下一級的進位 輸入和反置進位輸入。以本發明之全加器所組成之多位元 加法器其進位傳遞的最長路徑(Critical Path)裡面，是多工 器和反相器交替組合出現，因此將原本可能出現的傳輸電 晶體(Pass Transistor)串接問題，得以反相器分隔，大幅的 改善了目前已發表的所有十個電晶體會出現的Elmore效 應問題。 前述之全加器電路架構相對於先前的全加器電路設 計理論，本發明有兩個重要的改良重點： 第一點：本發明之電路架構避免使用電壓準位衰減的 電位控制最後產生進位訊號CQut與總和訊號Sum的電晶體 之閘極端’以防止會有之前所介紹的一般低電晶體數全加 器在輸出上的多重電壓準位衰減，造成電路内部電壓訊號 的準位下降。 弟一點·進位訊號在傳遞時，減少傳輸電晶體(Pass Transistor)串接的幅度以增加傳遞上的效率，這是由於在 Elmore定理裡，傳遞延遲的上升是依據串接的傳輸電晶體 200811704 ， 數目的平方倍’因此減少進位訊號在傳遞路徑上所經過的 傳輸電晶體串接巾*度將會對全加㈣串接應用上有相當 大的助益。 本發明之全加器藉由反相器結構（Inverter-Based) XOR/XNOR的设计’在保持使用十個電晶體的情況下，巧 妙的利用反相器具有準位回復與切斷過長的傳輸陸捏的 優點，解決其他十個電晶體全加器有連續準位衰退與傳輸 距離過長造成效能低落的問題。因此在應用上，本發明因 •為其他1〇T的多重臨界電壓衰退問題(multi-threshoM lose problem)，因此最低的動作電壓將可從28V大幅降低至 1.9V(0.35um製程），而當使用先進的〇 18um製程時習知 電路仍要h8V’而本發明則可低於1.15V，已經可以使用 單-電池操作。即，本發明之全加器將比其他十個電晶體 全加器更適用低電墨操作的電路，特別是使用電池作為驅 動的應用電路。 本發月之王加器、採用反相器結構（Inverter-Based) XOR/XNOR除了有上述低操作電壓的優點之外，反相器還 有高驅動能力的優點，換句話說本發明之全加器在速度上 也將南於其他十個電晶體全加器。本發明之全加器在速度 方面與其它ιοτ加法器相比，在組成8bit〜16bit的加法器 %大幅提升5〜1G倍的效能，而各電路最快工作頻率下之 力率/肖耗所、、先冲之功率速度乘積比Deiay pr〇(juct · I>DP)上本發明之全加器除了大幅領先其它ι〇τ 加法器 外，經過電晶體數目正常化(Normalized)(PDP除上電路相 17 200811704 較於十個電晶體的倍數）後亦超越其它一般以電晶體數較 高所設計的28T、20T、TGA、16T和14T等加法器。 本發明提出一種全新十個電晶體全加器設計設計之 電路架構之主要精神，係在不增加電晶體數量的限制之下 將反向器電路嵌入全加器電路架構之中，用以降低其十個 電晶體全加器設計輸出的訊號準位衰減幅度，使原本有衰 減兩次Vt才能達到正確的邏輯運算功能，進一步改良為 只衰減一個Vt的電壓幅度。而在串接的部份，在進位訊 _ 號傳遞的最長路徑(Critical Path)裡，本發明之電路架構並 不會出現冗長的傳輸電晶體(Pass Transistor)串接的情形， 這是由於電路架構中的反相器恰好在訊號傳遞的最長路 徑上，因此，每一次的訊號傳遞，後面都會接上一個反相 器隔開與下一級的開關直接傳遞的機會並且將上一個開 關在特定情況所衰減的電位修正回來，依照Elmore定理， 開關總共串接的級數(N)和整個串接的級數依一定的串接 數量（M)插入反相器作補償，在不考慮反相器的電路速度 延遲之下，經過反相器加強的電路其延遲時間將會由原本 的N2縮小到N*M(达M<N)，大幅改善一般低電晶體數量 之全加裔在多位元的應用上的速度過慢缺點。 據此，依照本發明所提供的架構設計可以獲得較高速 =多位元加法器，如此，在不需額外付出設計成本之下以 最少的電晶體數量完成高效能的多位元加法器電路，對於 加法器在電路設計的各種應用之下是相當方便有效率的。 上述过明僅為本發明之較佳實施例而已，並非用來限 18 200811704 定本發明實施之範圍。即凡依本發明申請專利範圍所做的 均等變化與修飾，皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖，係SERF的電路架構示意圖。 第2圖，係為所有十個電晶體加法器皆可適用之真值表。 第3圖，係本發明之全加器架構圖示意圖。 第4圖，係本發明之另一全加器架構圖示意圖。 釀第5圖，為本發明依照XNOR邏輯形式之十個電晶體全加 器電路圖。 【主要元件符號說明】 I :第一級XNOR邏輯區塊 2:第二級XNOR邏輯區塊 3:二對一多工器 II :第一多工器 _ 12 :第二多工器 13 :第三多工器 21 :第一反向器 22 :第二反向器 A :加數 B ·被加數 Sum :總和訊號 Cin :進位輸入 19 200811704 Q:進位反向輸入 cout :進位訊號 Q:進位反向訊號Sum=(A 十 Cin) · c-+(A0Cin) · B ; C0Ut=(A 十 Cin) · B+(A0Cin) · A 推 The full-charger architecture diagram of the present invention is derived from the formula As shown in the figure, the present invention is a full complement logic voltage compensation full adder comprising a first multiplexer 11 comprising two input terminals inO, ini respectively input carry input Cin and a carry reverse input G , and a selection terminal sei 13 200811704 input a plus signal A; - a first inverter 21, the input end of which is connected to the output signal of the first multiplexer; a second multiplexer 12, two inputs thereof The terminal in〇, ini respectively input the addend A and the addend B, and a select terminal sel inputs the output signal of the first inverter, and the output end of the second multiplexer 12 generates a carry signal Cout; a second inverter 22 having an input signal connected to the output signal of the second multiplexer 12 to generate a carry reverse signal Q; and a third multiplexer 13 having two input terminals in and in respectively input The carry-in reverse signal generated by the addend B and the second inverter, and a selection terminal sel input the output signal of the first inverter 21, and the output signal 3 multiplexer of the output terminal 13 generates a sum signal Sum. The carry input Cin is the carry signal Cout outputted by the previous stage, and the carry reverse input G is the carry reverse signal C(10) of the previous stage output, wherein the first, second and third multiplexers 11 12, 13 can only be completed by using a multiplexer composed of two transistors, PMOS transistor as the switch of the first input terminal inO, and an NMOS transistor as the second input terminal ini Switching element. When the input end inO of the first multiplexer 11 is connected to the carry input Cin, and the second input end ini is connected to the carry reverse input Q, the output signal of the first multiplexer 11 passes through the The first inverter 21 is reversed to form an XNOR logic circuit. The first input end inO of the second multiplexer 12 is connected to the addend B, and the second input end ini is connected to the addend A; the first input end of the third multiplexer 13 is connected to 0. The carry reverse signal generated by the second inverter 22. The second input terminal ini is connected to the plus number b. 200811704 The second inverter 22 and the third multiplexer 13 form another XNOR-like function to obtain the sum signal Sum and effectively use the second inverter 22 to pull back the level. Please refer to Fig. 4 again, which is a schematic diagram of another full adder frame of the present invention. When the first input end in0 of the first multiplexer 11 is connected to the carry reverse input C/w, and the second input terminal is connected to the carry input Cm, the output signal of the first multiplexer 11 is outputted. Then, through the reverse of the first inverter 21, an XOR logic circuit is formed. The first input terminal in the second multiplexer 12 is connected to the addend A, and the second input terminal ini is connected to the addend B; the first input end of the third multiplexer 13 is 0. The addee number B is accessed, and the second input terminal ini is connected to the carry reverse signal c coffee generated by the second inverter 22. Please refer to Fig. 5, which is a circuit diagram of ten transistor full adders according to the XNOR logic form of the present invention. The circuit for completing the XOR/XNOR logic operation of the first stage of the present invention is replaced by a two-input multiplexer with a complementary carry signal, and the first multiplexer 11 selects the output result of the addendum A. It is a carry input Cin or a carry reverse input Q. Since the present invention can produce complementary carry output signals Cout and ^^ in the design of the circuit, the input signal of the present invention has one more Q than the general adder). The invention only needs to use one transistor-PMOS transistor when generating the first-level signal (XOR/XNOR logic operation), and an NMOS transistor as the switching component of the input terminal, and the remaining second and third The tools 12, 13 can also be completed using only one multiplexer composed of two transistors. Therefore, it can be seen that the operation result of the first stage of the present invention immediately controls the output of the last sum signal Sum and the carry signal Cout after the first inverter 21 whose output is pulled back by the 2008 11704. The gate of the crystal, so in the aspect of the problem of interest, the voltage level of the final sum signal Sum in the adder circuit of the present invention is only attenuated by at most one Vt, and the same carry signal Cout is only attenuated at most. The magnitude of vt, as for another Q, is the perfect output level signal. On the other hand, in the case of serial connection, the carry signal and the carry signal of the present invention must be connected to the carry input and the inverted carry input of the next stage in the multi-bit serial connection application. In the longest path (Critical Path) of the multi-bit adder composed of the full adder of the present invention, the multiplexer and the inverter are alternately combined, so that the transmission transistor which may have appeared originally (Pass) Transistor) is a cascade problem that can be separated by inverters, greatly improving the Elmore effect of all ten transistors that have been published so far. Compared with the previous full adder circuit design theory, the present invention has two important improvements: First, the circuit architecture of the present invention avoids potential control using voltage level attenuation and finally generates a carry signal. CQut and the sum gate Sum's transistor gate terminal 'to prevent the multi-voltage level attenuation on the output of the general low-crystal number full adder introduced before, causing the level of the internal voltage signal of the circuit to drop. When the carry signal is transmitted, the amplitude of the transmit transistor (Pass Transistor) is reduced to increase the efficiency of the transfer. This is because in the Elmore theorem, the rise of the transfer delay is based on the serially connected transmission transistor 200811704. The square of the number 'thus reducing the transmission transistor linings that the carry signal passes on the transmission path will be of considerable benefit to the full-plus (four) concatenation application. The full adder of the present invention is designed by Inverter-Based XOR/XNOR's. In the case of using ten transistors, the inverter is used to have a level of recovery and cut off too long. The advantage of transmitting land pinch is to solve the problem that the other ten transistor full adders have continuous level decay and long transmission distance, resulting in low performance. Therefore, in application, the present invention is a multi-threshoM loss problem of other 1〇T, so the lowest operating voltage can be greatly reduced from 28V to 1.9V (0.35um process), and when The conventional circuit still requires h8V' when using the advanced 〇18um process and the present invention can be lower than 1.15V, and single-cell operation is already available. That is, the full adder of the present invention will be more suitable for circuits with low ink operation than other ten transistor full adders, particularly those that use batteries as a drive. In addition to the advantages of the above-mentioned low operating voltage, the inverter has the advantage of high driving capability, in other words, the full invention of the present invention. In addition to the advantages of the above-mentioned low operating voltage, the inverter has the advantage of high driving capability. The adder will also be souther than the other ten transistor full adders in speed. Compared with other ιοτ adders, the full adder of the present invention greatly increases the performance of the adder of 8bit~16bit by 5~1G times, and the power rate/short consumption of each circuit at the fastest working frequency. , the power ratio of the first impulse to the product ratio Deiay pr〇(juct · I>DP). The full adder of the present invention is normalized by the number of transistors except for a large lead other than the ιττ adder (PDP is divided The circuit phase 17 200811704 is also superior to other 28T, 20T, TGA, 16T and 14T adders designed with a higher number of transistors than the multiples of ten transistors. The invention proposes a main spirit of a circuit architecture of a new ten-transistor full adder design, embedding an inverter circuit in a full-adder circuit structure without reducing the number of transistors, thereby reducing the The attenuation level of the signal level of the output of the ten transistor full adder design makes it possible to achieve the correct logic operation function by attenuating twice Vt, and further improved to attenuate only one Vt voltage amplitude. In the serial part, in the critical path of the carry signal transmission, the circuit structure of the present invention does not have a long transmission transistor (Pass Transistor) series connection, which is due to the circuit. The inverter in the architecture happens to be on the longest path of the signal transmission. Therefore, each time the signal is transmitted, an inverter is connected to the opportunity to directly pass the switch with the next stage and the previous switch is in a specific situation. The attenuated potential is corrected back. According to Elmore's theorem, the total number of series (N) of the switch and the entire series of series are inserted into the inverter for compensation according to a certain number of series (M), regardless of the inverter. Under the circuit speed delay, the delay time of the circuit enhanced by the inverter will be reduced from the original N2 to N*M (up to M<N), which greatly improves the total number of low-transistors in the multi-bit The shortcomings of the application are too slow. Accordingly, the architecture design provided in accordance with the present invention can achieve a higher speed = multi-bit adder, thus completing a high-performance multi-bit adder circuit with a minimum number of transistors without additional design cost. It is quite convenient and efficient for the adder to be used in various applications of circuit design. The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention. [Simple description of the diagram] Figure 1 is a schematic diagram of the circuit architecture of the SERF. Figure 2 is a truth table for all ten transistor adders. Figure 3 is a schematic diagram of the full adder architecture of the present invention. Figure 4 is a schematic diagram of another full adder architecture of the present invention. Figure 5 is a circuit diagram of ten transistor full adders in accordance with the XNOR logic form of the present invention. [Main component symbol description] I: First stage XNOR logic block 2: Second stage XNOR logic block 3: Two-to-one multiplexer II: First multiplexer _ 12: Second multiplexer 13: Three multiplexer 21: first inverter 22: second inverter A: addend B · addendum Sum: sum signal Cin: carry input 19 200811704 Q: carry reverse input cout: carry signal Q: carry Reverse signal