AU2001290937A1 - Method of design and fabrication of integrated circuits using regular arrays and gratings - Google Patents
Method of design and fabrication of integrated circuits using regular arrays and gratingsInfo
- Publication number
- AU2001290937A1 AU2001290937A1 AU2001290937A AU9093701A AU2001290937A1 AU 2001290937 A1 AU2001290937 A1 AU 2001290937A1 AU 2001290937 A AU2001290937 A AU 2001290937A AU 9093701 A AU9093701 A AU 9093701A AU 2001290937 A1 AU2001290937 A1 AU 2001290937A1
- Authority
- AU
- Australia
- Prior art keywords
- gratings
- fabrication
- design
- integrated circuits
- regular arrays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
- G03F7/2026—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US23245100P | 2000-09-13 | 2000-09-13 | |
US60/232,451 | 2000-09-13 | ||
US27185001P | 2001-02-27 | 2001-02-27 | |
US60/271,850 | 2001-02-27 | ||
PCT/US2001/028777 WO2002025373A2 (en) | 2000-09-13 | 2001-09-13 | Method of design and fabrication of integrated circuits using regular arrays and gratings |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001290937A1 true AU2001290937A1 (en) | 2002-04-02 |
Family
ID=26926010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001290937A Abandoned AU2001290937A1 (en) | 2000-09-13 | 2001-09-13 | Method of design and fabrication of integrated circuits using regular arrays and gratings |
Country Status (3)
Country | Link |
---|---|
US (1) | US6818389B2 (en) |
AU (1) | AU2001290937A1 (en) |
WO (1) | WO2002025373A2 (en) |
Families Citing this family (77)
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JP3501688B2 (en) * | 1999-07-01 | 2004-03-02 | キヤノン株式会社 | Exposure method, exposure apparatus, and device manufacturing method |
US6967708B1 (en) * | 2000-11-10 | 2005-11-22 | National Institute Of Advanced Industrial Science And Technology | Pattern transfer device using PC projector |
TW530336B (en) * | 2001-08-21 | 2003-05-01 | Asml Masktools Bv | Lithographic method and lithographic apparatus |
US6884551B2 (en) * | 2002-03-04 | 2005-04-26 | Massachusetts Institute Of Technology | Method and system of lithography using masks having gray-tone features |
US7651821B2 (en) * | 2002-03-04 | 2010-01-26 | Massachusetts Institute Of Technology | Method and system of lithography using masks having gray-tone features |
US6875624B2 (en) * | 2002-05-08 | 2005-04-05 | Taiwan Semiconductor Manufacturing Co. Ltd. | Combined E-beam and optical exposure semiconductor lithography |
AU2003240931A1 (en) * | 2002-05-29 | 2003-12-19 | Massachusetts Institute Of Technology | A method for photolithography using multiple illuminations and a single fine feature mask |
DE60305584T2 (en) * | 2002-07-26 | 2007-05-24 | Asml Masktools B.V. | Directional shield for use with dipole exposure |
US6854106B2 (en) * | 2002-08-29 | 2005-02-08 | Micron Technology, Inc. | Reticles and methods of forming and using the same |
US6807663B2 (en) * | 2002-09-23 | 2004-10-19 | Numerical Technologies, Inc. | Accelerated layout processing using OPC pre-processing |
US8110345B2 (en) * | 2002-12-04 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High resolution lithography system and method |
DE10310136B4 (en) * | 2003-03-07 | 2007-05-03 | Infineon Technologies Ag | Mask set for the projection of pattern patterns arranged on the masks of the sentence and matched to one another on a semiconductor wafer |
DE10324502B3 (en) * | 2003-05-26 | 2005-04-21 | Infineon Technologies Ag | Photomask, and method for the production of semiconductor devices |
US20040241556A1 (en) * | 2003-05-29 | 2004-12-02 | Bellman Robert A. | Mask, mask blank, photosensitive film therefor and fabrication thereof |
US20040241557A1 (en) * | 2003-05-29 | 2004-12-02 | Bellman Robert A. | Mask, mask blank, photosensitive material therefor and fabrication thereof |
US6993741B2 (en) * | 2003-07-15 | 2006-01-31 | International Business Machines Corporation | Generating mask patterns for alternating phase-shift mask lithography |
US7261982B2 (en) * | 2003-08-07 | 2007-08-28 | Jds Uniphase Corporation | Planar circuit optimization |
US6993742B2 (en) * | 2003-08-08 | 2006-01-31 | Intel Corporation | Thermal proximity effects in lithography |
US20050073671A1 (en) * | 2003-10-07 | 2005-04-07 | Intel Corporation | Composite optical lithography method for patterning lines of substantially equal width |
US20050074698A1 (en) * | 2003-10-07 | 2005-04-07 | Intel Corporation | Composite optical lithography method for patterning lines of significantly different widths |
US7142282B2 (en) * | 2003-10-17 | 2006-11-28 | Intel Corporation | Device including contacts |
US20050085085A1 (en) * | 2003-10-17 | 2005-04-21 | Yan Borodovsky | Composite patterning with trenches |
US20050088633A1 (en) * | 2003-10-24 | 2005-04-28 | Intel Corporation | Composite optical lithography method for patterning lines of unequal width |
US20050112476A1 (en) * | 2003-11-24 | 2005-05-26 | Bellman Robert A. | Phase-shift mask and fabrication thereof |
US7153360B2 (en) * | 2003-12-16 | 2006-12-26 | Hewlett-Packard Development Company, Lp. | Template and methods for forming photonic crystals |
US7255805B2 (en) * | 2004-01-12 | 2007-08-14 | Hewlett-Packard Development Company, L.P. | Photonic structures, devices, and methods |
US7132327B2 (en) | 2004-05-25 | 2006-11-07 | Freescale Semiconductor, Inc. | Decoupled complementary mask patterning transfer method |
TWI229377B (en) * | 2004-07-30 | 2005-03-11 | Touch Micro System Tech | Method for forming cavities having different aspect ratios |
US7302651B2 (en) | 2004-10-29 | 2007-11-27 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
WO2006069340A2 (en) | 2004-12-21 | 2006-06-29 | Carnegie Mellon University | Lithography and associated methods, devices, and systems |
KR100642478B1 (en) | 2004-12-31 | 2006-11-02 | 동부일렉트로닉스 주식회사 | Method for removing the optical proximity effect |
US20060169592A1 (en) * | 2005-01-31 | 2006-08-03 | Hewlett-Packard Development Company, L.P. | Periodic layered structures and methods therefor |
US20060257749A1 (en) * | 2005-05-16 | 2006-11-16 | Sheng-Yueh Chang | Method for reducing critical dimension |
US8132130B2 (en) * | 2005-06-22 | 2012-03-06 | Asml Masktools B.V. | Method, program product and apparatus for performing mask feature pitch decomposition for use in a multiple exposure process |
US20070087291A1 (en) * | 2005-10-18 | 2007-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Lithography process to reduce interference |
US20070153249A1 (en) * | 2005-12-20 | 2007-07-05 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method using multiple exposures and multiple exposure types |
US7532403B2 (en) | 2006-02-06 | 2009-05-12 | Asml Holding N.V. | Optical system for transforming numerical aperture |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
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US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
WO2009018846A1 (en) | 2007-08-09 | 2009-02-12 | Carl Zeiss Smt Ag | Method of structuring a photosensitive material |
US8582079B2 (en) * | 2007-08-14 | 2013-11-12 | Applied Materials, Inc. | Using phase difference of interference lithography for resolution enhancement |
US7759242B2 (en) | 2007-08-22 | 2010-07-20 | Qimonda Ag | Method of fabricating an integrated circuit |
US20090117491A1 (en) * | 2007-08-31 | 2009-05-07 | Applied Materials, Inc. | Resolution enhancement techniques combining interference-assisted lithography with other photolithography techniques |
US20100002210A1 (en) * | 2007-08-31 | 2010-01-07 | Applied Materials, Inc. | Integrated interference-assisted lithography |
US8715909B2 (en) * | 2007-10-05 | 2014-05-06 | Infineon Technologies Ag | Lithography systems and methods of manufacturing using thereof |
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US8309371B1 (en) * | 2009-07-21 | 2012-11-13 | The United States Of America As Represented By The Secretary Of The Navy | System and method for creating a flat wavefront using a photonic crystal |
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JP6060796B2 (en) * | 2013-04-22 | 2017-01-18 | 大日本印刷株式会社 | Imprint mold and dummy pattern design method |
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US9287131B2 (en) * | 2014-02-21 | 2016-03-15 | Globalfoundries Inc. | Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules |
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US5415835A (en) | 1992-09-16 | 1995-05-16 | University Of New Mexico | Method for fine-line interferometric lithography |
US6042998A (en) * | 1993-09-30 | 2000-03-28 | The University Of New Mexico | Method and apparatus for extending spatial frequencies in photolithography images |
US5424154A (en) * | 1993-12-10 | 1995-06-13 | Intel Corporation | Lithographic emhancement method and apparatus for randomly spaced structures |
US5472814A (en) | 1994-11-17 | 1995-12-05 | International Business Machines Corporation | Orthogonally separated phase shifted and unphase shifted mask patterns for image improvement |
US5595843A (en) | 1995-03-30 | 1997-01-21 | Intel Corporation | Layout methodology, mask set, and patterning method for phase-shifting lithography |
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US5772905A (en) * | 1995-11-15 | 1998-06-30 | Regents Of The University Of Minnesota | Nanoimprint lithography |
WO1998002784A1 (en) | 1996-07-15 | 1998-01-22 | Micron Display Technology, Inc. | Method of phase shift lithography |
US5858580A (en) | 1997-09-17 | 1999-01-12 | Numerical Technologies, Inc. | Phase shifting circuit manufacture method and apparatus |
US5959325A (en) | 1997-08-21 | 1999-09-28 | International Business Machines Corporation | Method for forming cornered images on a substrate and photomask formed thereby |
US6534242B2 (en) * | 1997-11-06 | 2003-03-18 | Canon Kabushiki Kaisha | Multiple exposure device formation |
JP3101594B2 (en) | 1997-11-06 | 2000-10-23 | キヤノン株式会社 | Exposure method and exposure apparatus |
JP3123548B2 (en) * | 1998-06-30 | 2001-01-15 | キヤノン株式会社 | Exposure method and exposure apparatus |
JP3352405B2 (en) * | 1998-09-10 | 2002-12-03 | キヤノン株式会社 | Exposure method, device manufacturing method using the same, and semiconductor device |
WO2000025181A1 (en) | 1998-10-23 | 2000-05-04 | Hitachi, Ltd. | Method for fabricating semiconductor device and method for forming mask suitable therefor |
JP3311302B2 (en) * | 1998-10-27 | 2002-08-05 | キヤノン株式会社 | Exposure method |
JP2000315647A (en) * | 1999-05-06 | 2000-11-14 | Mitsubishi Electric Corp | Formation of resist pattern |
US6351304B1 (en) * | 1999-06-04 | 2002-02-26 | Canon Kabushiki Kaisha | Multiple exposure method |
WO2001006320A1 (en) | 1999-07-19 | 2001-01-25 | Marc Levenson | Generic phase shift mask |
US6387596B2 (en) * | 1999-08-30 | 2002-05-14 | International Business Machines Corporation | Method of forming resist images by periodic pattern removal |
US6274281B1 (en) * | 1999-12-28 | 2001-08-14 | Taiwan Semiconductor Manufacturing Company | Using different transmittance with attenuate phase shift mask (APSM) to compensate ADI critical dimension proximity |
US6541165B1 (en) * | 2000-07-05 | 2003-04-01 | Numerical Technologies, Inc. | Phase shift mask sub-resolution assist features |
-
2001
- 2001-09-13 AU AU2001290937A patent/AU2001290937A1/en not_active Abandoned
- 2001-09-13 WO PCT/US2001/028777 patent/WO2002025373A2/en active Application Filing
- 2001-09-13 US US09/952,185 patent/US6818389B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6818389B2 (en) | 2004-11-16 |
WO2002025373A3 (en) | 2003-04-24 |
WO2002025373A2 (en) | 2002-03-28 |
US20020045136A1 (en) | 2002-04-18 |
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