TW201621730A - Xor邏輯電路 - Google Patents

Xor邏輯電路 Download PDF

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TW201621730A
TW201621730A TW105109797A TW105109797A TW201621730A TW 201621730 A TW201621730 A TW 201621730A TW 105109797 A TW105109797 A TW 105109797A TW 105109797 A TW105109797 A TW 105109797A TW 201621730 A TW201621730 A TW 201621730A
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conductive structure
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貝克史考特Ｔ
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泰拉創新股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

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Abstract

一種互斥或電路包括由第二輸入節點控制的通道閘。當該通道閘受此控制時，其係連接以通過在第一輸入節點的邏輯狀態型式至一輸出節點。一傳輸閘由第一輸入節點控制。當該傳輸閘受此控制時，其係連接以通過在第二輸入節點的邏輯狀態型式至該輸出節點。上拉邏輯由第一與第二輸入節點共同控制。當第一與第二輸入節點皆為高，該上拉邏輯係連接以驅使該輸出節點為低。一種反互斥或電路係定義為相似該互斥或電路，僅不同於該上拉邏輯替換為下拉邏輯，當第一與第二輸入節點皆為高，該下拉邏輯係連接以驅使該輸出節點為高。

Description

XOR邏輯電路
本發明係關於XOR與XNOR邏輯電路及布局。
追求更高的性能與更小的晶粒尺寸驅使半導體產業每兩年約縮減50%的電路晶片面積。晶片面積的縮減提供邁向更新技術之經濟效益。晶片面積縮減50%是藉由縮減25%至30%的特徵尺寸而達成。特徵尺寸的縮減是由於製造設備與材料的進步。舉例來說，更小的特徵尺寸是由於微影製程的進步而達成，而能有更多層的互連層則部分是由於化學機械研磨(CMP, chemical mechanical polishing)的進步。
在微影技術的發展中，隨著最小的特徵尺寸逼近用以曝光特徵形狀的光源波長，非計畫的交互作用發生於鄰近的特徵之間。今日的最小特徵尺寸係縮減至45 nm(奈米)以下，而光微影製程所用的光源波長仍維持在193 nm。最小特徵尺寸與光微影製程所用的光源波長之間的差距係定義為微影間隙(lithographic gap)。微影製程的解析能力隨著微影間隙的增加而減弱。
干擾圖形於光罩上的各形狀與光源交互作用時產生。由鄰近形狀造成的干擾圖形能產生建設性或破壞性干擾。在建設性干擾的情況中，不需要的形狀可能在無意中產生。在破獲性干擾的情況中，預期的形狀可能在無意中移除。在任一情況中，特定形狀以不同於計畫的方式印出，因而可能導致裝置失靈。如光學鄰近效應修正法(OPC, optical proximity correction)的修正方法試圖預測由鄰近形狀造成的影響並修改光罩，致使印刷形狀如預期般製造。光交互作用的預測品質隨著製程幾何的縮小與光交互作用漸趨複雜而低落。
鑒於上述，隨著技術持續朝向更小的半導體元件特徵尺寸發展，尋求電路設計與布局之進步的解決方案，以能改善微影間隙議題之處理。
在一實施例中揭示互斥或(XOR, exclusive-or)邏輯電路。該XOR邏輯電路包括第一輸入節點、第二輸入節點、與一輸出節點。一通道閘係連接以由在第二輸入節點的邏輯狀態控制。當該通道閘由在第二輸入節點的邏輯狀態控制而傳送時，其連接以通過在第一輸入節點的邏輯狀態型式至該輸出節點。一傳輸閘係連接以由在第一輸入節點的邏輯狀態控制，當該傳輸閘由在第一輸入節點的邏輯狀態控制而傳送時，其連接以通過在第二輸入節點的邏輯狀態型式至該輸出節點。上拉邏輯係連接以由在第一輸入節點的邏輯狀態與在第二輸入節點的邏輯狀態共同控制。當在第一輸入節點的邏輯狀態與在第二輸入節點的邏輯狀態兩者皆為高，該上拉邏輯係連接以驅使在該輸出節點的狀態為低。
在一實施例中揭示互斥或(XOR)邏輯電路布局。該XOR邏輯電路布局包括六個PMOS電晶體與五個NMOS電晶體。該五個NMOS電晶體係與該六個PMOS電晶體中的五個分別配對，致使各對NMOS與PMOS電晶體係定義以共享沿著五個閘極軌道中的一個分別佈置之連續閘極結構。該六個PMOS電晶體中的第六個由沿著第六閘極軌道佈置之閘極結構定義，致使第六PMOS電晶體不與該互斥或邏輯電路布局中的另一個電晶體共享第六閘極軌道。該六個閘極軌道係定向為彼此互相平行。
在一實施例中揭示反互斥或(XNOR, exclusive-nor)邏輯電路。該XNOR邏輯電路包括第一輸入節點、第二輸入節點、與一輸出節點。一通道閘係連接以由在第二輸入節點的邏輯狀態控制。當該通道閘由在第二輸入節點的邏輯狀態控制而傳送時，其連接以通過在第一輸入節點的邏輯狀態型式至該輸出節點。一傳輸閘係連接以由在第一輸入節點的邏輯狀態控制。當該傳輸閘由在第一輸入節點的邏輯狀態控制而傳送時，其連接以通過在第二輸入節點的邏輯狀態型式至該輸出節點。下拉邏輯係連接以由在第一輸入節點的邏輯狀態與在第二輸入節點的邏輯狀態共同控制。當在第一輸入節點的邏輯狀態與在第二輸入節點的邏輯狀態兩者皆為低，該下拉邏輯係連接以驅使在該輸出節點的狀態為高。
在一實施例中揭示反互斥或(XNOR)邏輯電路布局。該XNOR邏輯電路布局包括五個PMOS電晶體與六個NMOS電晶體。該五個PMOS電晶體係與該六個NMOS電晶體中的五個分別配對，致使各對PMOS與NMOS電晶體係定義以共享沿著五個閘極軌道中的一個分別佈置之連續閘極結構。該六個NMOS電晶體中的第六個由沿著第六閘極軌道佈置之閘極結構定義，致使第六NMOS電晶體不與該反互斥或邏輯電路布局中的另一個電晶體共享第六閘極軌道。該六個閘極軌道係定向為彼此互相平行。
本發明的其他實施態樣與優點將可藉由本發明實例說明、配合隨後詳細說明與隨附圖式而更加明白。
在下列說明中，為提供對本發明的徹底了解而提出許多具體細節。然而，當可明白熟習本技藝者能在部分或全部具體細節之外實行本發明。在其他情況下，為避免不必要地混淆本發明而未詳細說明熟知的製程作業。習知的XOR電路
圖1A呈現習知的XOR邏輯閘電路(此後稱為「XOR 100」)。該XOR 100包括兩個輸入A與B，以及一個輸出Q。在節點101供給輸入A。在節點102供給輸入B。在節點105供給輸出Q。圖1B-1E呈現XOR的狀態表。如圖1B-1E所示，XOR 100為輸入A與B的多種狀態組合提供相稱狀態的輸出Q。
如圖1A所示，接收輸入A的節點101連接至PMOS電晶體117的閘與NMOS電晶體120的閘。節點101亦連接至反相器110的輸入。反相器110的輸出連接至節點103。節點103連接至PMOS電晶體113的閘與NMOS電晶體116的閘。
節點102連接到PMOS電晶體114的閘與NMOS電晶體119的閘。節點102亦連接至反相器111的輸入。反相器111的輸出連接至節點104。節點104連接至NMOS電晶體115的閘與PMOS電晶體118的閘。
PMOS電晶體113與114在電源供應(VDD)與節點105(供給XOR 100輸出Q)之間串聯。NMOS電晶體115與116在節點105與參考接地電位(GND)之間串聯。PMOS電晶體117與118在電源供應(VDD)與節點105之間串聯。NMOS電晶體119與120在節點105與參考接地電位(GND)之間串聯。
基於上述，習知的XOR 100包括兩組的上拉(pullup)邏輯，其中第一組由PMOS電晶體113與114定義，而第二組由PMOS電晶體117與118定義。XOR 100亦包括兩組下拉(pulldown)邏輯，其中第一組由NMOS電晶體115與116定義，而第二組由NMOS電晶體119與120定義。各組上拉與下拉邏輯皆各由輸入A的型式與輸入B的型式共同控制。因此，習知的XOR 100的電路根據輸入A與B，藉由個別使用上拉邏輯組或是下拉邏輯組而分別定義以驅使輸出Q為高或低。
此外，當知反相器110與111各包括一個PMOS電晶體與一個NMOS電晶體。圖1G係依照先前技術呈現反相器組態之實例。該反相器接收輸入信號A並產生輸出信號Q。該反相器包括一個PMOS電晶體192，其具有連接以受輸入信號A控制的閘、連接電源供應(VDD)的第一端子、以及連接以供給輸出信號Q的第二端子。該反相器亦一個包括NMOS電晶體193，其具有連接以受輸入信號A控制的閘、連接以供給輸出信號Q的第一端子、以及連接參考接地電位(GND)的第二端子。當該反相器的輸入A為高，輸出便為低，反之亦然。基於每個反相器包括一個PMOS電晶體與一個NMOS電晶體，當知習知的XOR 100總共包括6個PMOS電晶體與6個NMOS電晶體。
圖1F係依照本發明的一實施例呈現XOR 100之布局。依照限制閘層布局架構定義XOR 100之布局，如此處說明。在圖1F的布局中，相應標示如前述參照圖1A的各個PMOS與NMOS電晶體。在圖1F的布局中，亦相應標示如前述圖參照1A的各個節點。PMOS電晶體118與NMOS電晶體119的閘極係定義為共線，致使兩閘在閘層中以端點對端點的間隔195分開。並且，PMOS電晶體114與NMOS電晶體115的閘極亦定義為共線，致使兩閘在閘層中以端點對端點的間隔196分開。
當知為布局習知的XOR 100在六個閘極軌道中使用限制閘層架構，在XOR 100的閘層中最少需要具有兩個閘極端點對端點的間隔，如195與196。此類的端點對端點的閘極間隔係依照要求最小的端點對端點的間隔尺寸之適用設計準則而定義。因此，當知相較於不存在端點對端點的閘極間隔，存在端點對端點的閘極間隔要求P-型與N-型擴散區域更加分開，因而要求較大的整體單元高度。XOR 電路與布局實施例
圖3A係依照本發明的一實施例呈現XOR邏輯閘電路300(此後稱為「XOR 300」)。XOR 300包括兩個輸入A與B，以及一個輸出Q。在節點301供給輸入A。在節點302供給輸入B。在節點307供給輸出Q。圖3B-3E係依照本發明的一實施例呈現XOR 300的狀態表。如圖3B-3E所示， XOR 300為輸入A與B的多種狀態組合提供相稱狀態的輸出Q。
如圖3A所示，接收輸入A的節點301連接至反相器310的輸入與PMOS電晶體314的閘兩者。接收輸入B的節點302連接至反相器311的輸入。反相器310的輸出連接至節點303。節點303連接至：1) NMOS電晶體312的第一端子、2) PMOS電晶體316的閘、以及3) NMOS電晶體313的閘。反相器311的輸出連接至節點304。節點304連接至：1) NMOS電晶體312的閘、2) PMOS電晶體315的閘、3) NMOS電晶體313的第一端子、以及4) PMOS電晶體314的第一端子。
節點305連接至下列各點：1) NMOS電晶體312的第二端子、2) NOMS電晶體313的第二端子、3) PMOS電晶體314的第二端子、以及4) PMOS電晶體316的第二端子。PMOS電晶體315的第一端子連接至電源供應(VDD)。PMOS電晶體315的第二端子連接至節點306，其連接至PMOS電晶體316的第一端子。節點305連接至反相器317的輸入。反相器317的輸出連接至節點307，其供給XOR 300的輸出Q。
針對在輸入A與B施加不同的狀態組合，圖3B-3E的狀態表呈現XOR 300的各個節點(節點-301至節點-307)的不同狀態。反相器310、311與317各包括一個PMOS電晶體與一個NNOS電晶體。因此，相對於共包括六個PMOS電晶體與六個NMOS電晶體的習知XOR 100，XOR 300共包括六個PMOS電晶體與五個NMOS電晶體，因而省下一個NMOS電晶體。
該2-輸入XOR 300係定義為處理輸入A與B的四個獨特組合，如圖3B-3E所描述。具體而言，NMOS電晶體313與PMOS電晶體314一起定義由輸入A控制的傳輸閘(transmission gate)350。當輸入A的狀態為低，即邏輯0，傳輸閘350促使控制輸出Q的狀態，致使輸出Q的狀態的符合輸入B的狀態。NMOS電晶體312定義由輸入B控制的通道閘(pass gate)360。當輸入B的狀態為低，即邏輯0，通道閘360促使控制輸出Q的狀態，致使輸出Q的狀態符合輸入A的狀態。
PMOS電晶體315與316一起定義由輸入A與B共同控制的上拉邏輯370。當輸入A的狀態與輸入B的狀態皆為高，即邏輯1，傳輸閘350與通道閘360皆失效，而上拉邏輯370控制輸出Q的狀態，致使輸出Q的狀態為低，即邏輯0。當輸入A與B的其中一個狀態為低，即邏輯0，上拉邏輯370失效。
XOR 300係定義為下列之一： l  經由輸入B所控制的通道閘360，通過輸入A的狀態型式至輸出Q， l  經由輸入A所控制的傳輸閘350，通過輸入B的狀態型式至輸出Q， l  在輸入A與B共同控制下，經由上拉邏輯370驅使輸出Q的狀態為低。
依照前述，XOR邏輯電路300包括第一輸入A節點301、第二輸入B節點302、以及輸出Q節點307。通道閘360係連接以藉由在第二輸入節點302的邏輯狀態控制。當通道閘360藉由在第二輸入節點302的邏輯狀態控制而傳送時，其連接以通過在第一輸入節點301的邏輯狀態型式至輸出節點307。傳輸閘350係連接以藉由在第一輸入節點301的邏輯狀態控制。當傳輸閘350藉由在第一輸入節點301的邏輯狀態控制而傳送時，其連接以通過在第二輸入節點302的邏輯狀態型式至輸出節點307。上拉邏輯370係連接以藉由在第一輸入節點301的邏輯狀態與在第二輸入節點302的邏輯狀態共同控制。當在第一輸入節點301的邏輯狀態與在第二輸入節點302的邏輯狀態皆為高時，上拉邏輯370連接以驅使在輸出節點307的狀態為低。
圖3F係依照本發明的一實施例呈現XOR 300之布局。在一實施例中，依照限制閘層布局架構定義XOR 300之布局，如此處說明。反相器310由PMOS電晶體310P與NMOS電晶體310N定義，兩者共享沿單閘極軌道380定義的連續閘極結構310G。反相器311係由PMOS電晶體311P與NMOS電晶體311N定義，兩者共享沿單閘極軌道384定義的連續閘極結構311G。反相器317係由PMOS電晶體317P與NMOS電晶體317N定義，兩者共享沿單閘極軌道385定義的連續閘極結構317G。
上拉邏輯370的PMOS電晶體315與通道閘360的NMOS電晶體312共享沿單閘極軌道381定義的連續閘極結構381G。上拉邏輯370的PMOS電晶體316與傳輸閘350的NMOS電晶體313共享沿單閘極軌道382定義的連續閘極結構382G。傳輸閘350的PMOS電晶體314係沿單閘極軌道383定義。節點301-307係藉由接觸點、互連結構(M1、M2)與穿孔(Via1)的多種組合而定義在XOR 300之布局上，以構成如圖3A所示的多個電晶體之間的連接。
當XOR 300的布局係依照限制閘極架構定義時，當知其係使用六個鄰近的閘極軌道(380-385)定義。在一實施例中，六個鄰近的閘極軌道(380-385)為等距分開。然而，在另一實施例中，可使用不同的垂直間隔分開六個鄰近的閘極軌道(380-385)。並且，當XOR 300的布局係依照限制閘極架構定義時，當知其並不要求佈置閘極線的端點為彼此相對。換句話說，在XOR 300布局中沒有閘極結構沿著任何特定閘極軌道佈置為端點對端點。在閘極特徵之間製造端點對端點的間隔之相關微影技術困難因而避免。
並且，因為在P-型擴散區域與N-型擴散區域之間沒有沿著特定閘極軌道放置端點對端點的閘極間隔，所以不需如佈置/製造端點對端點的閘極間隔之相關設計準則所規定一般，迫使P-型擴散區域與N-型擴散區域之間的垂直布局空間需符合最小尺寸要求。所以若是某些實施例期望，XOR 300布局的整體單元高度(即VDD與GND之間的垂直距離)能夠藉由安排P-型與N-型擴散區域更加接近而減少。
另外，雖然圖3A與3F的示範性實施例呈現上拉邏輯370係定義為使PMOS電晶體315的閘連接至第二輸入反相器311的輸出，且使PMOS電晶體316的閘連接至第一輸入反相器310的輸出，但當知可顛倒PMOS電晶體315與316之堆疊。具體而言，在一實施例中，上拉邏輯370係定義為使PMOS電晶體315的閘連接至第一輸入反相器310的輸出，且使PMOS電晶體316的閘連接到第二輸入反相器311的輸出。XNOR 電路與布局實施例
圖2A係依照本發明的一實施例呈現XNOR邏輯閘電路(此後稱為「XNOR 200」)。XNOR 200包括兩個輸入A與B，以及一個輸出Q。在節點201供給輸入A。在節點202供給輸入B。在節點207供給輸出Q。圖2B-2E係依照發明的一實施例呈現XNOR 200的狀態表。如圖2B-2E所示，XNOR 200為輸入A與B的多種狀態組合提供相稱狀態的輸出Q。
如圖2A所示，接收輸入A的節點201連接至反相器210的輸入與NMOS電晶體214的閘。接收輸入B的節點202連接至反相器211的輸入。反相器210的輸出連接至節點203。節點203連接至：1) PMOS電晶體212的第一端子、2) PMOS電晶體213的閘、以及3) NMOS電晶體215的閘。反相器211的輸出連接至節點204。節點204連接至：1) PMOS電晶體212的閘、2) NMOS電晶體216的閘、3) PMOS電晶體213的第一端子、以及4) NMOS電晶體214的第一端子。
節點205連接至下列各點：1) PMOS電晶體212的第二端子、2) PMOS電晶體213的第二端子、3) NMOS電晶體214的第二端子、以及4) NMOS電晶體215的第二端子。NMOS電晶體216的第一端子連接至參考接地電位(GND)。NMOS電晶體216的第二端子連接至節點206，其連接至NMOS電晶體215的第一端子。節點205連接至反相器207的輸入。反相器217的輸出連接至節點207，其供給XNOR 200的輸出Q。針對在輸入A與B施加不同的狀態組合，圖2B-2E的狀態表呈現XNOR 200的各個節點(節點-201至節點-207)之不同狀態。反相器210、211與217各包括一個PMOS電晶體與一個NMOS電晶體。因此，XNOR 200共包括五個PMOS電晶體與六個NMOS電晶體。
該2-輸入XNOR係定義以處理輸入A與B的四個獨特組合，如圖2B-2E所描繪。具體而言，PMOS電晶體213與NMOS電晶體214一起定義由輸入A控制的傳輸閘250。當輸入A的狀態為高，即邏輯1，傳輸閘250促使控制輸出Q的狀態，致使輸出Q的狀態符合輸入B的狀態。PMOS電晶體212定義由輸入B控制的通道閘260。當輸入B的狀態為高，即邏輯1，通道閘260促使控制輸出Q的狀態，致使輸出Q的狀態符合輸入A的狀態。
NMOS電晶體215與216一起定義由輸入A與B共同控制的下拉邏輯270。當輸入A的狀態與輸入B的狀態皆為低，即邏輯0，傳輸閘250與通道閘260兩者皆失效，而下拉邏輯270控制輸出Q的狀態，致使輸出Q的狀態為高，即邏輯1。當輸入A與B的其中一個狀態為高，即邏輯1，下拉邏輯270便失效。
基於前述，XNOR 200係定義為下列之一： l  經由輸入B所控制的通道閘260，通過輸入A的狀態型式至輸出Q， l  經由輸入A所控制的傳輸閘250，通過輸入B的狀態型式至輸出Q， l  在輸入A與B共同控制下，經由下拉邏輯270驅使輸出Q的狀態為高。
依照前述，XNOR邏輯電路200包括第一輸入A節點201、第二輸入B節點202、以及輸出Q節點207。通道閘260係連接以藉由在第二輸入節點202的邏輯狀態控制。當通道閘260係藉由在第二輸入節點202的邏輯狀態控制而傳輸時，其連接以通過在第一輸入節點201的邏輯狀態型式至輸出節點207。傳輸閘250係連接以藉由在第一輸入節點201的邏輯狀態控制。當傳輸閘250係藉由在第一輸入節點201的邏輯狀態控制而傳輸時，其連接以通過在第二輸入節點202的邏輯狀態型式至輸出節點207。下拉邏輯217係連接以藉由在第一輸入節點201的邏輯狀態與在第二輸入節點202的邏輯狀態共同控制。當在第一輸入節點201的邏輯狀態與在第二輸出節點202的邏輯狀態皆為低，下拉邏輯270係連接以驅使在輸出節點207的狀態為高。
圖2F係依照本發明的一實施例呈現XNOR 200之布局。在一實施例中，根據限制閘層布局架構定義XNOR 200之布局，如此處說明。反相器210係藉由PMOS電晶體210P與NMOS電晶體210N定義，兩者共享沿單閘極軌道280定義的連續閘極結構210G。反相器211係藉由PMOS電晶體211P與NMOS電晶體211N定義，兩者共享沿單閘極軌道284定義的連續閘極結構211G。反相器217係藉由PMOS電晶體217P與NMOS電晶體217N定義，兩者共享沿單閘極軌道285定義的連續閘極結構217G。
下拉邏輯270的NMOS電晶體216與通道閘260的PMOS電晶體212共享沿單閘極軌道281定義的連續閘極結構281G。下拉結構270的NMOS電晶體215與傳輸閘250的PMOS電晶體213共享沿單閘極軌道282定義的連續閘極結構282G。傳輸閘250的NMOS電晶體214係定義為沿單閘極軌道283。節點201-207係藉由接觸點、互連結構(M1、M2)與穿孔(Via1)的多種組合而定義在XNOR 200的布局上，以構成如圖2A所示的多個電晶體之間的連接。
當依照限制閘極架構定義XNOR 200之布局時，當知其係使用六個鄰近的閘極軌道(280-285)而定義。在一實施例中，六個鄰近的閘極軌道(280-285)為等距分開。然而，在另一實施例中，可使用不同的垂直間隔分開六個鄰近的閘極軌道(280-285)。並且，當依照限制閘極架構定義XNOR 200之布局時，當知其並不要求佈置閘極線的端點為彼此相對。換句話說，在XNOR 200布局中沒有閘極結構沿著任何特定閘極軌道佈置為端點對端點。在閘極特徵之間製造端點對端點的間隔之相關微影技術的困難因而避免。
並且，因為在P-型擴散區域與N-型擴散區域之間沒有沿著特定閘極軌道放置端點對端點的閘極間隔，所以不需如佈置/製造端點對端點的閘極間隔之相關設計準則所規定一般，迫使P-型擴散區域與N-型擴散區域之間的垂直布局空間需符合最小尺寸要求。所以若是某些實施例期望，XNOR 200布局的整體單元高度(即VDD與GND之間的垂直距離)能夠藉由安排P-型與N-型擴散區域更加接近而減少。
當知如此處說明之XOR 300電路與相關布局可藉由移除輸出反相器317而轉換成XNOR電路與相關布局。在此轉換過的組態中，輸出節點307變成等同於節點305，且輸出Q以及輸入A與輸入B之間的關係就如同針對XNOR 200的圖2B-2E之狀態表所示。
當知如此處說明之XNOR 200電路與相關布局可藉由移除輸出反相器217而轉換成XOR電路與相關布局。在此轉換過的組態中，輸出節點207變成等同於節點205，且輸出Q以及輸入A與輸入B之間的關係就如同針對XOR 300的圖3B-3E之狀態表所示。
另外，雖然圖2A與2F的示範性實施例呈現下拉邏輯270係定義為使NMOS電晶體216的閘連接至第二輸入反相器211的輸出，且使NMOS電晶體215的閘連接至第一輸入反相器210的輸出，但當知可顛倒NMOS電晶體215與216之堆疊。具體來說，在一實施例中，下拉邏輯270係定義為使NMOS電晶體216的閘連接至第一輸入反相器210的輸出，且使NMOS電晶體215的閘連接至第二輸入反相器211的輸出。限制閘層布局架構
如上述所提，本發明的XOR 300與XNOR 200電路可在半導體晶片的一部分中以限制閘層布局架構完成。閘層中，定義數個平行的虛擬線延伸橫越該布局。因為這些平行的虛擬線在布局中用以標示各個電晶體的閘極之佈置，所以稱作閘極軌道。在一實施例中，形成閘極軌道的平行虛擬線係由線間的垂直間隔定義，其與特定閘極間距(pitch)等長。因此，閘極段在閘極軌道上的佈置相應於特定閘極間距。在另一實施例中，閘極軌道係以大於或等於特定閘極間距之可變間距而分開。
圖4A係依照本發明的一實施例呈現閘極軌道401A-401E之實例，其係定義於限制閘層布局架構中。閘極軌道401A-401E係由平行虛擬線形成，其延伸橫越晶片的閘層布局，且具有與特定閘極間距407等長之線間的垂直間隔。為了說明起見，互補擴散區域403與405係呈現在圖4A中。當知擴散區域403與405係定義在閘層之下的擴散層中。並且，當知擴散區域403與405係藉由實例提供，並非限制性地代表關於限制閘層布局架構之擴散層中的擴散區域尺寸、形狀、以及/或是佈置。
在限制閘層布局架構中，定義閘層特徵布局通道在特定閘極軌道的附近，使其延伸介於與該特定閘極軌道相鄰的閘極軌道之間。舉例來說，閘層特徵布局通道401A-1至401E-1係個別定義在閘極軌道401A至401E的附近。當知各閘極軌道具有相應的閘層特徵布局通道。並且，對於位在相鄰已定的布局空間邊緣(例如相鄰單元邊界)之閘極軌道，該相應閘層特徵布局通道以如同該已定的布局空間外側有虛擬閘極軌道一般延伸，如閘層特徵布局通道401A-1與401E-1所描繪。此外當知各閘層特徵布局通道係定義為沿其相應閘極軌道的整個長度延伸。所以，各閘層特徵布局通道係定義為在該閘層布局相關的晶片部分中，延伸橫越該閘層布局。
在限制閘層布局架構中，特定閘極軌道相關的閘層特徵係定義在該特定閘極軌道相關的閘層特徵布局通道中。連續閘層特徵可包括定義電晶體閘極的部分，以及未定義電晶體閘極的部份。所以，連續閘層特徵可延伸通過下層晶片層的擴散區域與介電區域。
在一實施例中，形成電晶體閘極的各閘層特徵部分係位於特定閘極軌道的實質中心上。此外，在此實施例中，未形成電晶體閘極的閘層特徵部分可位於特定閘極軌道相關的閘層特徵布局通道中。因此，特定閘層特徵基本上可定義在特定閘層特徵布局通道中的任何地方，只要特定閘層的閘極部分是位於相應特定閘層特徵布局通道的閘極軌道中心上，而且只要相對於鄰近的閘層布局通道中的其他閘層特徵，特定閘層特徵符合設計準則的間隔要求。另外，與鄰近閘極軌道相關的閘層特徵布局通道中所定義的閘層特徵之間禁止有實際接觸。
圖4B係依照本發明的一實施例，以定義於架構中之數個示範性閘層特徵409-423呈現圖4A的示範性限制閘層布局架構。閘層特徵409係定義在與閘極軌道401A相關的閘層特徵布局通道401A-1中。閘層特徵409的閘極部分係在閘極軌道401A的實質中心上。並且，閘層特徵409的非閘極部分與定義在鄰近的閘層特徵布局通道401B-1中的閘層特徵411與413保持設計準則的間距要求。相似地，閘層特徵411-423係定義在各自的閘層特徵布局通道中，並令其閘極部分在相應個別閘層特徵布局通道的閘極軌道之實質中心上。並且，當知各閘層特徵411-423與定義在鄰近的閘層特徵布局通道中的閘層特徵保持設計準則的間距要求，並避免與定義在鄰近的閘層特徵布局通道中之其他任何閘層特徵有實際接觸。
閘極相應延伸通過擴散區域的各閘層特徵的一部分，其中各閘層特徵係定義其整體在閘層特徵布局通道中。各閘層特徵係定義在其閘層特徵布局通道中，而未與定義在鄰近的閘層特徵布局通道中的其他閘層特徵有實際接觸。如圖4B的閘層特徵布局通道401A-1至401E-1之實例所描繪，各閘層特徵布局通道與特定閘極軌道相關並對應於一布局區域，其沿該特定閘極軌道延伸，並從該特定閘極軌道之各個相對方向垂直向外延伸至最近的鄰近閘極軌道或布局邊界外側的虛擬閘極軌道。
某些閘層特徵可能具有一個以上的接觸頭部分，其定義在沿其長度的任何數量的位置上。定義特定閘層特徵的接觸頭部分作為閘層特徵段，其具有足夠尺寸的高度與寬度以容納閘接觸(gate contact)結構，其中「寬度」係定義為以特定閘層特徵的閘極軌道之垂直方向橫越基板，而其中「高度」係定義為以特定閘層特徵的閘極軌道之平行方向橫越基板。當知從上觀之時，閘層特徵的接觸頭本質上能以任何布局形狀定義，包括正方形或長方形。並且，根據布局要求與電路設計，閘層特徵的特定接觸頭部分可能或可能不具有以上定義的閘接觸。
如上討論，此處揭示的多個實施例之閘層係定義為限制閘層。某些閘層特徵形成電晶體元件的閘極。其他的閘層特徵可形成為在閘層中延伸於兩點之間的導電段。並且，其他的閘層特徵可能對於積體電路作業不具功能。當知無論其功能為何，各閘層特徵係定義為在其個別閘層特徵布局通道中延伸橫越該閘層，而與定義在鄰近的閘層特徵布局通道中之其他閘層特徵無實際接觸。
在一實施例中，閘層特徵係定義為提供有限數量的受控布局形狀對形狀之微影交互作用，其可準確預測並最適化製造與設計過程。在該實施例中，閘層特徵係定義以避免布局形狀-對-布局形狀之空間關係，其會在布局中引起不良的微影交互作用，使其無法以高機率準確預測與減緩。然而，當知在微影交互作用為可預測與可管理時，可接受相應的閘層特徵布局通道中的閘層特徵方向改變。
無論其功能為何，當知各閘層特徵係定義為沒有任何閘層特徵會在未利用非閘層特徵下，配置成在閘層中沿著特定閘極軌道直接連接至沿不同閘極軌道定義的其他閘極特徵。再者，佈置在不同閘極軌道相關的不同閘層布局通道中的閘層特徵之間的各個連接為透過一個以上的非閘層特徵(可由較高的互連層定義)，即透過該閘層之上的一個以上之互連層，或是藉由在該閘層或閘層之下的局部互連特徵。
當知如此處揭示的XOR 300與XNOR 200電路與布局能以實體型式儲存，如電腦可讀取媒體中的數位格式。舉例來說，如此處揭示的XOR 300以及/或是XNOR 200電路之布局能以一個以上的單元(可從一個以上的公用程式(libraries)單元中選擇)儲存於布局資料檔案中。該布局檔案資料可格式化為GDS II (圖形資料系統，Graphic Data System)資料庫資料、OASIS (開放原圖系統交換標準，Open Artwork System Interchange Standard)資料庫檔案、或是其他適合儲存與傳輸半導體裝置布局的資料檔案格式之型式。並且，XOR 300以及/或是XNOR 200電路之多層布局能被包括在較大半導體元件的多層布局中。較大半導體元件的多層布局亦能以如上標明的布局資料檔案儲存。
並且，此處說明的本發明能以電腦可讀代碼收錄在電腦可讀取媒體中。舉例來說，電腦可讀代碼能包括儲存XOR 300以及/或是XNOR 200電路布局的布局資料檔案。電腦可讀代碼亦能包括程式指令，其用以選擇一個以上包括XOR 300以及/或是XNOR 200電路布局之布局公用程式以及/或是單元。該布局公用程式以及/或是單元亦能以數位格式儲存在電腦可讀取媒體中。
此處提及的電腦可讀取媒體為任何一種資料儲存元件，其能儲存之後由電腦系統讀取的資料。電腦可讀取媒體之實例包括硬碟、網路附加儲存設備(NAS, network attached storage)、唯讀記憶體、隨機存取記憶體、CD-ROMs、CD-Rs、CD-RWs、磁帶、以及其他光學與非光學資料儲存元件。該電腦可讀取媒體亦能分散至多台電腦系統的網路，使得該電腦可讀代碼以分散方式儲存與執行。
此處說明形成本發明一部分的任一作業皆為有用的機器作業。本發明亦關於執行這些作業的元件或裝置。該裝置能為特定目的而專門建構，例如專用目的電腦。當定義為專用目的電腦時，該電腦亦能執行其他不屬專用目的部分之處理、程式執行或常用程式，而仍然能為專用目的運作。或者，該作業能藉由通用目的電腦處理，其由儲存在電腦記憶體、快取記憶體、或透過網路取得之一個以上的電腦程式而選擇性啟動或配置。當透過網路取得資料時，該資料可能藉由網路上的其他電腦處理，如雲端運算資源。
本發明實施例亦可定義為從一狀態轉換資料至另一狀態之機器。該資料可能代表一個項目(article)，其可由電子信號與電子操作資料作為代表。在某些情況下，轉換的資料能形象化地描繪在顯示器上，代表資料轉換結果之實際物件。轉換的資料能一般性地儲存在儲存裝置中，或是透過能建構或描繪實際且實體的物件之特定型式。在某些實施例中，該操作可藉由處理器執行。在此類實例中，該處理器依此從一物轉換資料至另一物。除此之外，該方法能以一台以上能透過網路連接的機器或處理器處理。各機器能從一狀態或一物轉換資料至另一個，且亦能處理資料、儲存資料至儲存裝置、透過網路傳送資料、顯示結果、或是傳輸結果至另一台機器。
進一步當知如此處揭示的XOR 300與XNOR 200電路與布局能以半導體元件或晶片的一部分來製造。在如積體電路、記憶單元等等的半導體元件之製造中，執行一連串的製造作業以定義在半導體晶圓上的特徵。該晶圓包括以多層結構型式定義在矽基板的積體電路元件。在基板層中形成含擴散區域的電晶體元件。在後續層中，互連金屬線被圖形化並電氣連接至該電晶體元件以定義預期的積體電路元件。並且，圖形化的導體層以介電材料與其他導體層絕緣。
雖然已透過多個實施例說明本發明，然而應當知悉熟悉此技藝者將可藉由閱讀前述說明內容與研讀圖式而實現本發明的各種變化、新增、置換與等同者。因此，本發明意圖包括落在本發明的真實精神與範疇下的所有此類變化、新增、置換與等同者。
100‧‧‧習知的XOR邏輯閘電路
101~105‧‧‧節點
110、111‧‧‧反相器
113、114、117、118、192‧‧‧PMOS電晶體
115、116、119、120、193‧‧‧NMOS電晶體
195、196‧‧‧間隔
200‧‧‧XNOR邏輯閘電路
201~207‧‧‧節點
210、211、217‧‧‧反相器
212、213、210P、211P、217P‧‧‧PMOS電晶體
214、215、216、210N、211N、211P‧‧‧NNOS電晶體
210G、211G、217G、281G、282G、283G‧‧‧連續閘極結構
280~285‧‧‧閘極軌道
250‧‧‧傳輸閘
260‧‧‧通道閘
270‧‧‧下拉邏輯
300‧‧‧XOR邏輯閘電路
301~307‧‧‧節點
310、311、317‧‧‧反相器
314、315、316、310P、311P、317P‧‧‧PMOS電晶體
312、313、310N、311N、317N‧‧‧NMOS電晶體
310G、311G、317G、381G、382G‧‧‧連續閘極結構
380~385‧‧‧閘極軌道
350‧‧‧傳輸閘
360‧‧‧通過閘
370‧‧‧上拉邏輯
403、405‧‧‧擴散區域
401A~401E‧‧‧閘極軌道
401A-1~401E-1‧‧‧閘層特徵布局通道
407‧‧‧閘極間距
409、411、413、415、417、419、421、423‧‧‧閘層特徵
A、B‧‧‧輸入
Q‧‧‧輸出
GND‧‧‧參考接地電位
VDD‧‧‧電源供應
M1、M2‧‧‧互連結構
圖1A呈現習知的XOR邏輯閘電路；
圖1B-1E呈現圖1A的習知XOR邏輯閘電路之狀態表；
圖1F係依照本發明的一實施例呈現習知XOR之布局；
圖1G係依照先前技術呈現反相器組態之實例；
圖2A係依照本發明的一實施例呈現XNOR邏輯閘電路；
圖2B-2E係依照本發明的一實施例呈現圖2A的XNOR邏輯閘電路之狀態表；
圖2F係依照本發明的一實施例呈現圖2A的XNOR邏輯閘電路之布局；
圖3A係依照本發明的一實施例呈現XOR邏輯閘電路；
圖3B-3E係依照本發明的一實施例呈現圖3A的XOR邏輯閘電路之狀態表；
圖3F係依照本發明的一實施例呈現圖3A的XOR邏輯閘電路之布局；
圖4A係依照本發明的一實施例呈現定義在限制閘層布局架構中的閘極軌道之實例；以及
圖4B係依照本發明的一實施例呈現圖4A的示範性限制閘層布局架構，其具有數個定義在其中的示範性閘層特徵。
300‧‧‧XOR邏輯閘電路
301~307‧‧‧節點
310、311、317‧‧‧反相器
314、315、316、310P、311P、317P‧‧‧PMOS電晶體
312、313、310N、311N、317N‧‧‧NMOS電晶體
310G、311G、317G、381G、382G‧‧‧連續閘極結構
380~385‧‧‧閘極軌道
350‧‧‧傳輸閘
360‧‧‧通過閘
370‧‧‧上拉邏輯

Claims (17)

  1. 一種互斥或(exclusive-or)電路，包含： 一第一線形導電結構，其包含形成第一電晶體類型之第一電晶體之閘極電極的部分，該第一電晶體類型之第一電晶體係部份地藉由第一擴散類型之第一共享擴散區域而形成； 一第二線形導電結構，其包含形成第二電晶體類型之第一電晶體之閘極電極的部分，該第二電晶體類型之第一電晶體係部份地藉由第二擴散類型之第一共享擴散區域而形成； 一第三線形導電結構，其包含形成該第一電晶體類型之第二電晶體之閘極電極的部分，該第一電晶體類型之第二電晶體係部份地藉由該第一擴散類型之第一共享擴散區域而形成； 一第四線形導電結構，其包含形成該第二電晶體類型之第二電晶體之閘極電極的部分，該第二電晶體類型之第二電晶體係部份地藉由該第二擴散類型之第一共享擴散區域而形成； 一第一互連層導電結構，其形成該第一線形導電結構與該第四線形導電結構之間的電連接部分； 一第二互連層導電結構，其形成該第二線形導電結構與該第三線形導電結構之間的電連接部分；及 一第三互連層導電結構，其形成該第一擴散類型之第一共享擴散區域與該第二擴散類型之第一共享擴散區域之間的電連接部分。
  2. 如申請專利範圍第1項所述之互斥或電路，其中該第一互連層導電結構係與該第二互連層導電結構電絕緣。
  3. 如申請專利範圍第1項所述之互斥或電路，其中該第一互連層導電結構及該第二互連層導電結構係形成於相同的互連層中。
  4. 如申請專利範圍第1項所述之互斥或電路，其中該第一電晶體類型之第一電晶體及該第一電晶體類型之第二電晶體藉由不形成任何電晶體之源極或汲極的一內區域而集體與該第二電晶體類型之第一電晶體及該第二電晶體類型之第二電晶體分開。
  5. 如申請專利範圍第4項所述之互斥或電路，更包含： 一第一接觸結構，形成為實際接觸該第一線形導電結構； 一第二接觸結構，形成為實際接觸該第二線形導電結構； 一第三接觸結構，形成為實際接觸該第三線形導電結構；及 一第四接觸結構，形成為實際接觸該第四線形導電結構。
  6. 如申請專利範圍第5項所述之互斥或電路，其中該第一互連層導電結構係形成為實際接觸該第一接觸結構。
  7. 如申請專利範圍第6項所述之互斥或電路，其中該第一線形導電結構包含一外部分，其自該第一線形導電結構的形成該第一電晶體類型之第一電晶體之閘極電極的部分及自該內區域延伸離開，且其中該第一接觸結構係定位成實際接觸該第一線形導電結構的該外部分。
  8. 如申請專利範圍第7項所述之互斥或電路，其中該第一互連層導電結構係形成為實際接觸該第四接觸結構。
  9. 如申請專利範圍第8項所述之互斥或電路，其中該第四線形導電結構包含一外部分，其自該第四線形導電結構的形成該第二電晶體類型之第二電晶體之閘極電極的部分及自離開該內區域延伸離開，且其中該第四接觸結構係定位成實際接觸該第四線形導電結構的該外部分。
  10. 如申請專利範圍第9項所述之互斥或電路，其中該第二互連層導電結構係形成為實際接觸該第二接觸結構。
  11. 如申請專利範圍第10項所述之互斥或電路，其中該第二線形導電結構包含一內部分，其自該第二線形導電結構的形成該第二電晶體類型之第一電晶體之閘極電極的部分延伸離開、並延伸於該內區域上方，且其中該第二接觸結構係定位成實際接觸該第二線形導電結構的該內部分。
  12. 如申請專利範圍第11項所述之互斥或電路，其中該第三互連層導電結構係形成為實際接觸該第三接觸結構。
  13. 如申請專利範圍第12項所述之互斥或電路，其中該第三線形導電結構包含一內部分，其自該第三線形導電結構的形成該第一電晶體類型之第二電晶體之閘極電極的部分延伸離開、並延伸於該內區域上方，且其中該第三接觸結構係定位成實際接觸該第三線形導電結構的該內部分。
  14. 如申請專利範圍第1項所述之互斥或電路，其中該第一線形導電結構之長度方向中心線及該第二線形導電結構之長度方向中心線係共同對準。
  15. 如申請專利範圍第14項所述之互斥或電路，其中該第三線形導電結構之長度方向中心線及該第四線形導電結構之長度方向中心線係共同對準。
  16. 如申請專利範圍第15項所述之互斥或電路，其中該第一線形導電結構係藉由一第一端點對端點間隔而與該第二線形導電結構分開。
  17. 如申請專利範圍第16項所述之互斥或電路，其中該第三線形導電結構係藉由一第二端點對端點間隔而與該第四線形導電結構分開，其中該第一端點對端點間隔及該第二端點對端點間隔具有相同尺寸。
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